From 01218af77f6b1ebd965b2decbfa9d289896d607f Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 17 Apr 2015 09:50:21 +0000 Subject: [PATCH] [mips] Move ABI-dependent register selections to MipsABIInfo. NFC. Summary: For example, a common idiom was 'isN64 ? Mips::SP_64 : Mips::SP'. This has been moved to MipsABIInfo and replaced with 'ABI.GetStackPtr()'. There are others that should also be moved. This patch sticks to the ones that are obviously non-functional. The others have minor mistakes that need fixing at the same time, mostly involving checks for 64-bit GPR's instead of checks for 64-bit pointers. Reviewers: tomatabacu Reviewed By: tomatabacu Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8972 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235173 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 32 +++++++++++ lib/Target/Mips/MCTargetDesc/MipsABIInfo.h | 10 ++++ lib/Target/Mips/MipsRegisterInfo.cpp | 4 +- lib/Target/Mips/MipsSEFrameLowering.cpp | 58 +++++++++----------- lib/Target/Mips/MipsSEInstrInfo.cpp | 9 +-- lib/Target/Mips/MipsSERegisterInfo.cpp | 20 +++---- 6 files changed, 84 insertions(+), 49 deletions(-) diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index faf974198ca..b1f7c2f2259 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -90,3 +90,35 @@ MipsABIInfo MipsABIInfo::computeTargetABI(Triple TT, StringRef CPU, .Case("octeon", MipsABIInfo::N64()) .Default(MipsABIInfo::Unknown()); } + +unsigned MipsABIInfo::GetStackPtr() const { + return ArePtrs64bit() ? Mips::SP_64 : Mips::SP; +} + +unsigned MipsABIInfo::GetFramePtr() const { + return ArePtrs64bit() ? Mips::FP_64 : Mips::FP; +} + +unsigned MipsABIInfo::GetNullPtr() const { + return ArePtrs64bit() ? Mips::ZERO_64 : Mips::ZERO; +} + +unsigned MipsABIInfo::GetPtrAdduOp() const { + return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; +} + +unsigned MipsABIInfo::GetPtrAddiuOp() const { + return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu; +} + +unsigned MipsABIInfo::GetEhDataReg(unsigned I) const { + static const unsigned EhDataReg[] = { + Mips::A0, Mips::A1, Mips::A2, Mips::A3 + }; + static const unsigned EhDataReg64[] = { + Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64 + }; + + return IsN64() ? EhDataReg64[I] : EhDataReg[I]; +} + diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index 008e08ecfde..9a6ba946765 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -19,6 +19,7 @@ namespace llvm { class MCTargetOptions; class StringRef; +class TargetRegisterClass; class MipsABIInfo { public: @@ -61,6 +62,15 @@ public: bool operator<(const MipsABIInfo Other) const { return ThisABI < Other.GetEnumValue(); } + + unsigned GetStackPtr() const; + unsigned GetFramePtr() const; + unsigned GetNullPtr() const; + unsigned GetPtrAdduOp() const; + unsigned GetPtrAddiuOp() const; + inline bool ArePtrs64bit() const { return IsN64(); } + + unsigned GetEhDataReg(unsigned I) const; }; } diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 0ea48b19891..f72fb4d622e 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -50,8 +50,8 @@ unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } const TargetRegisterClass * MipsRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) const { - const MipsSubtarget &Subtarget = MF.getSubtarget(); - return Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + MipsABIInfo ABI = MF.getSubtarget().getABI(); + return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; } unsigned diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index 23feb5c3861..e9a206170a6 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -364,17 +364,6 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) : MipsFrameLowering(STI, STI.stackAlignment()) {} -unsigned MipsSEFrameLowering::ehDataReg(unsigned I) const { - static const unsigned EhDataReg[] = { - Mips::A0, Mips::A1, Mips::A2, Mips::A3 - }; - static const unsigned EhDataReg64[] = { - Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64 - }; - - return STI.isABI_N64() ? EhDataReg64[I] : EhDataReg[I]; -} - void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -387,10 +376,11 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; - unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; - unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; - unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned ADDu = ABI.GetPtrAdduOp(); // First, compute final stack size. uint64_t StackSize = MFI->getStackSize(); @@ -473,21 +463,21 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { } if (MipsFI->callsEhReturn()) { - const TargetRegisterClass *RC = STI.isABI_N64() ? - &Mips::GPR64RegClass : &Mips::GPR32RegClass; + const TargetRegisterClass *PtrRC = + ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; // Insert instructions that spill eh data registers. for (int I = 0; I < 4; ++I) { - if (!MBB.isLiveIn(ehDataReg(I))) - MBB.addLiveIn(ehDataReg(I)); - TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false, - MipsFI->getEhDataRegFI(I), RC, &RegInfo); + if (!MBB.isLiveIn(ABI.GetEhDataReg(I))) + MBB.addLiveIn(ABI.GetEhDataReg(I)); + TII.storeRegToStackSlot(MBB, MBBI, ABI.GetEhDataReg(I), false, + MipsFI->getEhDataRegFI(I), PtrRC, &RegInfo); } // Emit .cfi_offset directives for eh data registers. for (int I = 0; I < 4; ++I) { int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); - unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true); + unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); unsigned CFIIndex = MMI.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) @@ -521,10 +511,11 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, *static_cast(STI.getRegisterInfo()); DebugLoc dl = MBBI->getDebugLoc(); - unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; - unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; - unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; - unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; + MipsABIInfo ABI = STI.getABI(); + unsigned SP = ABI.GetStackPtr(); + unsigned FP = ABI.GetFramePtr(); + unsigned ZERO = ABI.GetNullPtr(); + unsigned ADDu = ABI.GetPtrAdduOp(); // if framepointer enabled, restore the stack pointer. if (hasFP(MF)) { @@ -539,8 +530,8 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, } if (MipsFI->callsEhReturn()) { - const TargetRegisterClass *RC = STI.isABI_N64() ? - &Mips::GPR64RegClass : &Mips::GPR32RegClass; + const TargetRegisterClass *RC = + ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; // Find first instruction that restores a callee-saved register. MachineBasicBlock::iterator I = MBBI; @@ -549,8 +540,8 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, // Insert instructions that restore eh data registers. for (int J = 0; J < 4; ++J) { - TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J), - RC, &RegInfo); + TII.loadRegFromStackSlot(MBB, I, ABI.GetEhDataReg(J), + MipsFI->getEhDataRegFI(J), RC, &RegInfo); } } @@ -612,7 +603,8 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineRegisterInfo &MRI = MF.getRegInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); - unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; + MipsABIInfo ABI = STI.getABI(); + unsigned FP = ABI.GetFramePtr(); // Mark $fp as used if function has dedicated frame pointer. if (hasFP(MF)) @@ -641,8 +633,8 @@ processFunctionBeforeCalleeSavedScan(MachineFunction &MF, if (isInt<16>(MaxSPOffset)) return; - const TargetRegisterClass *RC = STI.isABI_N64() ? - &Mips::GPR64RegClass : &Mips::GPR32RegClass; + const TargetRegisterClass *RC = + ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), RC->getAlignment(), false); RS->addScavengingFrameIndex(FI); diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index cb38393f30d..786307b95f8 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -359,10 +359,10 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const MipsSubtarget &STI = Subtarget; + MipsABIInfo ABI = Subtarget.getABI(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); - unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; - unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; + unsigned ADDu = ABI.GetPtrAdduOp(); + unsigned ADDiu = ABI.GetPtrAddiuOp(); if (Amount == 0) return; @@ -610,7 +610,8 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, // This pseudo instruction is generated as part of the lowering of // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and // indirect jump to TargetReg - unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; + MipsABIInfo ABI = Subtarget.getABI(); + unsigned ADDU = ABI.GetPtrAdduOp(); unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; diff --git a/lib/Target/Mips/MipsSERegisterInfo.cpp b/lib/Target/Mips/MipsSERegisterInfo.cpp index b89207ea1d2..8c74a98ecca 100644 --- a/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -110,8 +110,8 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, MachineFunction &MF = *MI.getParent()->getParent(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); - bool isN64 = - static_cast(MF.getTarget()).getABI().IsN64(); + MipsABIInfo ABI = + static_cast(MF.getTarget()).getABI(); const std::vector &CSI = MFI->getCalleeSavedInfo(); int MinCSFI = 0; @@ -134,7 +134,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned FrameReg; if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI) - FrameReg = isN64 ? Mips::SP_64 : Mips::SP; + FrameReg = ABI.GetStackPtr(); else FrameReg = getFrameRegister(MF); @@ -167,15 +167,16 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = II->getDebugLoc(); - unsigned ADDiu = isN64 ? Mips::DADDiu : Mips::ADDiu; - const TargetRegisterClass *RC = - isN64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + const TargetRegisterClass *PtrRC = + ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); - unsigned Reg = RegInfo.createVirtualRegister(RC); + unsigned Reg = RegInfo.createVirtualRegister(PtrRC); const MipsSEInstrInfo &TII = *static_cast( MBB.getParent()->getSubtarget().getInstrInfo()); - BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); + BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg) + .addReg(FrameReg) + .addImm(Offset); FrameReg = Reg; Offset = 0; @@ -185,14 +186,13 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, // instructions. MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = II->getDebugLoc(); - unsigned ADDu = isN64 ? Mips::DADDu : Mips::ADDu; unsigned NewImm = 0; const MipsSEInstrInfo &TII = *static_cast( MBB.getParent()->getSubtarget().getInstrInfo()); unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, OffsetBitSize == 16 ? &NewImm : nullptr); - BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) + BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg) .addReg(Reg, RegState::Kill); FrameReg = Reg; -- 2.34.1