Fix compiler warning (for -Asserts).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76110 91177308-0d34-0410-b5e6-96231b3b80d8

Silence warning in Linux builds:

X86InstrInfo.cpp:2272: warning: suggest explicit braces to avoid ambiguous 'else'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76105 91177308-0d34-0410-b5e6-96231b3b80d8

Add raw_null_ostream and llvm::nulls(), a raw_ostream that discards output.
 - No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76103 91177308-0d34-0410-b5e6-96231b3b80d8

Add line numbers to OProfile. To do this, I added a processDebugLoc()
call to the MachineCodeEmitter interface and made copying the start
line of a function not conditional on whether we're emitting Dwarf
debug information. I'll propagate the processDebugLoc() calls to the
non-X86 targets in a followup patch.

In the long run, it'll probably be better to gather this information
through the DwarfWriter, but the DwarfWriter currently depends on the
AsmPrinter and TargetAsmInfo, and fixing that would be out of the way
for this patch.

There's a bug in OProfile 0.9.4 that makes it ignore line numbers for
addresses above 4G, and a patch fixing it at
http://thread.gmane.org/gmane.linux.oprofile/7634

Sample output:

$ sudo opcontrol --reset; sudo opcontrol --start-daemon; sudo opcontrol --start; `pwd`/Debug/bin/lli fib.bc; sudo opcontrol --stop
Signalling daemon... done
Profiler running.
fib(40) == 165580141
Stopping profiling.

$ opreport -g -d -l `pwd`/Debug/bin/lli|head -60
Overflow stats not available
CPU: Core 2, speed 1998 MHz (estimated)
Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00 (Unhalted core cycles) count 100000
vma      samples  %        linenr info                 image name               symbol name
00007f67a30370b0 25489    61.2554  fib.c:24                    10946.jo                 fib_left
  00007f67a30370b0 1634      6.4106  fib.c:24
  00007f67a30370b1 83        0.3256  fib.c:24
  00007f67a30370b9 1997      7.8348  fib.c:24
  00007f67a30370c6 2080      8.1604  fib.c:27
  00007f67a30370c8 988       3.8762  fib.c:27
  00007f67a30370cd 1315      5.1591  fib.c:27
  00007f67a30370cf 251       0.9847  fib.c:27
  00007f67a30370d3 1191      4.6726  fib.c:27
  00007f67a30370d6 975       3.8252  fib.c:27
  00007f67a30370db 1010      3.9625  fib.c:27
  00007f67a30370dd 242       0.9494  fib.c:27
  00007f67a30370e1 2782     10.9145  fib.c:28
  00007f67a30370e5 3768     14.7828  fib.c:28
  00007f67a30370eb 615       2.4128  (no location information)
  00007f67a30370f3 6558     25.7287  (no location information)
00007f67a3037100 15603    37.4973  fib.c:29                    10946.jo                 fib_right
  00007f67a3037100 1646     10.5493  fib.c:29
  00007f67a3037101 45        0.2884  fib.c:29
  00007f67a3037109 2372     15.2022  fib.c:29
  00007f67a3037116 2234     14.3178  fib.c:32
  00007f67a3037118 612       3.9223  fib.c:32
  00007f67a303711d 622       3.9864  fib.c:32
  00007f67a303711f 385       2.4675  fib.c:32
  00007f67a3037123 404       2.5892  fib.c:32
  00007f67a3037126 634       4.0633  fib.c:32
  00007f67a303712b 870       5.5759  fib.c:32
  00007f67a303712d 62        0.3974  fib.c:32
  00007f67a3037131 1848     11.8439  fib.c:33
  00007f67a3037135 2840     18.2016  fib.c:33
  00007f67a303713a 1         0.0064  fib.c:33
  00007f67a303713b 1023      6.5564  (no location information)
  00007f67a3037143 5         0.0320  (no location information)
000000000080c1e4 15        0.0360  MachineOperand.h:150        lli                      llvm::MachineOperand::isReg() const
  000000000080c1e4 6        40.0000  MachineOperand.h:150
  000000000080c1ec 2        13.3333  MachineOperand.h:150
...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76102 91177308-0d34-0410-b5e6-96231b3b80d8

Teach MachineInstr::isRegTiedToDefOperand() to correctly parse inline asm operands.

The inline asm operands must be parsed from the first flag, you cannot assume
that an immediate operand preceeding a register use operand is the flag.
PowerPC "m" operands are represented as (flag, imm, reg) triples.
isRegTiedToDefOperand() would incorrectly interpret the imm as the flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76101 91177308-0d34-0410-b5e6-96231b3b80d8

Changed my mind. We now allow remat of instructions whose defs have subreg indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76100 91177308-0d34-0410-b5e6-96231b3b80d8

Privatize the ConstantFP table.  I'm on a roll!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76097 91177308-0d34-0410-b5e6-96231b3b80d8

this should be xfailed on darwin.  Darwin doesn't use the libstdc++ in the llvm-gcc distro, it uses the system version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76095 91177308-0d34-0410-b5e6-96231b3b80d8

With recent MC changes, RIP base register is explicitly modeled. Make sure we add it when x86 V_SET0 / V_SETALLONES (by transforming it into a constpool load) into the use instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76094 91177308-0d34-0410-b5e6-96231b3b80d8

Update CMake file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76093 91177308-0d34-0410-b5e6-96231b3b80d8

Move the ConstantInt uniquing table into LLVMContextImpl.  This exposed a number of issues in
our current context-passing stuff, which is also fixed here

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76089 91177308-0d34-0410-b5e6-96231b3b80d8

Removed the SubsectionsViaSymbols MCStreamer API and replaced it with a generic
EmitAssemblerFlag API which takes a value from the added AssemblerFlag
enumerated constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76087 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak svn:ignore

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76086 91177308-0d34-0410-b5e6-96231b3b80d8

Fill in some holes in ScalarEvolution's loop iteration condition
analysis. This allows indvars to emit a simpler loop trip count
expression.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76085 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up the definition of Str in AsmParser::ParseDirectiveDarwinDumpOrLoad
so it is defined with a lifetime that is as short as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76082 91177308-0d34-0410-b5e6-96231b3b80d8

Add SmallString unit test.
 - Patch by Ryan Flynn!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76081 91177308-0d34-0410-b5e6-96231b3b80d8

In an Apple-style build, compile with llvm-gcc/llvm-g++ if available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76080 91177308-0d34-0410-b5e6-96231b3b80d8

Add an isLoopSimplifyForm() predicate, following the example of
isLCSSAForm(), to test whether a loop is in the form guaranteed
by the LoopSimplify pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76077 91177308-0d34-0410-b5e6-96231b3b80d8

Use setStream infomatted_raw_ostream's constructor, to reduce code
duplication. Also, make setStream honor the old DeleteStream flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76075 91177308-0d34-0410-b5e6-96231b3b80d8

Remove inapplicable comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76074 91177308-0d34-0410-b5e6-96231b3b80d8

Add explicit keywords.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76073 91177308-0d34-0410-b5e6-96231b3b80d8

Tidy up #includes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76072 91177308-0d34-0410-b5e6-96231b3b80d8

Convert more tools code from cerr and cout to errs() and outs().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76070 91177308-0d34-0410-b5e6-96231b3b80d8

Use size_t.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76069 91177308-0d34-0410-b5e6-96231b3b80d8

Make xfail proper

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76065 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76064 91177308-0d34-0410-b5e6-96231b3b80d8

Temporary disable 16 bit bswap

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76063 91177308-0d34-0410-b5e6-96231b3b80d8

Add instruction formats and few opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76062 91177308-0d34-0410-b5e6-96231b3b80d8

Add bswap patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76061 91177308-0d34-0410-b5e6-96231b3b80d8

Provide crazy pseudos for regpairs spills / reloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76060 91177308-0d34-0410-b5e6-96231b3b80d8

Handle long-disp stuff more consistently

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76059 91177308-0d34-0410-b5e6-96231b3b80d8

All FP instructions have 12 bit memory displacement field

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76058 91177308-0d34-0410-b5e6-96231b3b80d8

Another predicate routine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76057 91177308-0d34-0410-b5e6-96231b3b80d8

More helpers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76056 91177308-0d34-0410-b5e6-96231b3b80d8

Add bunch of branch folding stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76055 91177308-0d34-0410-b5e6-96231b3b80d8

Add missed opcodes to short => long displacement conversion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76054 91177308-0d34-0410-b5e6-96231b3b80d8

Cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76053 91177308-0d34-0410-b5e6-96231b3b80d8

Fix logic inversion for RI-mode address selection

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76052 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak the test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76051 91177308-0d34-0410-b5e6-96231b3b80d8

Expand 32-bit bitconverts via memory

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76050 91177308-0d34-0410-b5e6-96231b3b80d8

Fix incomin arg stack frame offset in case we need to generate stack frame

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76049 91177308-0d34-0410-b5e6-96231b3b80d8

Fix instruction mnemonics for some fp_to_sint operations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76048 91177308-0d34-0410-b5e6-96231b3b80d8

i32 values are passed extended also on stack. Handle this in generic way

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76047 91177308-0d34-0410-b5e6-96231b3b80d8

We definitely have 1-0 bools

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76046 91177308-0d34-0410-b5e6-96231b3b80d8

Revert the commit, it just hides the real bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76045 91177308-0d34-0410-b5e6-96231b3b80d8

Out GR128 regclass is not a 'real' i128 one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76044 91177308-0d34-0410-b5e6-96231b3b80d8

Add missed condbranch opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76043 91177308-0d34-0410-b5e6-96231b3b80d8

Handle bitconverts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76042 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak mvi and friends - emit only 'significant' part of the operand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76041 91177308-0d34-0410-b5e6-96231b3b80d8

Expand fp_to_uint too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76040 91177308-0d34-0410-b5e6-96231b3b80d8

We don't have FP truncstores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76039 91177308-0d34-0410-b5e6-96231b3b80d8

Expand uint_to_fp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76038 91177308-0d34-0410-b5e6-96231b3b80d8

Emit proper rounding mode for fp_to_sint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76037 91177308-0d34-0410-b5e6-96231b3b80d8

f32/f64 regs are stored on stack if we're short in FP regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76036 91177308-0d34-0410-b5e6-96231b3b80d8

Lower anyext to zext, 32-bit stuff does not have any implicit zero-extension side effects

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76035 91177308-0d34-0410-b5e6-96231b3b80d8

Make FP zero to be legal FP immediate via LOAD ZERO

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76034 91177308-0d34-0410-b5e6-96231b3b80d8

Loads are not two-address in any way

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76033 91177308-0d34-0410-b5e6-96231b3b80d8

Add LOAD NEGATIVE instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76032 91177308-0d34-0410-b5e6-96231b3b80d8

LOAD COMPLEMENT instruction is not really two-addr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76031 91177308-0d34-0410-b5e6-96231b3b80d8

Add multiple add/sub instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76030 91177308-0d34-0410-b5e6-96231b3b80d8

Handle FP callee-saved regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76029 91177308-0d34-0410-b5e6-96231b3b80d8

Proper FP extloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76028 91177308-0d34-0410-b5e6-96231b3b80d8

Add proper PWS impdef's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76027 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate FP select_cc to dag inserters

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76026 91177308-0d34-0410-b5e6-96231b3b80d8

Implement fp_to_sint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76025 91177308-0d34-0410-b5e6-96231b3b80d8

Implement FP regs spills / restores

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76024 91177308-0d34-0410-b5e6-96231b3b80d8

Add fabs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76023 91177308-0d34-0410-b5e6-96231b3b80d8

Add fneg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76022 91177308-0d34-0410-b5e6-96231b3b80d8

We don't have native sine / cosine instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76021 91177308-0d34-0410-b5e6-96231b3b80d8

More sint_to_fp stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76020 91177308-0d34-0410-b5e6-96231b3b80d8

Add bunch of FP instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76019 91177308-0d34-0410-b5e6-96231b3b80d8

We don't have any FP extloads

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76018 91177308-0d34-0410-b5e6-96231b3b80d8

Implement all comparisons

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76017 91177308-0d34-0410-b5e6-96231b3b80d8

Add constpool lowering / printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76016 91177308-0d34-0410-b5e6-96231b3b80d8

Allow FP arguments pass / return

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76015 91177308-0d34-0410-b5e6-96231b3b80d8

Register FP regclasses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76014 91177308-0d34-0410-b5e6-96231b3b80d8

Add FP regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76013 91177308-0d34-0410-b5e6-96231b3b80d8

Fix fallout from prev. patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76012 91177308-0d34-0410-b5e6-96231b3b80d8

Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8

Use divide single for 32 bit signed divides

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76010 91177308-0d34-0410-b5e6-96231b3b80d8

Add missed operands types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76009 91177308-0d34-0410-b5e6-96231b3b80d8

Missed part of prev. patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76008 91177308-0d34-0410-b5e6-96231b3b80d8

Another attempt to fix prologue emission

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76007 91177308-0d34-0410-b5e6-96231b3b80d8

Implement 'large' PIC model

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76006 91177308-0d34-0410-b5e6-96231b3b80d8

Implement shifts properly (hopefilly - finally!)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8

Remove redundand register move

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8

Properly handle divides. As a bonus - implement memory versions of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8

Fix epic fail: full-width muls are not commutable. This unbreaks bunch of stuff from SingleSource/Benchmarks/Stanford

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76002 91177308-0d34-0410-b5e6-96231b3b80d8

32 bit rotate is not twoaddr instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76001 91177308-0d34-0410-b5e6-96231b3b80d8

32 bit shifts have only 12 bit displacements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76000 91177308-0d34-0410-b5e6-96231b3b80d8

Add proper register aliases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75999 91177308-0d34-0410-b5e6-96231b3b80d8

Properly generate stack frame

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75998 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak indirect branches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75997 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75996 91177308-0d34-0410-b5e6-96231b3b80d8

Do not forget to save R15 when we allocate stack frame

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75995 91177308-0d34-0410-b5e6-96231b3b80d8

All calls clobbers R14

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75994 91177308-0d34-0410-b5e6-96231b3b80d8

Unbreak calls to vararg functions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75993 91177308-0d34-0410-b5e6-96231b3b80d8

Stupid typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75992 91177308-0d34-0410-b5e6-96231b3b80d8

Typos

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75991 91177308-0d34-0410-b5e6-96231b3b80d8

Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8