Fix the JIT encoding of VSPLTI*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27159 91177308-0d34-0410-b5e6-96231b3b80d8

Pass llvm/test/Regression/CodeGen/Generic/debug-info.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27158 91177308-0d34-0410-b5e6-96231b3b80d8

SelectionDAGISel can now natively handle Switch instructions, in the same
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27156 91177308-0d34-0410-b5e6-96231b3b80d8

Bullet proof against undefined args produced by upgrading ols-style debug info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27155 91177308-0d34-0410-b5e6-96231b3b80d8

How to be dumb on $5/day.  Need a tri-state to track valid debug descriptors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27154 91177308-0d34-0410-b5e6-96231b3b80d8

add vsel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27153 91177308-0d34-0410-b5e6-96231b3b80d8

Readme note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27152 91177308-0d34-0410-b5e6-96231b3b80d8

Codegen vector predicate compares.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8

Remove X86:isZeroVector, use ISD::isBuildVectorAllZeros instead; some fixes / cleanups

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27150 91177308-0d34-0410-b5e6-96231b3b80d8

Remove PPC:isZeroVector, use ISD::isBuildVectorAllZeros instead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27149 91177308-0d34-0410-b5e6-96231b3b80d8

Add immAllZerosV helper

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27148 91177308-0d34-0410-b5e6-96231b3b80d8

Add ISD::isBuildVectorAllZeros predicate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27147 91177308-0d34-0410-b5e6-96231b3b80d8

Allow targets to custom lower their own intrinsics if desired.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27146 91177308-0d34-0410-b5e6-96231b3b80d8

Add predicate comparison intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27145 91177308-0d34-0410-b5e6-96231b3b80d8

Update dependencies to reflect split of the Intrinsics.td file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27144 91177308-0d34-0410-b5e6-96231b3b80d8

Add all of the altivec comparison instructions.  Add patterns for the
non-predicate altivec compare intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27143 91177308-0d34-0410-b5e6-96231b3b80d8

Add and 8/16-bit adds, add all integer subtracts, add saturating subtract
intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27142 91177308-0d34-0410-b5e6-96231b3b80d8

Split the PPC and X86 intrinsics out to their own files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27141 91177308-0d34-0410-b5e6-96231b3b80d8

Add saturating subtracts, non-predicate compares, and some other random
intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27140 91177308-0d34-0410-b5e6-96231b3b80d8

implement the vsldoi intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27139 91177308-0d34-0410-b5e6-96231b3b80d8

add int_ppc_altivec_vsldoi intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27138 91177308-0d34-0410-b5e6-96231b3b80d8

Correct the vandc testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27137 91177308-0d34-0410-b5e6-96231b3b80d8

fix the pattern for vandc, it's NOT vnand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27136 91177308-0d34-0410-b5e6-96231b3b80d8

add patterns for VANDC/VNOR, implementing
CodeGen/PowerPC/eqv-andc-orc-nor.ll:VNOR/VANDC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27135 91177308-0d34-0410-b5e6-96231b3b80d8

new testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27134 91177308-0d34-0410-b5e6-96231b3b80d8

Add some comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27133 91177308-0d34-0410-b5e6-96231b3b80d8

add a vnot helper node for matching 'not' on vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27132 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bug in ISD::isBuildVectorAllOnesInteger that  caused it to always return
false

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27131 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the ISD::isBuildVectorAllOnesInteger predicate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27130 91177308-0d34-0410-b5e6-96231b3b80d8

Add a predicate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27129 91177308-0d34-0410-b5e6-96231b3b80d8

Don't call SimplifyDemandedBits on vectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27128 91177308-0d34-0410-b5e6-96231b3b80d8

Add some logical operations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27127 91177308-0d34-0410-b5e6-96231b3b80d8

Add a missing check which cause an invalid .td file to crash tblgen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27126 91177308-0d34-0410-b5e6-96231b3b80d8

Don't crash on packed logical ops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27125 91177308-0d34-0410-b5e6-96231b3b80d8

Teach BinaryOperator::createNot to work with packed integer types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27124 91177308-0d34-0410-b5e6-96231b3b80d8

Unused function - easier to throw away than fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27123 91177308-0d34-0410-b5e6-96231b3b80d8

Cast instruction not inserted into basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27122 91177308-0d34-0410-b5e6-96231b3b80d8

Add a BUILD_VECTOR with unpack and interleave testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27121 91177308-0d34-0410-b5e6-96231b3b80d8

Added missing (any_extend (load ...)) patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27120 91177308-0d34-0410-b5e6-96231b3b80d8

Build arbitrary vector with more than 2 distinct scalar elements with a
series of unpack and interleave ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27119 91177308-0d34-0410-b5e6-96231b3b80d8

implement a bunch of intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27118 91177308-0d34-0410-b5e6-96231b3b80d8

Move all Altivec stuff out into a new PPCInstrAltivec.td file.

Add a bunch of patterns for different datatypes, e.g. bit_convert, undef and
zero vector support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27117 91177308-0d34-0410-b5e6-96231b3b80d8

Add some basic patterns for other datatypes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27116 91177308-0d34-0410-b5e6-96231b3b80d8

add all supported formats to the vector register file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27115 91177308-0d34-0410-b5e6-96231b3b80d8

remove extraneous lets

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27114 91177308-0d34-0410-b5e6-96231b3b80d8

Add a bunch of simple altivec intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27113 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for __builtin_altivec_vnmsubfp /vmaddfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27112 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for __builtin_altivec_vnmsubfp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27111 91177308-0d34-0410-b5e6-96231b3b80d8

When failing selection for an intrinsic, print this:

Cannot yet select: intrinsic %llvm.ppc.altivec.lvx

instead of this:

Cannot yet select: 0x9b047e0: v4i32,ch = INTRINSIC 0x9b04540:1, 0x9b04710, 0x9b04790, 0x9b04540

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27110 91177308-0d34-0410-b5e6-96231b3b80d8

#include Intrinsics.h into all dag isels

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8

Implement Intrinsic::getName

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27108 91177308-0d34-0410-b5e6-96231b3b80d8

Add a programatic interface to intrinsic names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27107 91177308-0d34-0410-b5e6-96231b3b80d8

Codegen things like:
 <int -1, int -1, int -1, int -1>
and
 <int 65537, int 65537, int 65537, int 65537>

Using things like:
  vspltisb v0, -1
and:
  vspltish v0, 1

instead of using constant pool loads.

This implements CodeGen/PowerPC/vec_splat.ll:splat_imm_i{32|16}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27106 91177308-0d34-0410-b5e6-96231b3b80d8

New tests for vsplti*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27105 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 cacheability support ops intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27104 91177308-0d34-0410-b5e6-96231b3b80d8

Added SSE cachebility ops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27103 91177308-0d34-0410-b5e6-96231b3b80d8

Instruction encoding bug

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27102 91177308-0d34-0410-b5e6-96231b3b80d8

Added a scalar to vector with zero extension testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27101 91177308-0d34-0410-b5e6-96231b3b80d8

Add new intrinsic node definitions for tblgen use

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27100 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 SIMD store intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27099 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 SIMD load intrinsics (movhps, movlps, and movups).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27098 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 conversion operations intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27097 91177308-0d34-0410-b5e6-96231b3b80d8

Added 128-bit packed integer subtraction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27096 91177308-0d34-0410-b5e6-96231b3b80d8

Added CVTTPS2PI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27095 91177308-0d34-0410-b5e6-96231b3b80d8

Added CVTSS2SI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27094 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 comparison intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27093 91177308-0d34-0410-b5e6-96231b3b80d8

X86 SSE1 arithmetic and logical operation intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27092 91177308-0d34-0410-b5e6-96231b3b80d8

Support for scalar to vector with zero extension.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27091 91177308-0d34-0410-b5e6-96231b3b80d8

Change approach so that we get codegen for free for intrinsics.  With this,
intrinsics that don't take pointer arguments now work.  For example, we can
compile this:

int test3( __m128d *A) {
  return _mm_movemask_pd(*A);
}
int test4( __m128 *A) {
  return _mm_movemask_ps(*A);
}

to this:

_test3:
        movl 4(%esp), %eax
        movapd (%eax), %xmm0
        movmskpd %xmm0, %eax
        ret
_test4:
        movl 4(%esp), %eax
        movaps (%eax), %xmm0
        movmskps %xmm0, %eax
        ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27090 91177308-0d34-0410-b5e6-96231b3b80d8

fix inverted conditional

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27089 91177308-0d34-0410-b5e6-96231b3b80d8

D'oh - should be even numbered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8

Added LDMXCSR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27087 91177308-0d34-0410-b5e6-96231b3b80d8

ldmxcsr is a SSE instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27086 91177308-0d34-0410-b5e6-96231b3b80d8

Added ldmxcsr intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27085 91177308-0d34-0410-b5e6-96231b3b80d8

fix 80 column violations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27084 91177308-0d34-0410-b5e6-96231b3b80d8

plug the intrinsics into the patterns for movmsk*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27083 91177308-0d34-0410-b5e6-96231b3b80d8

Parse intrinsics correctly and perform type propagation.  This doesn't currently
emit the code to select intrinsics, but that is next :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27082 91177308-0d34-0410-b5e6-96231b3b80d8

Add dwarf register numbering to register data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for dwarf register numbering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27080 91177308-0d34-0410-b5e6-96231b3b80d8

Hack no more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27079 91177308-0d34-0410-b5e6-96231b3b80d8

Make sure to initialize the TheDef field!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27078 91177308-0d34-0410-b5e6-96231b3b80d8

add another note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27077 91177308-0d34-0410-b5e6-96231b3b80d8

add a note

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27076 91177308-0d34-0410-b5e6-96231b3b80d8

Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of
the CodeGen* implementations.

Parse the MVT::ValueType for each operand of the intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27075 91177308-0d34-0410-b5e6-96231b3b80d8

Specify the value type for each llvm type.  This needs work for pointers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27074 91177308-0d34-0410-b5e6-96231b3b80d8

Shuffle some includes around

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27073 91177308-0d34-0410-b5e6-96231b3b80d8

Pull in valuetypes.td here, we will use it shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27072 91177308-0d34-0410-b5e6-96231b3b80d8

Only to vector shuffle for {x,x,y,y} cases when SCALAR_TO_VECTOR is free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27071 91177308-0d34-0410-b5e6-96231b3b80d8

expose intrinsic info to the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27070 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bad JIT encoding of VPERM.  Why is VPERM D,A,B,C but vfmadd is D,A,C,B ??

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27069 91177308-0d34-0410-b5e6-96231b3b80d8

Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0.  This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8

New testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27067 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27066 91177308-0d34-0410-b5e6-96231b3b80d8

Fix indent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27065 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up some commentary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27064 91177308-0d34-0410-b5e6-96231b3b80d8

Rename for truth in advertising.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27063 91177308-0d34-0410-b5e6-96231b3b80d8

Fixed some grammer and spelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27062 91177308-0d34-0410-b5e6-96231b3b80d8

Zero vector testcase

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27061 91177308-0d34-0410-b5e6-96231b3b80d8

Disable the i32->float G5 optimization.  It is unsafe, as documented in the
comment.

This fixes 177.mesa, and McCat/09-vor with the td scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27060 91177308-0d34-0410-b5e6-96231b3b80d8

add support for using vxor to build zero vectors.  This implements
Regression/CodeGen/PowerPC/vec_zero.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27059 91177308-0d34-0410-b5e6-96231b3b80d8