cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107990 91177308-0d34-0410-b5e6-96231b3b80d8

remove useless cast and fix typos in comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107989 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107988 91177308-0d34-0410-b5e6-96231b3b80d8

--- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107984 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107983 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107982 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107981 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107980 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107979 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107978 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107977 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107976 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107975 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107974 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107972 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator* (found by inspection)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107971 91177308-0d34-0410-b5e6-96231b3b80d8

fix clang selfhost issue (shadowing)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107970 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107969 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107968 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107967 91177308-0d34-0410-b5e6-96231b3b80d8

cache result of operator*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107966 91177308-0d34-0410-b5e6-96231b3b80d8

cache operator*'s result (in multiple functions)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107965 91177308-0d34-0410-b5e6-96231b3b80d8

refactor type expressions and cache operator*'s result

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107964 91177308-0d34-0410-b5e6-96231b3b80d8

do not repeatedly dereference use_iterator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107963 91177308-0d34-0410-b5e6-96231b3b80d8

do not repeatedly dereference use_iterator

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107962 91177308-0d34-0410-b5e6-96231b3b80d8

two more cases of reuse result of operator*, found by inspection

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107961 91177308-0d34-0410-b5e6-96231b3b80d8

another case of reuse result of operator*, it is expensive to recompute

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107960 91177308-0d34-0410-b5e6-96231b3b80d8

reuse result of operator*, it is expensive to recompute

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107959 91177308-0d34-0410-b5e6-96231b3b80d8

Added a support for inserting new MBBs into the numbering.

Unlike insertMachineInstrInMaps this does not guarantee live intervals will
remain correct. The caller will need to manually update intervals to account
for the changes made to the CFG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107958 91177308-0d34-0410-b5e6-96231b3b80d8

Avoid creating %physreg:subidx operands in SimpleRegisterCoalescing::RemoveCopyByCommutingDef.

This fixes PR7602.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107957 91177308-0d34-0410-b5e6-96231b3b80d8

Deal with a few remaining spots that assume physical registers have live intervals.

This fixes PR7601.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107955 91177308-0d34-0410-b5e6-96231b3b80d8

Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX
fields to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8

Fix test to be less sensitive of regalloc accidents

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107951 91177308-0d34-0410-b5e6-96231b3b80d8

Fix broken isCopy handling in TrimLiveIntervalToLastUse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107950 91177308-0d34-0410-b5e6-96231b3b80d8

Handle COPY in VirtRegRewriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107949 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the memoperand offsets in code generated for va_start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107948 91177308-0d34-0410-b5e6-96231b3b80d8

These changes should have accompanied r107943.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107947 91177308-0d34-0410-b5e6-96231b3b80d8

have the mc lowering process handle a few tail call forms, lowering them to
jumps where possible and turning the TAILCALL marker in the instruction
asm string into a proper comment.

This eliminates a FIXME and is on the path to finishing:
rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc.

However, I can't eliminate the encodings for these instructions because the JIT
still exists and has its own copy of the encoder, sigh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107946 91177308-0d34-0410-b5e6-96231b3b80d8

Print "dregpair" NEON operands with a space between them, for readability and
consistency with other instructions that have lists of register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8

Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8

Factor out x86 segment override prefix encoding, and also use it for VEX

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8

Reenable DAG combining for vector shuffles.  It looks like it was temporarily
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8

reject pseudo instructions early in the encoder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107939 91177308-0d34-0410-b5e6-96231b3b80d8

Remove trailing whitespaces from file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107937 91177308-0d34-0410-b5e6-96231b3b80d8

Change LEA to have 5 operands for its memory operand, just
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8

Reverting r107918 and r107919.  Radar 8063111.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107930 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "Fix broken isCopy handling in TrimLiveIntervalToLastUse"

This reverts commit 107921. It broke the clang self host.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107926 91177308-0d34-0410-b5e6-96231b3b80d8

add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8

Relax assertion. In optimized code, it is possible that first instruction is coming from a inlined function.
This fixes PR7596 .

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107923 91177308-0d34-0410-b5e6-96231b3b80d8

Extension of r107506. Make sure that we don't mark a function as having a call
if the inline ASM doesn't need a stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107922 91177308-0d34-0410-b5e6-96231b3b80d8

Fix broken isCopy handling in TrimLiveIntervalToLastUse

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107921 91177308-0d34-0410-b5e6-96231b3b80d8

Remember the VR64 register class

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107920 91177308-0d34-0410-b5e6-96231b3b80d8

Fix decl/def debug info for template functions.  Radar 8063111.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107919 91177308-0d34-0410-b5e6-96231b3b80d8

Rework segment prefix emission code to handle segments
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8

introduce a new X86II::getMemoryOperandNo method, which
returns the start of the memory operand for an instruction.

Introduce a new "X86AddrSegment" enum to reduce # magic numbers
referring to X86 memory operand layout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107916 91177308-0d34-0410-b5e6-96231b3b80d8

Switch SPU calling convention (function arguments)
to a Tablegen implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107913 91177308-0d34-0410-b5e6-96231b3b80d8

Test case for r107843.  Radar 8152866.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107907 91177308-0d34-0410-b5e6-96231b3b80d8

Revert some unneeded parts of the change in r107886 for the
.weak_def_can_be_hidden directive.  Chris pointed out that the MCAsmInfo.h/.cpp
chunks aren't needed for this until the compiler starts generating these.  And
when that happens it will be more convenient for it to be a bool than a const
char*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107906 91177308-0d34-0410-b5e6-96231b3b80d8

Check for FiniteOnlyFPMath as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8

Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107903 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the x86 floating point stackifier to handle COPY instructions.

This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107899 91177308-0d34-0410-b5e6-96231b3b80d8

Implement X86InstrInfo::copyPhysReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107898 91177308-0d34-0410-b5e6-96231b3b80d8

The NEONPreAllocPass should never have to assign fixed registers anymore.
This pass can go away entirely soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8

For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8

After r107880, findSurvivorReg() no longer needs to be public.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107887 91177308-0d34-0410-b5e6-96231b3b80d8

Added the darwin .weak_def_can_be_hidden directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107886 91177308-0d34-0410-b5e6-96231b3b80d8

only dereference iterator once in the loop
(by caching the result we save a potentially expensive dereference)

also use typedefs to shorten type declarations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107883 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8

remove unneeded parens

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107881 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up scavengeRegister() a bit to prefer available regs, which allows
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107880 91177308-0d34-0410-b5e6-96231b3b80d8

Convert EXTRACT_SUBREG to COPY when emitting machine instrs.

EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8

Remove references to INSERT_SUBREG after de-SSA.

Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107878 91177308-0d34-0410-b5e6-96231b3b80d8

Use std::vector rather than SmallVector here because SmallVector
causes some versions of gcc to crash when building LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107869 91177308-0d34-0410-b5e6-96231b3b80d8

Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107868 91177308-0d34-0410-b5e6-96231b3b80d8

Do not use std::stack because it causes obscure failures when
compiled with MSVC 2010 (PR7367).  Instead use a SmallVector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107867 91177308-0d34-0410-b5e6-96231b3b80d8

Teach instcombine to transform
(X >s -1) ? C1 : C2 and (X <s  0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.

This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.

for
int sel(int n) {
     return n >= 0 ? 60 : 100;
}

we now generate
  sarl  $31, %edi
  andl  $40, %edi
  leal  60(%rdi), %eax

instead of
  testl %edi, %edi
  movl  $60, %ecx
  movl  $100, %eax
  cmovnsl %ecx, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107866 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak some docs now that the default build is called Debug+Asserts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107862 91177308-0d34-0410-b5e6-96231b3b80d8

A slight reworking of the custom patterns for x86-64 tpoff codegen and
correct the testcase for valid assembly.

Needs more tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107860 91177308-0d34-0410-b5e6-96231b3b80d8

r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8

Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs.

This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.

Any remaining calls to copyRegToReg wil be replaced by COPY instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8

Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met:
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8

Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8

Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8

When processing frame index virtual registers, consider all available registers
(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107847 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the second half of PR7437: scalarrepl wasn't preserving
address spaces when SRoA'ing memcpy's.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107846 91177308-0d34-0410-b5e6-96231b3b80d8

Don't forward-declare registers for static allocas, which we'll
prefer to materialize as local constants. This fixes the clang
bootstrap abort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107840 91177308-0d34-0410-b5e6-96231b3b80d8

Fix -fast-isel-abort to check the right instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107839 91177308-0d34-0410-b5e6-96231b3b80d8

use PrintEscapedString to handle attribute section with escapes in it,
PR7399.  The asm parser already handles this.  This is of dubious
utility (see the PR) but the asmprinter was clearly broken here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107834 91177308-0d34-0410-b5e6-96231b3b80d8

fix copies to/from GR8_ABCD_H even more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107832 91177308-0d34-0410-b5e6-96231b3b80d8

grammar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107831 91177308-0d34-0410-b5e6-96231b3b80d8

Handle cases where the post-RA scheduler may move instructions between the
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107830 91177308-0d34-0410-b5e6-96231b3b80d8

finish up support for callw: PR7195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107826 91177308-0d34-0410-b5e6-96231b3b80d8

Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler.  Still some discussion to be
done.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8

Add more assembly opcodes for SSE compare instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107823 91177308-0d34-0410-b5e6-96231b3b80d8

One MDNode may be used to create regular DIE as well as abstract DIE.
Keep track of abstract subprogram DIEs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107822 91177308-0d34-0410-b5e6-96231b3b80d8

Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107820 91177308-0d34-0410-b5e6-96231b3b80d8

Print undefined/unknown debug value as "undef".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107818 91177308-0d34-0410-b5e6-96231b3b80d8

Not all custom inserters create new basic blocks. If the inserter
didn't create a new block, don't reset the insert position.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107813 91177308-0d34-0410-b5e6-96231b3b80d8

grammar and trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107811 91177308-0d34-0410-b5e6-96231b3b80d8