7 years agoWinCOFFObjectWriter.cpp: make write_uint32_le more efficient
Hans Wennborg [Sun, 28 Sep 2014 00:22:27 +0000 (00:22 +0000)]
WinCOFFObjectWriter.cpp: make write_uint32_le more efficient

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218574 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Redundant store instructions should be removed as dead code
James Molloy [Sat, 27 Sep 2014 17:02:54 +0000 (17:02 +0000)]
[AArch64] Redundant store instructions should be removed as dead code

If there is a store followed by a store with the same value to the same location, then the store is dead/noop. It can be removed.

This problem is found in spec2006-197.parser.

For example,
  stur    w10, [x11, #-4]
  stur    w10, [x11, #-4]
Then one of the two stur instructions can be removed.

Patch by David Xu!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218569 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix llvm::huge_valf multiple initializations with Visual C++.
Yaron Keren [Sat, 27 Sep 2014 14:41:29 +0000 (14:41 +0000)]
Fix llvm::huge_valf multiple initializations with Visual C++.

llvm::huge_valf is defined in a header file, so it is initialized
multiple times in every compiled unit upon program startup.

With non-VC compilers huge_valf is set to a HUGE_VALF which the
compiler can probably optimize out.

With VC numeric_limits<float>::infinity() does not return a number
but a runtime structure member which therotically may change
between calls so the compiler does not optimize out the
initialization and it happens many times. It can be easily seen by
placing a breakpoint on the initialization line.

This patch moves llvm::huge_valf initialization to a source file
instead of the header.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218567 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix yet another issue with widening vector shuffle elements.
Chandler Carruth [Sat, 27 Sep 2014 08:40:33 +0000 (08:40 +0000)]
[x86] Fix yet another issue with widening vector shuffle elements.
I spotted this by inspection when debugging something else, so I have no
test case what-so-ever, and am not even sure it is possible to
realistically trigger the bug. But this is what was intended here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218565 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate test case to match minor formatting change introduced in r218563.
Craig Topper [Sat, 27 Sep 2014 05:36:53 +0000 (05:36 +0000)]
Update test case to match minor formatting change introduced in r218563.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218564 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReduce code duplication a bit.
Craig Topper [Sat, 27 Sep 2014 05:26:42 +0000 (05:26 +0000)]
Reduce code duplication a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218563 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix terrible bugs everywhere in the new vector shuffle lowering
Chandler Carruth [Sat, 27 Sep 2014 04:42:44 +0000 (04:42 +0000)]
[x86] Fix terrible bugs everywhere in the new vector shuffle lowering
and in the target shuffle combining when trying to widen vector

Previously only one of these was correct, and we didn't correctly
propagate zeroing target shuffle masks (which have a different sentinel
value from undef in non- target shuffle masks now). This isn't just
a missed optimization, this caused us to drop zeroing shuffles on the
floor and miscompile code. The added test case is one example of that.

There are other fixes to the test suite as a consequence of this as well
as restoring the undef elements in some of the masks that were lost when
I brought sanity to the actual *value* of the undef and zero sentinels.

I've also just cleaned up some of the PSHUFD and PSHUFLW and PSHUFHW
combining code, but that code really needs to go. It was a nice initial
attempt, but it isn't very principled and the recursive shuffle combiner
is much more powerful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218562 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Flip the sentinel values used in the target shuffle mask decoding
Chandler Carruth [Sat, 27 Sep 2014 04:42:39 +0000 (04:42 +0000)]
[x86] Flip the sentinel values used in the target shuffle mask decoding
to significantly more sane sentinels. Notably, everywhere else in the
backend's representation of shuffles uses '-1' to represent undef. The
target shuffle masks really shouldn't diverge from that, especially as
in a few places they are manipulated by shared code.

This causes us to lose some undef lanes in various test masks. I want to
get these back, but technically it isn't invalid and there are a *lot*
of bugs here so I want to try to establish a saner baseline for fixing
some of the bugs by aligning the specific senitnel values used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218561 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix TableGen -gen-disassembler output for bit fields with an offset.
Craig Topper [Sat, 27 Sep 2014 04:38:02 +0000 (04:38 +0000)]
Fix TableGen -gen-disassembler output for bit fields with an offset.

This fixes bit assignments like this
Inst{7-0} = Foo{9-2}

Patch by Steve King.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218560 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactor reciprocal and reciprocal square root estimate into target-independent funct...
Sanjay Patel [Fri, 26 Sep 2014 23:01:47 +0000 (23:01 +0000)]
Refactor reciprocal and reciprocal square root estimate into target-independent functions (part 2).

This is purely refactoring. No functional changes intended. PowerPC is the only target
that is currently using this interface.

The ultimate goal is to allow targets other than PowerPC (certainly X86 and Aarch64) to turn this:

z = y / sqrt(x)


z = y * rsqrte(x)


z = y / x


z = y * rcpe(x)

using whatever HW magic they can use. See http://llvm.org/bugs/show_bug.cgi?id=20900 .

There is one hook in TargetLowering to get the target-specific opcode for an estimate instruction
along with the number of refinement steps needed to make the estimate usable.

Differential Revision: http://reviews.llvm.org/D5484

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218553 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd LLVM_ENABLE_MODULES flag to CMake to enable building with C++ modules.
Richard Smith [Fri, 26 Sep 2014 22:40:15 +0000 (22:40 +0000)]
Add LLVM_ENABLE_MODULES flag to CMake to enable building with C++ modules.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218551 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-vtabledump: Further simplification
David Majnemer [Fri, 26 Sep 2014 22:32:19 +0000 (22:32 +0000)]
llvm-vtabledump: Further simplification

Hoist out calls to getSection and getContents.  No functional change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218550 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoObject: BSS/virtual sections don't have contents
David Majnemer [Fri, 26 Sep 2014 22:32:16 +0000 (22:32 +0000)]
Object: BSS/virtual sections don't have contents

Users of getSectionContents shouldn't try to pass in BSS or virtual
sections.  In all instances, this is a bug in the code calling this

N.B. Some COFF implementations (like CL) will mark their BSS sections as
taking space on disk.  This would confuse COFFObjectFile into thinking
the section is larger than the file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218549 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoclang-format of ChangeStdinToBinary & ChangeStdoutToBinary.
Yaron Keren [Fri, 26 Sep 2014 22:27:11 +0000 (22:27 +0000)]
clang-format of ChangeStdinToBinary & ChangeStdoutToBinary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218547 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate llvm-objdump’s Mach-O symbolizer code to print the name of symbol stubs.
Kevin Enderby [Fri, 26 Sep 2014 22:20:44 +0000 (22:20 +0000)]
Update llvm-objdump’s Mach-O symbolizer code to print the name of symbol stubs.

So in fully linked images when a call is made through a stub it now gets a
comment like the following in the disassembly:

    callq 0x100000f6c             ## symbol stub for: _printf

indicating the call is to a symbol stub and which symbol it is for.  This is
done for branch reference types and seeing if the branch target is in a stub
section and if so using the indirect symbol table entry for that stub and
using that symbol table entries symbol name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218546 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove definition of LLVM_VERSION_INFO; this macro is not used by any of the
Richard Smith [Fri, 26 Sep 2014 21:53:12 +0000 (21:53 +0000)]
Remove definition of LLVM_VERSION_INFO; this macro is not used by any of the
files in this directory. If it should be defined anywhere, it should be defined
when building lib/LTO/LTOCodeGenerator.cpp, but we've not had it defined there
for quite some time, so that doesn't really seem to be very important. (It also
would slow down the modules build by creating extra module variants.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218544 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix CMake warning CMP0054: don't quote a variable name that is intended to be
Richard Smith [Fri, 26 Sep 2014 21:35:48 +0000 (21:35 +0000)]
Fix CMake warning CMP0054: don't quote a variable name that is intended to be
expanded; future versions of cmake may not expand the variable in this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218543 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix misinterpretation of CMake rule found by a CMake warning (related to CMP0054).
Richard Smith [Fri, 26 Sep 2014 21:33:05 +0000 (21:33 +0000)]
Fix misinterpretation of CMake rule found by a CMake warning (related to CMP0054).

lldb sets the variable SHARED_LIBRARY to 1, which breaks this conditional,
because older versions of CMake interpret


as meaning

  if ("${t}" STREQUAL "1")

in this case. Change the conditional so it does the right thing with both old
and new CMakes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218542 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix a moderately terrifying bug in the new 128-bit shuffle logic
Chandler Carruth [Fri, 26 Sep 2014 20:41:45 +0000 (20:41 +0000)]
[x86] Fix a moderately terrifying bug in the new 128-bit shuffle logic
that managed to elude all of my fuzz testing historically. =/

Something changed to allow this code path to actually be exercised and
it was doing bad things. It is especially heavily exercised by the
patterns that emerge when doing AVX shuffles that end up lowered through
the 128-bit code path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218540 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[IndVar] Don't widen loop compare unless IV user is sign extended.
Chad Rosier [Fri, 26 Sep 2014 20:05:35 +0000 (20:05 +0000)]
[IndVar] Don't widen loop compare unless IV user is sign extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218539 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Use break instead of continue
Matt Arsenault [Fri, 26 Sep 2014 17:55:14 +0000 (17:55 +0000)]
R600/SI: Use break instead of continue

If an instruction doesn't have src1, it doesn't have src2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218536 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add strict check lines to div_scale tests.
Matt Arsenault [Fri, 26 Sep 2014 17:55:11 +0000 (17:55 +0000)]
R600/SI: Add strict check lines to div_scale tests.

This has weird operand requirements so it's worthwhile
to have very strict checks for its operands.

Add different combinations of SGPR operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218535 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add a note about the order of the operands to div_scale
Matt Arsenault [Fri, 26 Sep 2014 17:55:09 +0000 (17:55 +0000)]
R600/SI: Add a note about the order of the operands to div_scale

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218534 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Move finding SGPR operand to move to separate function
Matt Arsenault [Fri, 26 Sep 2014 17:55:06 +0000 (17:55 +0000)]
R600/SI: Move finding SGPR operand to move to separate function

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218533 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI Allow same SGPR to be used for multiple operands
Matt Arsenault [Fri, 26 Sep 2014 17:55:03 +0000 (17:55 +0000)]
R600/SI Allow same SGPR to be used for multiple operands

Instead of moving the first SGPR that is different than the first,
legalize the operand that requires the fewest moves if one
SGPR is used for multiple operands.

This saves extra moves and is also required for some instructions
which require that the same operand be used for multiple operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218532 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Partially move operand legalization to post-isel hook.
Matt Arsenault [Fri, 26 Sep 2014 17:54:59 +0000 (17:54 +0000)]
R600/SI: Partially move operand legalization to post-isel hook.

Disable the SGPR usage restriction parts of the DAG legalizeOperands.
It now should only be doing immediate folding until it can be replaced
later. The real legalization work is now done by the other

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218531 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Implement findCommutedOpIndices
Matt Arsenault [Fri, 26 Sep 2014 17:54:54 +0000 (17:54 +0000)]
R600/SI: Implement findCommutedOpIndices

The base implementation of commuteInstruction is used
in some cases, but it turns out this has been broken for a
long time since modifiers were inserted between the real operands.

The base implementation of commuteInstruction also fails on immediates,
which also needs to be fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218530 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Don't move operands that are required to be SGPRs
Matt Arsenault [Fri, 26 Sep 2014 17:54:52 +0000 (17:54 +0000)]
R600/SI: Don't move operands that are required to be SGPRs

e.g. v_cndmask_b32 requires the condition operand be an SGPR.
If one of the source operands were an SGPR, that would be considered
the one SGPR use and the condition operand would be illegally moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218529 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Don't assert on exotic operand types
Matt Arsenault [Fri, 26 Sep 2014 17:54:46 +0000 (17:54 +0000)]
R600/SI: Don't assert on exotic operand types

This needs a test, but I'm not sure if it is currently possible and
I originally hit it due to a bug. Right now the only global address
operands have no reason to be VALU instructions, although it
theoretically could be a problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218528 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix using wrong operand indices when commuting
Matt Arsenault [Fri, 26 Sep 2014 17:54:43 +0000 (17:54 +0000)]
R600/SI: Fix using wrong operand indices when commuting

No test since the current SIISelLowering::legalizeOperands
effectively hides this, and the general uses seem to only fire
on SALU instructions which don't have modifiers between
the operands.

When trying to use legalizeOperands immediately after
instruction selection, it now sees a lot more patterns
it did not see before which break on this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218527 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Remove apparently dead code in legalizeOperands
Matt Arsenault [Fri, 26 Sep 2014 17:54:38 +0000 (17:54 +0000)]
R600/SI: Remove apparently dead code in legalizeOperands

No tests hit this, and I don't see any way a GlobalAddress
node would survive beyond lowering on SI. It it would, the
move should probably be inserted by selection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218526 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIgnore annotation function calls in cost computation
David Peixotto [Fri, 26 Sep 2014 17:48:40 +0000 (17:48 +0000)]
Ignore annotation function calls in cost computation

The annotation instructions are dropped during codegen and have no
impact on size.  In some cases, the annotations were preventing the
unroller from unrolling a loop because the annotation calls were
pushing the cost over the unrolling threshold.

Differential Revision: http://reviews.llvm.org/D5335

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218525 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] The mnemonic is SHUFPS not SHUPFS. =[ I'm very bad at spelling
Chandler Carruth [Fri, 26 Sep 2014 17:27:40 +0000 (17:27 +0000)]
[x86] The mnemonic is SHUFPS not SHUPFS. =[ I'm very bad at spelling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218524 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] In the new vector shuffle lowering, when trying to do another
Chandler Carruth [Fri, 26 Sep 2014 17:24:26 +0000 (17:24 +0000)]
[x86] In the new vector shuffle lowering, when trying to do another
layer of tie-breaking sorting, it really helps to check that you're in
a tie first. =] Otherwise the whole thing cycles infinitely. Test case
added, another one found through fuzz testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218523 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix a large collection of bugs that crept in as I fleshed out the
Chandler Carruth [Fri, 26 Sep 2014 17:11:02 +0000 (17:11 +0000)]
[x86] Fix a large collection of bugs that crept in as I fleshed out the
AVX support.

New test cases included. Note that none of the existing test cases
covered these buggy code paths. =/ Also, it is clear from this that
SHUFPS and SHUFPD are the most bug prone shuffle instructions in x86. =[

These were all detected by fuzz-testing. (I <3 fuzz testing.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218522 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoElide repeated register operand in Thumb1 instructions
Renato Golin [Fri, 26 Sep 2014 16:14:29 +0000 (16:14 +0000)]
Elide repeated register operand in Thumb1 instructions

This patch makes the ARM backend transform 3 operand instructions such as
'adds/subs' to the 2 operand version of the same instruction if the first
two register operands are the same.

Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'.

Currently for some instructions such as 'adds' if you try to assemble
'adds r0, r0, #8' for thumb v6m the assembler would throw an error message
because the immediate cannot be encoded using 3 bits.

The backend should be smart enough to transform the instruction to
'adds r0, #8', which allows for larger immediate constants.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218521 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][SchedModel] SSE reciprocal square root instruction latencies.
Andrea Di Biagio [Fri, 26 Sep 2014 12:56:44 +0000 (12:56 +0000)]
[X86][SchedModel] SSE reciprocal square root instruction latencies.

The SSE rsqrt instruction (a fast reciprocal square root estimate) was
grouped in the same scheduling IIC_SSE_SQRT* class as the accurate (but very
slow) SSE sqrt instruction. For code which uses rsqrt (possibly with
newton-raphson iterations) this poor scheduling was affecting performances.

This patch splits off the rsqrt instruction from the sqrt instruction scheduling
classes and creates new IIC_SSE_RSQER* classes with latency values based on
Agner's table.

Differential Revision: http://reviews.llvm.org/D5370

Patch by Simon Pilgrim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218517 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "Store TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFU...
Frederic Riss [Fri, 26 Sep 2014 12:34:06 +0000 (12:34 +0000)]
Revert "Store TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFUnitSection."

This reverts commit r218513.

Buildbots using libstdc++ issue an error when trying to copy
SmallVector<std::unique_ptr<>>. Revert the commit until we have a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218514 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoStore TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFUnitSection.
Frederic Riss [Fri, 26 Sep 2014 12:15:40 +0000 (12:15 +0000)]
Store TypeUnits in a SmallVector<DWARFUnitSection> instead of a single DWARFUnitSection.

There will be multiple TypeUnits in an unlinked object that will be extracted
from different sections. Now that we have DWARFUnitSection that is supposed
to represent an input section, we need a DWARFUnitSection<TypeUnit> per
input .debug_types section.

Once this is done, the interface is homogenous and we can move the Section
parsing code into DWARFUnitSection.

Reviewers: samsonov, dblaikie

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218513 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix unused variable warning added in r218509
Daniel Sanders [Fri, 26 Sep 2014 10:45:26 +0000 (10:45 +0000)]
Fix unused variable warning added in r218509

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218510 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Generalize the handling of f128 return values to support f128 arguments.
Daniel Sanders [Fri, 26 Sep 2014 10:06:12 +0000 (10:06 +0000)]
[mips] Generalize the handling of f128 return values to support f128 arguments.

This will allow us to handle f128 arguments without duplicating code from
CCState::AnalyzeFormalArguments() or CCState::AnalyzeCallOperands().

No functional change.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5292

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218509 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Added load/store from BW/VL subsets to Register2Memory opcode tables.
Robert Khasanov [Fri, 26 Sep 2014 09:48:50 +0000 (09:48 +0000)]
[AVX512] Added load/store from BW/VL subsets to Register2Memory opcode tables.
Added lowering tests for these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218508 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-vtabledump: Small cleanup
David Majnemer [Fri, 26 Sep 2014 08:01:23 +0000 (08:01 +0000)]
llvm-vtabledump: Small cleanup

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218505 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofix a typo in doumentation index.
Jyoti Allur [Fri, 26 Sep 2014 06:59:15 +0000 (06:59 +0000)]
fix a typo in doumentation index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218504 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-vtabledump: strip trailing NUL bytes
David Majnemer [Fri, 26 Sep 2014 05:50:45 +0000 (05:50 +0000)]
llvm-vtabledump: strip trailing NUL bytes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218502 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix build breakage on MSVC 2013
David Majnemer [Fri, 26 Sep 2014 04:47:54 +0000 (04:47 +0000)]
Fix build breakage on MSVC 2013

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218499 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-vtabledump: Dump RTTI structures for the MS ABI
David Majnemer [Fri, 26 Sep 2014 04:21:51 +0000 (04:21 +0000)]
llvm-vtabledump: Dump RTTI structures for the MS ABI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218498 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTarget: Fix build breakage.
David Majnemer [Fri, 26 Sep 2014 02:57:05 +0000 (02:57 +0000)]
Target: Fix build breakage.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218497 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSupport: Remove undefined behavior from &raw_ostream::operator<<
David Majnemer [Fri, 26 Sep 2014 02:48:14 +0000 (02:48 +0000)]
Support: Remove undefined behavior from &raw_ostream::operator<<

Don't negate signed integer types in &raw_ostream::operator<<(const
FormattedNumber &FN).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218496 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert patch of r218493, delete the test case
David Xu [Fri, 26 Sep 2014 02:40:54 +0000 (02:40 +0000)]
Revert patch of r218493, delete the test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218495 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert patch ofr218493
David Xu [Fri, 26 Sep 2014 02:28:03 +0000 (02:28 +0000)]
Revert patch ofr218493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218494 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRedundant store instructions should be removed as dead code
David Xu [Fri, 26 Sep 2014 02:02:09 +0000 (02:02 +0000)]
Redundant store instructions should be removed as dead code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218493 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd the first backend support for on demand subtarget creation
Eric Christopher [Fri, 26 Sep 2014 01:44:08 +0000 (01:44 +0000)]
Add the first backend support for on demand subtarget creation
based on the Function. This is currently used to implement
mips16 support in the mips backend via the existing module
pass resetting the subtarget.

Things to note:

a) This involved running resetTargetOptions before creating a
new subtarget so that code generation options like soft-float
could be recognized when creating the new subtarget. This is
to deal with initialization code in isel lowering that only
paid attention to the initial value.

b) Many of the existing testcases weren't using the soft-float
feature correctly. I've corrected these based on the check
values assuming that was the desired behavior.

c) The mips port now pays attention to the target-cpu and
target-features strings when generating code for a particular
function. I've removed these from one function where the
requested cpu and features didn't match the check lines in
the testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218492 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a FIXME to TargetMachine to remove the function specific
Eric Christopher [Fri, 26 Sep 2014 01:44:05 +0000 (01:44 +0000)]
Add a FIXME to TargetMachine to remove the function specific
code generation options from TargetMachine. This will depend
upon Function + TargetSubtargetInfo based code generation at
which point resetTargetOptions and this code can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218491 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoHave setSubtarget take a const subtarget.
Eric Christopher [Fri, 26 Sep 2014 01:28:13 +0000 (01:28 +0000)]
Have setSubtarget take a const subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218490 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove resetTargetOptions from taking a MachineFunction to a Function
Eric Christopher [Fri, 26 Sep 2014 01:28:10 +0000 (01:28 +0000)]
Move resetTargetOptions from taking a MachineFunction to a Function
since we are accessing the TargetMachine that we're a member
function of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218489 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Avoid repeated check lines
Matt Arsenault [Fri, 26 Sep 2014 01:12:36 +0000 (01:12 +0000)]
R600: Avoid repeated check lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218487 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix emitting trailing whitespace after s_waitcnt
Matt Arsenault [Fri, 26 Sep 2014 01:09:46 +0000 (01:09 +0000)]
R600/SI: Fix emitting trailing whitespace after s_waitcnt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218486 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Simplify use of !con()
Adam Nemet [Fri, 26 Sep 2014 00:53:12 +0000 (00:53 +0000)]
[AVX512] Simplify use of !con()

No change in X86.td.expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218485 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Pull pattern for subvector extract into the instruction definition
Adam Nemet [Thu, 25 Sep 2014 23:48:49 +0000 (23:48 +0000)]
[AVX512] Pull pattern for subvector extract into the instruction definition

No functional change.

I initially thought that pulling the Pat<> into the instruction pattern was
not possible because it was doing a transform on the index in order to convert
it from a per-element (extract_subvector) index into a per-chunk (vextract*x4)

Turns out this also works inside the pattern because the vextract_extract
PatFrag has an OperandTransform EXTRACT_get_vextract{128,256}_imm, so the
index in $idx goes through the same conversion.

The existing test CodeGen/X86/avx512-insert-extract.ll extended in the
previous commit provides coverage for this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218480 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well
Adam Nemet [Thu, 25 Sep 2014 23:48:47 +0000 (23:48 +0000)]
[AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well

Extend test so that it provides coverage for the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218479 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Refactor subvector extracts
Adam Nemet [Thu, 25 Sep 2014 23:48:45 +0000 (23:48 +0000)]
[AVX512] Refactor subvector extracts

No functional change.

These are now implemented as two levels of multiclasses heavily relying on the
new X86VectorVTInfo class.  The multiclass at the first level that is called
with float or int provides the 128 or 256 bit subvector extracts.  The second
level provides the register and memory variants and some more Pat<>s.

I've compared the td.expanded files before and after.  One change is that
ExeDomain for 64x4 is SSEPackedDouble now.  I think this is correct, i.e. a

(BTW, this is the change that was blocked on the recent tablegen fix.  The
class-instance values X86VectorVTInfo inside vextract_for_type weren't
properly evaluated.)

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218478 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Fix typo
Adam Nemet [Thu, 25 Sep 2014 23:48:42 +0000 (23:48 +0000)]
[AVX512] Fix typo

F->I in VEXTRACTF32x4rr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218477 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd SDAG TableGen definitions for BR_CC
Hal Finkel [Thu, 25 Sep 2014 23:34:18 +0000 (23:34 +0000)]
Add SDAG TableGen definitions for BR_CC

Add SelectionDAG TableGen definitions for BR_CC so that targets can instruction-select
BR_CC using TableGen pattern matching.

Patch by deadal nix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218476 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Fix some missing conversion testcases
Matt Arsenault [Thu, 25 Sep 2014 23:16:18 +0000 (23:16 +0000)]
R600: Fix some missing conversion testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218474 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove duplicated RUN lines in middle of test
Matt Arsenault [Thu, 25 Sep 2014 23:16:14 +0000 (23:16 +0000)]
Remove duplicated RUN lines in middle of test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218473 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MachineSink+PGO] Teach MachineSink to use BlockFrequencyInfo
Bruno Cardoso Lopes [Thu, 25 Sep 2014 23:14:26 +0000 (23:14 +0000)]
[MachineSink+PGO] Teach MachineSink to use BlockFrequencyInfo

Machine Sink uses loop depth information to select between successors BBs to
sink machine instructions into, where BBs within smaller loop depths are
preferable.  This patch adds support for choosing between successors by using
profile information from BlockFrequencyInfo instead, whenever the information
is available.

Tested it under SPEC2006 train (average of 30 runs for each program); ~1.5%
execution speedup in average on x86-64 darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218472 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoObject: Add range iterators for Archive children
David Majnemer [Thu, 25 Sep 2014 22:56:54 +0000 (22:56 +0000)]
Object: Add range iterators for Archive children

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218471 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Support] Fix Format.h to build on Windows
Nick Kledzik [Thu, 25 Sep 2014 21:00:38 +0000 (21:00 +0000)]
[Support] Fix Format.h to build on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218467 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Support] Add type-safe alternative to llvm::format()
Nick Kledzik [Thu, 25 Sep 2014 20:30:58 +0000 (20:30 +0000)]
[Support] Add type-safe alternative to llvm::format()

llvm::format() is somewhat unsafe. The compiler does not check that integer
parameter size matches the %x or %d size and it does not complain when a
StringRef is passed for a %s.  And correctly using a StringRef with format() is
ugly because you have to convert it to a std::string then call c_str().

The cases where llvm::format() is useful is controlling how numbers and
strings are printed, especially when you want fixed width output.  This
patch adds some new formatting functions to raw_streams to format numbers
and StringRefs in a type safe manner. Some examples:

   OS << format_hex(255, 6)        => "0x00ff"
   OS << format_hex(255, 4)        => "0xff"
   OS << format_decimal(0, 5)      => "    0"
   OS << format_decimal(255, 5)    => "  255"
   OS << right_justify(Str, 5)     => "  foo"
   OS << left_justify(Str, 5)      => "foo  "

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218463 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactoring: raw pointer -> unique_ptr
Anton Yartsev [Thu, 25 Sep 2014 19:55:58 +0000 (19:55 +0000)]
Refactoring: raw pointer -> unique_ptr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218462 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: Remove unneeded check for MI->hasPostISelHook()
Tom Stellard [Thu, 25 Sep 2014 18:59:23 +0000 (18:59 +0000)]
ARM: Remove unneeded check for MI->hasPostISelHook()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218459 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSelectionDAG: Remove #if NDEBUG from check for a post-isel hook
Tom Stellard [Thu, 25 Sep 2014 18:59:22 +0000 (18:59 +0000)]
SelectionDAG: Remove #if NDEBUG from check for a post-isel hook

The InstrEmitter will skip the check of MI.hasPostISelHook()
before calling AdjustInstrPostInstrSelection() when NDEBUG
is not defined.

This was added in r140228, and I'm not sure if it is intentional or not,
but it is a likely source for bugs, because it means with
Release+Asserts builds you can forget to set the hasPostISelHook
flag on TableGen definitions and AdjustInstrPostInstrSelection() will
still be called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218458 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add support for global atomic add
Tom Stellard [Thu, 25 Sep 2014 18:30:26 +0000 (18:30 +0000)]
R600/SI: Add support for global atomic add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218457 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLower idempotent RMWs to fence+load
Robin Morisset [Thu, 25 Sep 2014 17:27:43 +0000 (17:27 +0000)]
Lower idempotent RMWs to fence+load

I originally tried doing this specifically for X86 in the backend in D5091,
but it was rather brittle and generally running too late to be general.
Furthermore, other targets may want to implement similar optimizations.
So I reimplemented it at the IR-level, fitting it into AtomicExpandPass
as it interacts with that pass (which could not be cleanly done before
at the backend level).

This optimization relies on a new target hook, which is only used by X86
for now, as the correctness of the optimization on other targets remains
an open question. If it is found correct on other targets, it should be
trivial to enable for them.

Details of the optimization are discussed in D5091.

Test Plan: make check-all + a new test

Reviewers: jfb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218455 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSince the DisasmMemoryObject only operates on const data, it now only accepts a const...
Aaron Ballman [Thu, 25 Sep 2014 14:02:43 +0000 (14:02 +0000)]
Since the DisasmMemoryObject only operates on const data, it now only accepts a const data pointer. This silences a -Wcast-qual warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218454 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd missing attributes !cmp.[eq,gt,gtu] instructions.
Sid Manning [Thu, 25 Sep 2014 13:09:54 +0000 (13:09 +0000)]
Add missing attributes !cmp.[eq,gt,gtu] instructions.

These instructions do not indicate they are extendable or the
number of bits in the extendable operand.  Rename to match
architected names.  Add a testcase for the intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218453 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd llvm_unreachables() for [ASZ]ExtUpper to X86FastISel.cpp to appease the buildbots.
Daniel Sanders [Thu, 25 Sep 2014 13:08:51 +0000 (13:08 +0000)]
Add llvm_unreachables() for [ASZ]ExtUpper to X86FastISel.cpp to appease the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218452 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struc...
Daniel Sanders [Thu, 25 Sep 2014 12:15:05 +0000 (12:15 +0000)]
[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values.

The N32/N64 ABI's require that structs passed in registers are laid out
such that spilling the register with 'sd' places the struct at the lowest
address. For little endian this is trivial but for big-endian it requires
that structs are shifted into the upper bits of the register.

We also require that structs passed in registers have the 'inreg'
attribute for big-endian N32/N64 to work correctly. This is because the
tablegen-erated calling convention implementation only has access to the
lowered form of struct arguments (one or more integers of up to 64-bits
each) and is unable to determine the original type.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5286

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218451 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd aliases for VAND imm to VBIC ~imm
Renato Golin [Thu, 25 Sep 2014 11:31:24 +0000 (11:31 +0000)]
Add aliases for VAND imm to VBIC ~imm

On ARM NEON, VAND with immediate (16/32 bits) is an alias to VBIC ~imm with
the same type size. Adding that logic to the parser, and generating VBIC
instructions from VAND asm files.

This patch also fixes the validation routines for NEON splat immediates which
were wrong.

Fixes PR20702.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218450 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering to use AVX2 instructions for
Chandler Carruth [Thu, 25 Sep 2014 11:03:55 +0000 (11:03 +0000)]
[x86] Teach the new vector shuffle lowering to use AVX2 instructions for
v4f64 and v8f32 shuffles when they are lane-crossing. We have fully
general lane-crossing permutation functions in AVX2 that make this easy.

Part of this also changes exactly when and how these vectors are split
up when we don't have AVX2. This isn't always a win but it usually is
a win, so on the balance I think its better. The primary regressions are
all things that just need to be fixed anyways such as modeling when
a blend can be completely accomplished via VINSERTF128, etc.

Also, this highlights one of the few remaining big features: we do
a really poor job of inserting elements into AVX registers efficiently.

This completes almost all of the big tricks I have in mind for AVX2. The
only things left that I plan to add:

1) element insertion smarts
2) palignr and other fairly specialized lowerings when they happen to

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218449 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate my previous commit to fit 80 cols...
Sylvestre Ledru [Thu, 25 Sep 2014 10:58:16 +0000 (10:58 +0000)]
Update my previous commit to fit 80 cols...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218448 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDetails that -debug-only is not available when LLVM is built with --enable-optimized
Sylvestre Ledru [Thu, 25 Sep 2014 10:57:00 +0000 (10:57 +0000)]
Details that -debug-only is not available when LLVM is built with --enable-optimized

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218447 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering a fancier way to lower
Chandler Carruth [Thu, 25 Sep 2014 10:21:15 +0000 (10:21 +0000)]
[x86] Teach the new vector shuffle lowering a fancier way to lower
256-bit vectors with lane-crossing.

Rather than immediately decomposing to 128-bit vectors, try flipping the
256-bit vector lanes, shuffling them and blending them together. This
reduces our worst case shuffle by a pretty significant margin across the

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218446 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Thumb2] BXJ should be undefined for v7M, v8A
Oliver Stannard [Thu, 25 Sep 2014 10:02:05 +0000 (10:02 +0000)]
[Thumb2] BXJ should be undefined for v7M, v8A

The Thumb2 BXJ instruction (Branch and Exchange Jazelle) is not
defined for v7M or v8A. It is defined for all other Thumb2-supporting
architectures (v6T2, v7A and v7R).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218445 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix an oversight in the v8i32 path of the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 04:10:27 +0000 (04:10 +0000)]
[x86] Fix an oversight in the v8i32 path of the new vector shuffle
lowering where it only used the mask of the low 128-bit lane rather than
the entire mask.

This allows the new lowering to correctly match the unpack patterns for
v8i32 vectors.

For reference, the reason that we check for the the entire mask rather
than checking the repeated mask is because the repeated masks don't
abide by all of the invariants of normal masks. As a consequence, it is
safer to use the full mask with functions like the generic equivalence

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218442 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Rearrange the code for v16i16 lowering a bit for clarity and to
Chandler Carruth [Thu, 25 Sep 2014 04:03:22 +0000 (04:03 +0000)]
[x86] Rearrange the code for v16i16 lowering a bit for clarity and to
reduce the amount of checking we do here.

The first realization is that only non-crossing cases between 128-bit
lanes are handled by almost the entire function. It makes more sense to
handle the crossing cases first.

THe second is that until we actually are going to generate fancy shared
lowering strategies that use the repeated semantics of the v8i16
lowering, we should waste time checking for repeated masks. It is
simplest to directly test for the entire unpck masks anyways, so we
gained nothing from this.

This also matches the structure of v32i8 more closely.

No functionality changed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218441 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Implement AVX2 support for v32i8 in the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 02:52:12 +0000 (02:52 +0000)]
[x86] Implement AVX2 support for v32i8 in the new vector shuffle

This completes the basic AVX2 feature support, but there are still some
improvements I'd like to do to really get the last mile of performance

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218440 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] More tweaks to the v32i8 test cases.
Chandler Carruth [Thu, 25 Sep 2014 02:44:39 +0000 (02:44 +0000)]
[x86] More tweaks to the v32i8 test cases.

I made a mistake in the previous commit and produced the wrong pattern.
Fix that. Also make one more shuffle pattern byte-based rather than
word-based, and add two more blend patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218439 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Re-work a bunch of the v32i8 test cases to actually involve byte
Chandler Carruth [Thu, 25 Sep 2014 02:20:02 +0000 (02:20 +0000)]
[x86] Re-work a bunch of the v32i8 test cases to actually involve byte
shuffles rather than word shuffles.

As you might guess, these were built starting from the word shuffle test
cases and I failed to properly port a bunch of them and left them as
widened word shuffle test cases. We still have a couple of tests that
check our ability to widen shuffles, but now we will test the actual
byte shuffle quite a bit better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218438 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: Use @IMGREL instead of @IMGREL32, which we can't parse
Reid Kleckner [Thu, 25 Sep 2014 02:09:18 +0000 (02:09 +0000)]
MC: Use @IMGREL instead of @IMGREL32, which we can't parse

Nico Rieck added support for this 32-bit COFF relocation some time ago
for Win64 stuff. It appears that as an oversight, the assembly output
used "foo"@IMGREL32 instead of "foo"@IMGREL, which is what we can parse.

Sadly, there were actually tests that took in IMGREL and put out
IMGREL32, and we didn't notice the inconsistency. Oh well. Now LLVM can
assemble it's own output with slightly more fidelity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218437 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Remove the defunct X86ISD::BLENDV entry -- we use vector selects
Chandler Carruth [Thu, 25 Sep 2014 01:16:01 +0000 (01:16 +0000)]
[x86] Remove the defunct X86ISD::BLENDV entry -- we use vector selects
for this now.

Should prevent folks from running afoul of this and not knowing why
their code won't instruction select the way I just did...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218436 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix the v16i16 blend logic I added in the prior commit and add the
Chandler Carruth [Thu, 25 Sep 2014 01:13:38 +0000 (01:13 +0000)]
[x86] Fix the v16i16 blend logic I added in the prior commit and add the
missing test cases for it.

Unsurprisingly, without test cases, there were bugs here. Surprisingly,
this bug wasn't caught at compile time. Yep, there is an X86ISD::BLENDV.
It isn't wired to anything. Oops. I'll fix than next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218434 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-cov: Combine segments that cover the same location
Justin Bogner [Thu, 25 Sep 2014 00:34:18 +0000 (00:34 +0000)]
llvm-cov: Combine segments that cover the same location

If we have multiple coverage counts for the same segment, we need to
add them up rather than arbitrarily choosing one. This fixes that and
adds a test with template instantiations to exercise it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218432 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86,AVX] Add an isel pattern for X86VBroadcast.
Akira Hatanaka [Thu, 25 Sep 2014 00:26:15 +0000 (00:26 +0000)]
[X86,AVX] Add an isel pattern for X86VBroadcast.

This fixes PR21050 and rdar://problem/18434607.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218431 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Implement v16i16 support with AVX2 in the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 00:24:19 +0000 (00:24 +0000)]
[x86] Implement v16i16 support with AVX2 in the new vector shuffle

This also implements the fancy blend lowering for v16i16 using AVX2 and
teaches the X86 backend to print shuffle masks for 256-bit PSHUFB
and PBLENDW instructions. It also makes the mask decoding correct for
PBLENDW instructions. The yaks, they are legion.

Tests are updated accordingly. There are some missing tests for the
VBLENDVB lowering, but I'll add those in a follow-up as this commit has
accumulated enough cruft already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218430 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFlush out enough of llvm-objdump’s SymbolizerSymbolLookUp() for Mach-O files to
Kevin Enderby [Wed, 24 Sep 2014 23:08:22 +0000 (23:08 +0000)]
Flush out enough of llvm-objdump’s SymbolizerSymbolLookUp() for Mach-O files to
get the literal string “Hello world” printed as a comment on the instruction
that loads the pointer to it. For now this is just for x86_64. So for object
files with relocation entries it produces things like:

leaq L_.str(%rip), %rax      ## literal pool for: "Hello world\n"

and similar for fully linked images like executables:

leaq 0x4f(%rip), %rax        ## literal pool for: "Hello world\n"

Also to allow testing against darwin’s otool(1), I hooked up the existing
-no-show-raw-insn option to the Mach-O parser code, added the new Mach-O
only -full-leading-addr option to match otool(1)'s printing of addresses and
also added the new -print-imm-hex option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218423 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[asan] don't instrument module CTORs that may be run before asan.module_ctor. This...
Kostya Serebryany [Wed, 24 Sep 2014 22:41:55 +0000 (22:41 +0000)]
[asan] don't instrument module CTORs that may be run before asan.module_ctor. This fixes asan running together -coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218421 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemoving empty ARM tests from failed revert
Renato Golin [Wed, 24 Sep 2014 21:58:04 +0000 (21:58 +0000)]
Removing empty ARM tests from failed revert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218419 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemoving empty tests from failed revert
Renato Golin [Wed, 24 Sep 2014 21:45:26 +0000 (21:45 +0000)]
Removing empty tests from failed revert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218417 91177308-0d34-0410-b5e6-96231b3b80d8