9 years agoUpdate
Bill Wendling [Mon, 18 Mar 2013 17:47:33 +0000 (17:47 +0000)]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177298 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix 80-col. violations in PPCCTRLoops
Hal Finkel [Mon, 18 Mar 2013 17:40:46 +0000 (17:40 +0000)]
Fix 80-col. violations in PPCCTRLoops

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177296 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix large count and negative constant count handling in PPCCTRLoops
Hal Finkel [Mon, 18 Mar 2013 17:40:44 +0000 (17:40 +0000)]
Fix large count and negative constant count handling in PPCCTRLoops

This commit fixes an assert that would occur on loops with large constant counts
(like looping for ((uint32_t) -1) iterations on PPC64). The existing code did
not handle counts that it computed to be negative (asserting instead), but
these can be created with valid inputs.

This bug was discovered by bugpoint while I was attempting to isolate a
completely different problem.

Also, in writing test cases for the negative-count problem, I discovered that
the ori/lsi handling was broken (there was a typo which caused the logic that
was supposed to detect these pairs and extract the iteration count to always
fail). This has now also been corrected (and is covered by one of the new test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177295 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCleanup initial-value constants in PPCCTRLoops
Hal Finkel [Mon, 18 Mar 2013 17:40:27 +0000 (17:40 +0000)]
Cleanup initial-value constants in PPCCTRLoops

Because the initial-value constants had not been added to the list
of instructions considered for DCE the resulting code had redundant
constant-materialization instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177294 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix integer comparison in DIEInteger::BestForm.
Hans Wennborg [Mon, 18 Mar 2013 17:03:05 +0000 (17:03 +0000)]
Fix integer comparison in DIEInteger::BestForm.

The always-true "(int)Int == (signed)Int" comparison was found
while experimenting with a potential new Clang warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177290 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReleaseNotes: Tweak hexagonv2/hexagonv3 removal note.
Matthew Curtis [Mon, 18 Mar 2013 13:08:24 +0000 (13:08 +0000)]
ReleaseNotes: Tweak hexagonv2/hexagonv3 removal note.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177284 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove default copy ctor/assignment, makes AttributeSet trivially copyable.
Benjamin Kramer [Mon, 18 Mar 2013 12:14:30 +0000 (12:14 +0000)]
Remove default copy ctor/assignment, makes AttributeSet trivially copyable.

And enables SmallVector's pod optimizations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177281 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInitially forgotten-to-svn-add test case for r177279.
David Tweed [Mon, 18 Mar 2013 12:07:24 +0000 (12:07 +0000)]
Initially forgotten-to-svn-add test case for r177279.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177280 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago The optimization a + (-0.0f) -> a was being misapplied to a + (+0.0f) in the vector...
David Tweed [Mon, 18 Mar 2013 11:54:44 +0000 (11:54 +0000)]
 The optimization a + (-0.0f) -> a was being misapplied to a + (+0.0f) in the vector case (because
we weren't differntiating floating-point zeroinitializers from other zero-initializers)
which was causing problems for code relying upon a + (+0.0f) to, eg, flush denormals to
0. Make the scalar and vector cases have the same behaviour.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177279 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: implement indirect adressing for SI
Christian Konig [Mon, 18 Mar 2013 11:34:16 +0000 (11:34 +0000)]
R600/SI: implement indirect adressing for SI

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: add float vector types
Christian Konig [Mon, 18 Mar 2013 11:34:10 +0000 (11:34 +0000)]
R600/SI: add float vector types

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177276 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: add shl pattern
Christian Konig [Mon, 18 Mar 2013 11:34:05 +0000 (11:34 +0000)]
R600/SI: add shl pattern

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: add BUFFER_LOAD_DWORD pattern
Christian Konig [Mon, 18 Mar 2013 11:34:00 +0000 (11:34 +0000)]
R600/SI: add BUFFER_LOAD_DWORD pattern

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177274 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: implement SI.load.const intrinsic
Christian Konig [Mon, 18 Mar 2013 11:33:55 +0000 (11:33 +0000)]
R600/SI: implement SI.load.const intrinsic

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177273 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes
Christian Konig [Mon, 18 Mar 2013 11:33:50 +0000 (11:33 +0000)]
R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177272 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: fix inserting waits for all defines
Christian Konig [Mon, 18 Mar 2013 11:33:45 +0000 (11:33 +0000)]
R600/SI: fix inserting waits for all defines

Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177271 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] when creating string constants, set unnamed_attr and align 1 so that equal...
Kostya Serebryany [Mon, 18 Mar 2013 09:38:39 +0000 (09:38 +0000)]
[asan] when creating string constants, set unnamed_attr and align 1 so that equal strings are merged by the linker. Observed up to 1% binary size reduction. Thanks to Anton Korobeynikov for the suggestion

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177264 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMark internal classes as POD-like to get better behavior out of
Chandler Carruth [Mon, 18 Mar 2013 08:36:46 +0000 (08:36 +0000)]
Mark internal classes as POD-like to get better behavior out of
SmallVector and DenseMap.

This speeds up SROA by 25% on PR15412.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177259 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTLS support for MinGW targets.
Anton Korobeynikov [Mon, 18 Mar 2013 08:12:28 +0000 (08:12 +0000)]
TLS support for MinGW targets.
MinGW is almost completely compatible to MSVC, with the exception of the _tls_array global not being available.

Patch by David Nadlinger!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177257 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoWindows TLS: Section name prefix to ensure correct order
Anton Korobeynikov [Mon, 18 Mar 2013 08:10:10 +0000 (08:10 +0000)]
Windows TLS: Section name prefix to ensure correct order
The linker sorts the .tls$<xyz> sections by name, and we need
to make sure any extra sections we produce (e.g. for weak globals)
always end up between .tls$AAA and .tls$ZZZ, even if the name
starts with e.g. an underscore.

Patch by David Nadlinger!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177256 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] while generating the description of a global variable, emit the module name...
Kostya Serebryany [Mon, 18 Mar 2013 08:05:29 +0000 (08:05 +0000)]
[asan] while generating the description of a global variable, emit the module name in a separate field, thus not duplicating this information if every description. This decreases the binary size (observed up to 3%). https://code.google.com/p/address-sanitizer/issues/detail?id=168 . This changes the asan API version. llvm-part

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177254 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[asan] don't instrument functions with available_externally linkage. This saves a...
Kostya Serebryany [Mon, 18 Mar 2013 07:33:49 +0000 (07:33 +0000)]
[asan] don't instrument functions with available_externally linkage. This saves a bit of compile time and reduces the number of redundant global strings generated by asan (https://code.google.com/p/address-sanitizer/issues/detail?id=167)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177250 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExtract a method.
Jakob Stoklund Olesen [Mon, 18 Mar 2013 04:08:07 +0000 (04:08 +0000)]
Extract a method.

This computes the type of an instruction operand or result based on the
records in the instruction's ins and outs lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177244 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPost process ADC/SBB and use a shorter encoding if they use a sign extended immediate.
Craig Topper [Mon, 18 Mar 2013 03:34:55 +0000 (03:34 +0000)]
Post process ADC/SBB and use a shorter encoding if they use a sign extended immediate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRefactor some duplicated code into helper functions.
Craig Topper [Mon, 18 Mar 2013 02:53:34 +0000 (02:53 +0000)]
Refactor some duplicated code into helper functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the build broken in r177239
David Blaikie [Sun, 17 Mar 2013 21:32:54 +0000 (21:32 +0000)]
Fix the build broken in r177239

Seems some accidental C++11 crept in there. Reported by the C++98 buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177241 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and moved...
Michael Gottesman [Sun, 17 Mar 2013 21:31:12 +0000 (21:31 +0000)]
Reduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and moved it to retain-block-escape-analysis.ll.

*NOTE* I verified that the original bug behind
dont-infinite-loop-during-block-escape-analysis.ll occurs when using opt on

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177240 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSplit out filename & directory from DIFile to start generalizing over DIScopes
David Blaikie [Sun, 17 Mar 2013 21:13:55 +0000 (21:13 +0000)]
Split out filename & directory from DIFile to start generalizing over DIScopes

This is the first step to making all DIScopes have a common metadata prefix (so
that things (using directives, for example) that can appear in any scope can be
added to that common prefix). DIFile is itself a DIScope so the common prefix
of all DIScopes cannot be a DIFile - instead it's the raw filename/directory
name pair.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoGeneralize debug info test to be resilient to changes in metadata node numbering
David Blaikie [Sun, 17 Mar 2013 21:08:22 +0000 (21:08 +0000)]
Generalize debug info test to be resilient to changes in metadata node numbering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177238 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImprove DIFile debug info annotation by letting it fallback to DIScope
David Blaikie [Sun, 17 Mar 2013 20:28:12 +0000 (20:28 +0000)]
Improve DIFile debug info annotation by letting it fallback to DIScope

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177236 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse ArrayRef<MVT::SimpleValueType> when possible.
Jakob Stoklund Olesen [Sun, 17 Mar 2013 17:26:09 +0000 (17:26 +0000)]
Use ArrayRef<MVT::SimpleValueType> when possible.

Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTo avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.
Sylvestre Ledru [Sun, 17 Mar 2013 12:40:42 +0000 (12:40 +0000)]
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoBuild LLVMgold.so on FreeBSD using cmake.
Rafael Espindola [Sun, 17 Mar 2013 12:01:05 +0000 (12:01 +0000)]
Build LLVMgold.so on FreeBSD using cmake.
Patch by Stephen Checkoway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177233 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThe promised test case for r175939.
Michael Gottesman [Sun, 17 Mar 2013 08:42:58 +0000 (08:42 +0000)]
The promised test case for r175939.

This test makes sure that the ObjCARC escape analysis looks at the uses of
instructions which copy the block pointer value by checking all four cases where
that can occur.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImprove PPC VR (Altivec) register spilling
Hal Finkel [Sun, 17 Mar 2013 04:43:44 +0000 (04:43 +0000)]
Improve PPC VR (Altivec) register spilling

This change cleans up two issues with Altivec register spilling:

  1. The spilling code was inefficient (using two instructions, and add and a
     load, when just one would do)

  2. The code assumed that r0 would always be available (true for now, but this
     will change)

The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove FIXMEs in PPC test cases related to unaligned loads/stores
Hal Finkel [Sat, 16 Mar 2013 23:02:31 +0000 (23:02 +0000)]
Remove FIXMEs in PPC test cases related to unaligned loads/stores

As pointed out by Bill in response to r177160, these two FIXMEs
can also be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove PPC avoidWriteAfterWrite callback
Hal Finkel [Sat, 16 Mar 2013 22:50:51 +0000 (22:50 +0000)]
Remove PPC avoidWriteAfterWrite callback

As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoChange the default latency for implicit defs.
Andrew Trick [Sat, 16 Mar 2013 18:58:57 +0000 (18:58 +0000)]
Change the default latency for implicit defs.

Implicit defs are not currently positional and not modeled by the
per-operand machine model. Unfortunately, we treat defs that are part
of the architectural instruction description, like flags, the same as
other implicit defs. Really, they should have a fixed MachineInstr
layout and probably shouldn't be "implicit" at all.

For now, we'll change the default latency to be the max operand
latency. That will give flag setting operands full latency for x86
folded loads. Other kinds of "fake" implicit defs don't occur prior to
regalloc anyway, and we would like them to go away postRegAlloc as

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMachine model. Allow mixed itinerary classes and SchedRW lists.
Andrew Trick [Sat, 16 Mar 2013 18:58:55 +0000 (18:58 +0000)]
Machine model. Allow mixed itinerary classes and SchedRW lists.

We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[docs] Discuss a potential bug to be aware of.
Sean Silva [Sat, 16 Mar 2013 16:58:20 +0000 (16:58 +0000)]
[docs] Discuss a potential bug to be aware of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177224 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTest case for graceful handling of long file names on Windows. Patch thanks to Paul...
Aaron Ballman [Sat, 16 Mar 2013 15:00:51 +0000 (15:00 +0000)]
Test case for graceful handling of long file names on Windows.  Patch thanks to Paul Robinson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177223 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd X86 code emitter support AVX encoded MRMDestReg instructions.
Craig Topper [Sat, 16 Mar 2013 03:44:31 +0000 (03:44 +0000)]
Add X86 code emitter support AVX encoded MRMDestReg instructions.

Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDefine more SchedWrites for annotating X86 instructions.
Jakob Stoklund Olesen [Sat, 16 Mar 2013 00:02:17 +0000 (00:02 +0000)]
Define more SchedWrites for annotating X86 instructions.

Since almost all X86 instructions can fold loads, use a multiclass to
define register/memory pairs of SchedWrites.

An X86FoldableSchedWrite represents the register version of an
instruction. It holds a reference to the SchedWrite to use when the
instruction folds a load.

This will be used inside multiclasses that define rr and rm instruction
versions together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd SchedRW as an Instruction field.
Jakob Stoklund Olesen [Fri, 15 Mar 2013 22:51:13 +0000 (22:51 +0000)]
Add SchedRW as an Instruction field.

Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ADT] Fix StringSet::insert() to not allocate on every lookup.
Daniel Dunbar [Fri, 15 Mar 2013 20:16:59 +0000 (20:16 +0000)]
[ADT] Fix StringSet::insert() to not allocate on every lookup.
 - The previous implementation always constructed the StringMap entry, even if
   the key was present in the set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177178 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Support][Path][Windows] Fix dangling else. Don't call CloseHandle when CloseFD is...
Michael J. Spencer [Fri, 15 Mar 2013 19:25:47 +0000 (19:25 +0000)]
[Support][Path][Windows] Fix dangling else. Don't call CloseHandle when CloseFD is false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177175 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM cost model: Fix costs for some vector selects
Arnold Schwaighofer [Fri, 15 Mar 2013 18:31:01 +0000 (18:31 +0000)]
ARM cost model: Fix costs for some vector selects

I was too pessimistic in r177105. Vector selects that fit into a legal register
type lower just fine. I was mislead by the code fragment that I was using. The
stores/loads that I saw in those cases came from lowering the conditional off
an address.

Changing the code fragment to:

%T0_3 = type <8 x i18>
%T1_3 = type <8 x i1>

define void @func_blend3(%T0_3* %loadaddr, %T0_3* %loadaddr2,
                         %T1_3* %blend, %T0_3* %storeaddr) {
  %v0 = load %T0_3* %loadaddr
  %v1 = load %T0_3* %loadaddr2
==> FROM:
  ;%c = load %T1_3* %blend
==> TO:
  %c = icmp slt %T0_3 %v0, %v1
==> USE:
  %r = select %T1_3 %c, %T0_3 %v0, %T0_3 %v1

  store %T0_3 %r, %T0_3* %storeaddr
  ret void

revealed this mistake.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177170 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdding an A15 specific optimization pass for interactions between S/D/Q registers...
Silviu Baranga [Fri, 15 Mar 2013 18:28:25 +0000 (18:28 +0000)]
Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177169 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: Fix an old refacto.
Benjamin Kramer [Fri, 15 Mar 2013 17:27:39 +0000 (17:27 +0000)]
ARM: Fix an old refacto.

Fixes PR15520.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177167 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoEnable unaligned memory access on PPC for scalar types
Hal Finkel [Fri, 15 Mar 2013 15:27:13 +0000 (15:27 +0000)]
Enable unaligned memory access on PPC for scalar types

Unaligned access is supported on PPC for non-vector types, and is generally
more efficient than manually expanding the loads and stores.

A few of the existing test cases were using expanded unaligned loads and stores
to test other features (like load/store with update), and for these test cases,
unaligned access remains disabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177160 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM cost model: Fix cost of fptrunc and fpext instructions
Arnold Schwaighofer [Fri, 15 Mar 2013 15:10:47 +0000 (15:10 +0000)]
ARM cost model: Fix cost of fptrunc and fpext instructions

A vector fptrunc and fpext simply gets split into scalar instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177159 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoProtect PPC Altivec patterns with a predicate
Hal Finkel [Fri, 15 Mar 2013 13:21:21 +0000 (13:21 +0000)]
Protect PPC Altivec patterns with a predicate

In preparation for the addition of other SIMD ISA extensions (such as QPX) we
need to make sure that all Altivec patterns are properly predicated on having
Altivec support.

No functionality change intended (one test case needed to be updated b/c it
assumed that Altivec intrinsics would be supported without enabling Altivec

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177152 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFixup for r176933: more careful setup of path to llvm-symbolizer
Alexey Samsonov [Fri, 15 Mar 2013 07:27:49 +0000 (07:27 +0000)]
Fixup for r176933: more careful setup of path to llvm-symbolizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177144 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse NumBaseBits in a few more places in SmallBitVector instead of recalculating it...
Craig Topper [Fri, 15 Mar 2013 06:01:42 +0000 (06:01 +0000)]
Use NumBaseBits in a few more places in SmallBitVector instead of recalculating it. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177142 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the FDE encoding to be relative on ELF.
Rafael Espindola [Fri, 15 Mar 2013 05:51:57 +0000 (05:51 +0000)]
Fix the FDE encoding to be relative on ELF.

This is a very late complement to r130637 which fixed this on x86_64. Fixes

Since it looks like that every elf architecture uses this encoding when using
cfi, make it the default for elf. Just exclude mips64el. It has a lovely
.ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary
content of the .eh_frame produced by llc. Oblige it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAllocate the RS spill slot for any PPC function with spills and a large stack frame
Hal Finkel [Fri, 15 Mar 2013 05:06:04 +0000 (05:06 +0000)]
Allocate the RS spill slot for any PPC function with spills and a large stack frame

For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.

I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTurn anonymous type in anonymous union warning back on after cleaning up
Eric Christopher [Fri, 15 Mar 2013 00:43:00 +0000 (00:43 +0000)]
Turn anonymous type in anonymous union warning back on after cleaning up

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177136 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSilence anonymous type in anonymous union warnings.
Eric Christopher [Fri, 15 Mar 2013 00:42:55 +0000 (00:42 +0000)]
Silence anonymous type in anonymous union warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a triple to the test.
Nadav Rotem [Fri, 15 Mar 2013 00:10:23 +0000 (00:10 +0000)]
Add a triple to the test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177131 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUnaligned loads should use the VMOVUPS opcode.
Nadav Rotem [Thu, 14 Mar 2013 23:49:44 +0000 (23:49 +0000)]
Unaligned loads should use the VMOVUPS opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove some unused variables to clean the Clang -Werror build
David Blaikie [Thu, 14 Mar 2013 23:11:07 +0000 (23:11 +0000)]
Remove some unused variables to clean the Clang -Werror build

(these were added in r177089)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Set isAllocatable bit of unallocatable register classes to 0.
Akira Hatanaka [Thu, 14 Mar 2013 23:09:19 +0000 (23:09 +0000)]
[mips] Set isAllocatable bit of unallocatable register classes to 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix r177112: Add ProcResGroup.
Andrew Trick [Thu, 14 Mar 2013 22:47:01 +0000 (22:47 +0000)]
Fix r177112: Add ProcResGroup.

This is the other half of r177122 that I meant to commit at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177123 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPrepare for adding InstrSchedModel annotations to X86 instructions.
Jakob Stoklund Olesen [Thu, 14 Mar 2013 22:42:17 +0000 (22:42 +0000)]
Prepare for adding InstrSchedModel annotations to X86 instructions.

The new InstrSchedModel is easier to use than the instruction
itineraries. It will be used to model instruction latency and throughput
in modern Intel microarchitectures like Sandy Bridge.

InstrSchedModel should be able to coexist with instruction itinerary
classes, but for cleanliness we should switch the Atom processor model
to the new InstrSchedModel as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177122 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a new method which enables one to change register classes.
Reed Kotler [Thu, 14 Mar 2013 22:02:09 +0000 (22:02 +0000)]
Add a new method which enables one to change register classes.
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup.

Normally you need to add register classes and then call

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLoopVectorizer: Insert some white space to make test case more readable
Arnold Schwaighofer [Thu, 14 Mar 2013 21:31:09 +0000 (21:31 +0000)]
LoopVectorizer: Insert some white space to make test case more readable

Also remove some unneeded function attributes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177114 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handle
Chad Rosier [Thu, 14 Mar 2013 21:25:04 +0000 (21:25 +0000)]
[fast-isel] The X86FastISel::FastLowerArguments function doesn't properly handle
the win64 calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177113 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMachineModel: Add a ProcResGroup class.
Andrew Trick [Thu, 14 Mar 2013 21:21:50 +0000 (21:21 +0000)]
MachineModel: Add a ProcResGroup class.

This allows abitrary groups of processor resources. Using something in
a subset automatically counts againts the superset. Currently, this
only works if the superset is also a ProcResGroup as opposed to a

This allows SandyBridge to be expressed naturally, which will be
checked in shortly.

def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>;
def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>;
def SBPort23  : ProcResGroup<[SBPort2, SBPort3]>;
def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177112 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove estimateStackSize from ARM into MachineFrameInfo
Hal Finkel [Thu, 14 Mar 2013 21:15:20 +0000 (21:15 +0000)]
Move estimateStackSize from ARM into MachineFrameInfo

This is a generic function (derived from PEI); moving it into
MachineFrameInfo eliminates a current redundancy between the ARM and AArch64
backends, and will allow it to be used by the PowerPC target code.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177111 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoProvide the register scavenger to processFunctionBeforeFrameFinalized
Hal Finkel [Thu, 14 Mar 2013 20:33:40 +0000 (20:33 +0000)]
Provide the register scavenger to processFunctionBeforeFrameFinalized

Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.

This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse frame-index scavenging for PPC register spilling
Hal Finkel [Thu, 14 Mar 2013 20:21:47 +0000 (20:21 +0000)]
Use frame-index scavenging for PPC register spilling

Make requiresFrameIndexScavenging return true, and create virtual registers in
the spilling code instead of using the register scavenger directly. This makes
the target-level code simpler, and importantly, delays the scavenging until
after callee-saved register processing (which will be important for later

Also cleans up trackLivenessAfterRegAlloc (makes it inline in the header with
the other related functions). This makes it clear that it always returns true.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177107 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoNot all PPC functions with a frame pointer need a RS spill slot
Hal Finkel [Thu, 14 Mar 2013 19:34:32 +0000 (19:34 +0000)]
Not all PPC functions with a frame pointer need a RS spill slot

We used to add a spill slot for the register scavenger whenever the function
has a frame pointer. This is unnecessarily conservative: We may need the spill
slot for dynamic stack allocations, and functions with dynamic stack
allocations always have a FP, but we might also have a FP for other reasons
(such as the user explicitly disabling frame-pointer elimination), and we don't
necessarily need a spill slot for those functions.

The structsinregs test needed adjustment because it disables FP elimination.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177106 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM cost model: Increase cost of some vector selects we do terrible on
Arnold Schwaighofer [Thu, 14 Mar 2013 19:17:02 +0000 (19:17 +0000)]
ARM cost model: Increase cost of some vector selects we do terrible on

By terrible I mean we store/load from the stack.

This matters on PAQp8 in _Z5trainPsS_ii (which is inlined into Mixer::update)
where we decide to vectorize a loop with a VF of 8 resulting in a 25%
degradation on a cortex-a8.

LV: Found an estimated cost of 2 for VF 8 For instruction:   icmp slt i32
LV: Found an estimated cost of 2 for VF 8 For instruction:   select i1, i32, i32

The bug that tracks the CodeGen part is PR14868.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177105 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Fix filename in comment and delete unnecessary lines of code.
Akira Hatanaka [Thu, 14 Mar 2013 19:09:52 +0000 (19:09 +0000)]
[mips] Fix filename in comment and delete unnecessary lines of code.

No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoHexagon: Removed asserts regarding alignment and offset.
Jyotsna Verma [Thu, 14 Mar 2013 19:08:03 +0000 (19:08 +0000)]
Hexagon: Removed asserts regarding alignment and offset.
We are warning the user about the alignment, so we should not assert.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd missing asserts flag to test - it uses debug flags
Arnold Schwaighofer [Thu, 14 Mar 2013 19:01:58 +0000 (19:01 +0000)]
Add missing asserts flag to test - it uses debug flags

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177102 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAndroid uses cacheflush(long start, long end, long flags) for MIPS.
Akira Hatanaka [Thu, 14 Mar 2013 19:01:00 +0000 (19:01 +0000)]
Android uses cacheflush(long start, long end, long flags) for MIPS.

Patch by Stephen Hines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177101 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLoopVectorize: Invert case when we use a vector cmp value to query select cost
Arnold Schwaighofer [Thu, 14 Mar 2013 18:54:36 +0000 (18:54 +0000)]
LoopVectorize: Invert case when we use a vector cmp value to query select cost

We generate a select with a vectorized condition argument when the condition is
NOT loop invariant. Not the other way around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177098 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd back lines which were accidentally deleted in CMakeLists.txt.
Akira Hatanaka [Thu, 14 Mar 2013 18:46:46 +0000 (18:46 +0000)]
Add back lines which were accidentally deleted in CMakeLists.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.
Akira Hatanaka [Thu, 14 Mar 2013 18:39:25 +0000 (18:39 +0000)]
[mips] Define function MipsSEDAGToDAGISel::selectAddESubE.

No intended functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177095 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a comment about overlapping PPC frame offsets
Hal Finkel [Thu, 14 Mar 2013 18:38:31 +0000 (18:38 +0000)]
Add a comment about overlapping PPC frame offsets

I don't think that it is otherwise clear how the overlapping offsets
are processed into distinct spill slots. Comment that this is done
in processFunctionBeforeFrameFinalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177094 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Rename functions and variables to start with proper case.
Akira Hatanaka [Thu, 14 Mar 2013 18:33:23 +0000 (18:33 +0000)]
[mips] Rename functions and variables to start with proper case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177092 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd header file MipsISelDAGToDAG.h.
Akira Hatanaka [Thu, 14 Mar 2013 18:28:19 +0000 (18:28 +0000)]
Add header file MipsISelDAGToDAG.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177090 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
Akira Hatanaka [Thu, 14 Mar 2013 18:27:31 +0000 (18:27 +0000)]
[mips] Define two subclasses of MipsDAGToDAGISel. Mips16DAGToDAGISel is for
mips16 and MipsSEDAGToDAGISel is for mips32/64.

No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177089 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPerform factorization as a last resort of unsafe fadd/fsub simplification.
Shuxin Yang [Thu, 14 Mar 2013 18:08:26 +0000 (18:08 +0000)]
Perform factorization as a last resort of unsafe fadd/fsub simplification.

Rules include:
  1)1 x*y +/- x*z => x*(y +/- z)
    (the order of operands dosen't matter)

  2) y/x +/- z/x => (y +/- z)/x

 The transformation is disabled if the new add/sub expr "y +/- z" is a


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177088 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTest that we emit a DW_AT_location for self captured by a block.
Adrian Prantl [Thu, 14 Mar 2013 17:54:13 +0000 (17:54 +0000)]
Test that we emit a DW_AT_location for self captured by a block.
This is the backend part of a CFE test with the same name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177087 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Factorize code handling Const Read Port limitation
Vincent Lejeune [Thu, 14 Mar 2013 15:50:45 +0000 (15:50 +0000)]
R600: Factorize code handling Const Read Port limitation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ASan] emit instrumentation for initialization order checking by default
Alexey Samsonov [Thu, 14 Mar 2013 12:38:58 +0000 (12:38 +0000)]
[ASan] emit instrumentation for initialization order checking by default

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177063 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPR14972: SROA vs. GVN exposed a really bad bug in SROA.
Chandler Carruth [Thu, 14 Mar 2013 11:32:24 +0000 (11:32 +0000)]
PR14972: SROA vs. GVN exposed a really bad bug in SROA.

The fundamental problem is that SROA didn't allow for overly wide loads
where the bits past the end of the alloca were masked away and the load
was sufficiently aligned to ensure there is no risk of page fault, or
other trapping behavior. With such widened loads, SROA would delete the
load entirely rather than clamping it to the size of the alloca in order
to allow mem2reg to fire. This was exposed by a test case that neatly
arranged for GVN to run first, widening certain loads, followed by an
inline step, and then SROA which miscompiles the code. However, I see no
reason why this hasn't been plaguing us in other contexts. It seems
deeply broken.

Diagnosing all of the above took all of 10 minutes of debugging. The
really annoying aspect is that fixing this completely breaks the pass.
;] There was an implicit reliance on the fact that no loads or stores
extended past the alloca once we decided to rewrite them in the final
stage of SROA. This was used to encode information about whether the
loads and stores had been split across multiple partitions of the
original alloca. That required threading explicit tracking of whether
a *use* of a partition is split across multiple partitions.

Once that was done, another problem arose: we allowed splitting of
integer loads and stores iff they were loads and stores to the entire
alloca. This is a really arbitrary limitation, and splitting at least
some integer loads and stores is crucial to maximize promotion
opportunities. My first attempt was to start removing the restriction
entirely, but currently that does Very Bad Things by causing *many*
common alloca patterns to be fully decomposed into i8 operations and
lots of or-ing together to produce larger integers on demand. The code
bloat is terrifying. That is still the right end-goal, but substantial
work must be done to either merge partitions or ensure that small i8
values are eagerly merged in some other pass. Sadly, figuring all this
out took essentially all the time and effort here.

So the end result is that we allow splitting only when the load or store
at least covers the alloca. That ensures widened loads and stores don't
hurt SROA, and that we don't rampantly decompose operations more than we
have previously.

All of this was already fairly well tested, and so I've just updated the
tests to cover the wide load behavior. I can add a test that crafts the
pass ordering magic which caused the original PR, but that seems really
brittle and to provide little benefit. The fundamental problem is that
widened loads should Just Work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177055 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd two of the float related ARM-specific entries for e_flags needed for
Joerg Sonnenberger [Thu, 14 Mar 2013 08:01:36 +0000 (08:01 +0000)]
Add two of the float related ARM-specific entries for e_flags needed for
linkers to interact with GNU ld.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177016 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the name of a variable to match its declaration. Fixes build failure from r177014.
Craig Topper [Thu, 14 Mar 2013 07:47:43 +0000 (07:47 +0000)]
Fix the name of a variable to match its declaration. Fixes build failure from r177014.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177015 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set...
Craig Topper [Thu, 14 Mar 2013 07:40:52 +0000 (07:40 +0000)]
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTeach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to...
Craig Topper [Thu, 14 Mar 2013 07:09:57 +0000 (07:09 +0000)]
Teach X86 MC instruction lowering that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177011 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix PR15309
Michael Liao [Thu, 14 Mar 2013 06:57:42 +0000 (06:57 +0000)]
Fix PR15309

- Fix the typo on type checking

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177010 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agotest commit: remove blank line.
Jiong Wang [Thu, 14 Mar 2013 05:43:59 +0000 (05:43 +0000)]
test commit: remove blank line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177009 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove a change to the debug info in this test, that I made while testing
Nick Lewycky [Thu, 14 Mar 2013 05:28:10 +0000 (05:28 +0000)]
Remove a change to the debug info in this test, that I made while testing
something else and forgot to remove.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177007 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTry using %S to find the emitted .gcno file.
Nick Lewycky [Thu, 14 Mar 2013 05:23:30 +0000 (05:23 +0000)]
Try using %S to find the emitted .gcno file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177006 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove accidentally committed debug line.
Nick Lewycky [Thu, 14 Mar 2013 05:19:12 +0000 (05:19 +0000)]
Remove accidentally committed debug line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177005 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRefactor GCOV's six constructor arguments into a struct with a getter that
Nick Lewycky [Thu, 14 Mar 2013 05:13:26 +0000 (05:13 +0000)]
Refactor GCOV's six constructor arguments into a struct with a getter that
constructs default arguments. It can now take default arguments from
cl::opt'ions. Add a new -default-gcov-version=... option, and actually test it!

Sink the reverse-order of the version into GCOVProfiling, hiding it from our

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177002 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix typo in comment.
Nick Lewycky [Thu, 14 Mar 2013 01:26:17 +0000 (01:26 +0000)]
Fix typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176997 91177308-0d34-0410-b5e6-96231b3b80d8