7 years agoSimplify memory management with std::unique_ptr.
Rafael Espindola [Wed, 16 Dec 2015 22:28:34 +0000 (22:28 +0000)]
Simplify memory management with std::unique_ptr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255831 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Make MachineInstrBuilder::copyImplicitOps const. NFC.
Ahmed Bougacha [Wed, 16 Dec 2015 22:15:30 +0000 (22:15 +0000)]
[CodeGen] Make MachineInstrBuilder::copyImplicitOps const. NFC.

This matches the other MIB methods, none of which modify the builder.
Without this, we can't chain copyImplicitOps.
Also reformat the few users, in PPCEarlyReturn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255828 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PGO] Handle and report overflow during profile merge for all types of data
Nathan Slingerland [Wed, 16 Dec 2015 21:45:43 +0000 (21:45 +0000)]
[PGO] Handle and report overflow during profile merge for all types of data

Summary: Surface counter overflow when merging profile data. Merging still occurs on overflow but counts saturate to the maximum representable value. Overflow is reported to the user.

Reviewers: davidxl, dnovillo, silvas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255825 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse LLVM style variable name (NFC)
Teresa Johnson [Wed, 16 Dec 2015 21:37:48 +0000 (21:37 +0000)]
Use LLVM style variable name (NFC)

Fixes variable name from r255779.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255824 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCXX_FAST_TLS calling convention: performance improvement for AArch64.
Manman Ren [Wed, 16 Dec 2015 21:04:19 +0000 (21:04 +0000)]
CXX_FAST_TLS calling convention: performance improvement for AArch64.

The access function has a short entry and a short exit, the initialization
block is only run the first time. To improve the performance, we want to
have a short frame at the entry and exit.

We explicitly handle most of the CSRs via copies. Only the CSRs that are not
handled via copies will be in CSR_SaveList.

Frame lowering and prologue/epilogue insertion will generate a short frame
in the entry and exit according to CSR_SaveList. The majority of the CSRs will
be handled by register allcoator. Register allocator will try to spill and
reload them in the initialization block.

We add CSRsViaCopy, it will be explicitly handled during lowering.

1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target
   supports it for the given machine function and the function has only return
   exits). We also call TLI->initializeSplitCSR to perform initialization.
2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to
   virtual registers at beginning of the entry block and copies from virtual
   registers to CSRsViaCopy at beginning of the exit blocks.
3> we also need to make sure the explicit copies will not be eliminated.

The target independent portion was committed as r255353.

Differential Revision: http://reviews.llvm.org/D15341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255821 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Update e_flags in the ELF definitions
Krzysztof Parzyszek [Wed, 16 Dec 2015 20:57:07 +0000 (20:57 +0000)]
[Hexagon] Update e_flags in the ELF definitions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255820 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCXX_FAST_TLS calling convention: target independent portion.
Manman Ren [Wed, 16 Dec 2015 20:45:48 +0000 (20:45 +0000)]
CXX_FAST_TLS calling convention: target independent portion.

Update supportSplitCSR's interface to take machine function instead of the
calling convention.

Review comments for http://reviews.llvm.org/D15341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255818 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove now-unused include
Derek Schuff [Wed, 16 Dec 2015 20:43:10 +0000 (20:43 +0000)]
Remove now-unused include

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255817 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIterate over phys regs instead
Derek Schuff [Wed, 16 Dec 2015 20:43:08 +0000 (20:43 +0000)]
Iterate over phys regs instead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255816 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Print an extra local decl when the user stack pointer is used
Derek Schuff [Wed, 16 Dec 2015 20:43:06 +0000 (20:43 +0000)]
[WebAssembly] Print an extra local decl when the user stack pointer is used

Differential Revision: http://reviews.llvm.org/D15546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255815 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago [Hexagon] Misc fixes to r255807
Krzysztof Parzyszek [Wed, 16 Dec 2015 20:07:04 +0000 (20:07 +0000)]
 [Hexagon] Misc fixes to r255807

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255811 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSet debugger tuning from TargetOptions (NFC)
Paul Robinson [Wed, 16 Dec 2015 19:58:30 +0000 (19:58 +0000)]
Set debugger tuning from TargetOptions (NFC)

Differential Revision: http://reviews.llvm.org/D15427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255810 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Update the Hexagon packetizer
Krzysztof Parzyszek [Wed, 16 Dec 2015 19:36:12 +0000 (19:36 +0000)]
[Hexagon] Update the Hexagon packetizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255807 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[ARM] Add ARMv8.2-A FP16 scalar instructions"
Reid Kleckner [Wed, 16 Dec 2015 19:21:03 +0000 (19:21 +0000)]
Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"

This reverts commit r255762.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255806 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Fix the CFG Stackifier to handle unoptimized branches
Dan Gohman [Wed, 16 Dec 2015 19:06:41 +0000 (19:06 +0000)]
[WebAssembly] Fix the CFG Stackifier to handle unoptimized branches

If a branch both branches to and falls through to the same block, treat it as
an explicit branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255803 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLPM: Make callers of LPM.deleteLoopFromQueue update LoopInfo directly. NFC
Justin Bogner [Wed, 16 Dec 2015 18:40:20 +0000 (18:40 +0000)]
LPM: Make callers of LPM.deleteLoopFromQueue update LoopInfo directly. NFC

As of r255720, the loop pass manager will DTRT when passes update the
loop info for removed loops, so they no longer need to reach into
LPPassManager APIs to do this kind of transformation. This change very
nearly removes the need for the LPPassManager to even be passed into
loop passes - the only remaining pass that uses the LPM argument is

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255797 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Override getCFInstrCost
Matt Arsenault [Wed, 16 Dec 2015 18:37:19 +0000 (18:37 +0000)]
AMDGPU: Override getCFInstrCost

The default cost was 0 with the assumption that it is predictable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255796 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineScheduler: Add a target hook for deciding which RegPressure sets to
Tom Stellard [Wed, 16 Dec 2015 18:31:01 +0000 (18:31 +0000)]
MachineScheduler: Add a target hook for deciding which RegPressure sets to

This patch adds a function called getRegPressureSetScore() to
TargetRegisterInfo.  The MachineScheduler uses this when comparing
instruction that increase the register pressure of different sets
to determine which set is safer to increase.

This hook is useful for GPU targets where the number of registers in the
class is not the best metric for determing which presser set is safer to

Future work may include adding more parameters to this function, like
for example, the current pressure level of the set or the amount that
the pressure will be increased/decreased.

Reviewers: qcolombet, escha, arsenm, atrick, MatzeB

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14806

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255795 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Adding llvm-profdata to the list of tools clang needs.
Chris Bieneman [Wed, 16 Dec 2015 18:30:36 +0000 (18:30 +0000)]
[CMake] Adding llvm-profdata to the list of tools clang needs.

Bootstrapping clang to generate PGO data (patches coming soon), requires llvm-profdata targets to be generated before clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255794 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReland "[llvm-readobj] Simplify usage of -codeview flag"
Reid Kleckner [Wed, 16 Dec 2015 18:28:12 +0000 (18:28 +0000)]
Reland "[llvm-readobj] Simplify usage of -codeview flag"

Relands r255790 with fixed tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255793 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLPVectorizer] Ensure dominated reduction values.
Charlie Turner [Wed, 16 Dec 2015 18:23:44 +0000 (18:23 +0000)]
[SLPVectorizer] Ensure dominated reduction values.

When considering incoming values as part of a reduction phi, ensure the
incoming value is dominated by said phi.

Failing to ensure this property causes miscompiles.

Fixes PR25787.

Many thanks to Mattias Eriksson for reporting, reducing and analyzing the
problem for me.

Differential Revision: http://reviews.llvm.org/D15580

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255792 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[llvm-readobj] Simplify usage of -codeview flag"
Reid Kleckner [Wed, 16 Dec 2015 18:19:34 +0000 (18:19 +0000)]
Revert "[llvm-readobj] Simplify usage of -codeview flag"

This reverts commit r255790.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255791 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-readobj] Simplify usage of -codeview flag
Reid Kleckner [Wed, 16 Dec 2015 18:18:39 +0000 (18:18 +0000)]
[llvm-readobj] Simplify usage of -codeview flag

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255790 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGenerate a clang CompilationDatabase when running CMake
Benjamin Kramer [Wed, 16 Dec 2015 18:17:45 +0000 (18:17 +0000)]
Generate a clang CompilationDatabase when running CMake

This generates a compile_commands.json file, which tells tools like
YouCompleteMe and clang_complete exactly how to build each source file.

Patch by Justin Lebar!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255789 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Use the new offset syntax for memory operands in inline asm.
Dan Gohman [Wed, 16 Dec 2015 18:14:49 +0000 (18:14 +0000)]
[WebAssembly] Use the new offset syntax for memory operands in inline asm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255788 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Sort relocs to avoid code corruption by linker optimization
Ulrich Weigand [Wed, 16 Dec 2015 18:12:40 +0000 (18:12 +0000)]
[SystemZ] Sort relocs to avoid code corruption by linker optimization

The SystemZ linkers provide an optimization to transform a general-
or local-dynamic TLS sequence into an initial-exec sequence if possible.
Do do that, the compiler generates a function call to __tls_get_offset,
which is a brasl instruction annotated with *two* relocations:

- a R_390_PLT32DBL to install __tls_get_offset as branch target
- a R_390_TLS_GDCALL / R_390_TLS_LDCALL to inform the linker that
  the TLS optimization should be performed if possible

If the optimization is performed, the brasl is replaced by an ld load

However, *both* relocs are processed independently by the linker.
Therefore it is crucial that the R_390_PLT32DBL is processed *first*
(installing the branch target for the brasl) and the R_390_TLS_GDCALL
is processed *second* (replacing the whole brasl with an ld).

If the relocs are swapped, the linker will first replace the brasl
with an ld, and *then* install the __tls_get_offset branch target
offset.  Since ld has a different layout than brasl, this may even
result in a completely different (or invalid) instruction; in any
case, the resulting code is corrupted.

Unfortunately, the way the MC common code sorts relocations causes
these two to *always* end up the wrong way around, resulting in
wrong code generation by the linker and crashes.

This patch overrides the sortRelocs routine to detect this particular
pair of relocs and enforce the required order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255787 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Fix assertion failure in adjustSubwordCmp
Ulrich Weigand [Wed, 16 Dec 2015 18:04:06 +0000 (18:04 +0000)]
[SystemZ] Fix assertion failure in adjustSubwordCmp

When comparing a zero-extended value against a constant small enough to
be in range of the inner type, it doesn't matter whether a signed or
unsigned compare operation (for the outer type) is being used.  This is
why the code in adjustSubwordCmp had this assertion:

    assert(C.ICmpType == SystemZICMP::Any &&
           "Signedness shouldn't matter here.");

assuming the the caller had already detected that fact.  However, it
turns out that there cases, in particular with always-true or always-
false conditions that have not been eliminated when compiling at -O0,
where this is not true.

Instead of failing an assertion if C.ICmpType is not SystemZICMP::Any
here, we can simply *set* it safely to SystemZICMP::Any, however.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255786 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Make memcpy lowering thread-safe
Tobias Edler von Koch [Wed, 16 Dec 2015 17:29:37 +0000 (17:29 +0000)]
[Hexagon] Make memcpy lowering thread-safe

This removes an unpleasant hack involving a global variable for special
lowering of certain memcpy calls. These are now lowered as intended in
EmitTargetCodeForMemcpy in the same way that other targets do it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255785 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NFC] Update horizontal reduction test cases.
Charlie Turner [Wed, 16 Dec 2015 17:22:24 +0000 (17:22 +0000)]
[NFC] Update horizontal reduction test cases.

These testcases no longer need to specify -slp-vectorize-hor, since it was
enabled by default in r252733.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255783 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Support more kinds of inline asm operands
Dan Gohman [Wed, 16 Dec 2015 17:15:17 +0000 (17:15 +0000)]
[WebAssembly] Support more kinds of inline asm operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255782 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstall runtime dlls in the INSTALL_DIR/bin directory. NFC
Sumanth Gundapaneni [Wed, 16 Dec 2015 17:07:15 +0000 (17:07 +0000)]
Install runtime dlls in the INSTALL_DIR/bin directory. NFC

One of the earlier patches updated the cmake rule to install the
runtime dlls in INSTALL_DIR/lib which is not correct. This patch
updates the rule to install CMake's RUNTIME in bin directory
Differential Revision: http://reviews.llvm.org/D15505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255781 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Packetizer] Add a check whether an instruction should be packetized now
Krzysztof Parzyszek [Wed, 16 Dec 2015 16:38:16 +0000 (16:38 +0000)]
[Packetizer] Add a check whether an instruction should be packetized now

Add a function VLIWPacketizerList::shouldAddToPacket, which will allow
specific implementations to decide if it is profitable to add given
instruction to the current packet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255780 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd RAII wrapper for gold plugin file management
Teresa Johnson [Wed, 16 Dec 2015 16:34:06 +0000 (16:34 +0000)]
Add RAII wrapper for gold plugin file management

Suggested in review of r255256.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255779 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd InaccessibleMemOnly and inaccessibleMemOrArgMemOnly attributes
Vaivaswatha Nagaraj [Wed, 16 Dec 2015 16:16:19 +0000 (16:16 +0000)]
Add InaccessibleMemOnly and inaccessibleMemOrArgMemOnly attributes

This patch introduces two new function attributes

InaccessibleMemOnly: This attribute indicates that the function may only access memory that is not accessible by the program/IR being compiled. This is a weaker form of ReadNone.
inaccessibleMemOrArgMemOnly: This attribute indicates that the function may only access memory that is either not accessible by the program/IR being compiled, or is pointed to by its pointer arguments. This is a weaker form of  ArgMemOnly

Test cases have been updated. This revision uses this (https://github.com/llvm-mirror/llvm/commit/d001932f3a8aa1ebd1555162fdce365f011bc292) as reference.

Reviewers: jmolloy, hfinkel

Subscribers: reames, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D15499

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255778 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SimplifyCFG] Don't create unnecessary PHIs
James Molloy [Wed, 16 Dec 2015 14:12:44 +0000 (14:12 +0000)]
[SimplifyCFG] Don't create unnecessary PHIs

In conditional store merging, we were creating PHIs when we didn't
need to. If the value to be predicated isn't defined in the block
we're predicating, then it doesn't need a PHI at all (because we only
deal with triangles and diamonds, any value not in the predicated BB
must dominate the predicated BB).

This fixes a large code size increase in some benchmarks in a popular embedded benchmark suite.

Now with a fix (and fixed tests) for the conformance issue seen in Chromium.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255767 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Add ARMv8.2-A FP16 vector instructions
Oliver Stannard [Wed, 16 Dec 2015 12:37:39 +0000 (12:37 +0000)]
[ARM] Add ARMv8.2-A FP16 vector instructions

ARMv8.2-A adds 16-bit floating point versions of all existing SIMD
floating-point instructions. This is an optional extension, so all of
these instructions require the FeatureFullFP16 subtarget feature.

Note that VFP without SIMD is not a valid combination for any version of
ARMv8-A, but I have ensured that these instructions all depend on both
FeatureNEON and FeatureFullFP16 for consistency.

Differential Revision: http://reviews.llvm.org/D15039

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255764 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Add ARMv8.2-A FP16 scalar instructions
Oliver Stannard [Wed, 16 Dec 2015 11:35:44 +0000 (11:35 +0000)]
[ARM] Add ARMv8.2-A FP16 scalar instructions

ARMv8.2-A adds 16-bit floating point versions of all existing VFP
floating-point instructions. This is an optional extension, so all of
these instructions require the FeatureFullFP16 subtarget feature.

The assembly for these instructions uses S registers (AArch32 does not
have H registers), but the instructions have ".f16" type specifiers
rather than ".f32" or ".f64". The top 16 bits of each source register
are ignored, and the top 16 bits of the destination register are set to

These instructions are mostly the same as the 32- and 64-bit versions,
but they use coprocessor 9 rather than 10 and 11.

Two new instructions, VMOVX and VINS, have been added to allow packing
and extracting two 16-bit floats stored in the top and bottom halves of
an S register.

New fixup kinds have been added for the PC-relative load and store
instructions, but no ELF relocations have been added as they have a
range of 512 bytes.

Differential Revision: http://reviews.llvm.org/D15038

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255762 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Improve shift combining
Michael Kuperstein [Wed, 16 Dec 2015 11:22:37 +0000 (11:22 +0000)]
[X86] Improve shift combining

This folds (ashr (shl a, [56,48,32,24,16]), SarConst)
into       (shl, (sext (a), [56,48,32,24,16] - SarConst))
or into    (lshr, (sext (a), SarConst - [56,48,32,24,16]))
depending on sign of (SarConst - [56,48,32,24,16])

sexts in X86 are MOVs.
The MOVs have the same code size as above SHIFTs (only SHIFT by 1 has lower code size).
However the MOVs have 2 advantages to SHIFTs on x86:
1. MOVs can write to a register that differs from source.
2. MOVs accept memory operands.

This fixes PR24373.

Patch by: evgeny.v.stupachenko@intel.com
Differential Revision: http://reviews.llvm.org/D13161

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255761 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SectionMemoryManager] Make better use of virtual memory
Keno Fischer [Wed, 16 Dec 2015 11:13:23 +0000 (11:13 +0000)]
[SectionMemoryManager] Make better use of virtual memory

Summary: On Windows, the allocation granularity can be significantly
larger than a page (64K), so with many small objects, just clearing
the FreeMem list rapidly leaks quite a bit of virtual memory space
(if not rss). Fix that by only removing those parts of the FreeMem
blocks that overlap pages for which we are applying memory permissions,
rather than dropping the FreeMem blocks entirely.

Reviewers: lhames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D15202

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255760 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRecommit LiveDebugValues pass after fixing a couple of minor issues.
Vikram TV [Wed, 16 Dec 2015 11:09:48 +0000 (11:09 +0000)]
Recommit LiveDebugValues pass after fixing a couple of minor issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255759 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove FileCheck from test case token_landingpad.ll.
Chen Li [Wed, 16 Dec 2015 06:27:09 +0000 (06:27 +0000)]
Remove FileCheck from test case token_landingpad.ll.
The test case only needs to make sure it does not crash LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255755 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMinor change to TailDuplication.cpp to turn on normalization when removing successor
Cong Hou [Wed, 16 Dec 2015 06:03:30 +0000 (06:03 +0000)]
Minor change to TailDuplication.cpp to turn on normalization when removing successor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255752 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMinor cleanup of Attribute code. NFC.
George Burgess IV [Wed, 16 Dec 2015 05:21:02 +0000 (05:21 +0000)]
Minor cleanup of Attribute code. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255751 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixed test case in rL255749: [SelectionDAGBuilder] Adds support for landingpads of...
Chen Li [Wed, 16 Dec 2015 05:05:18 +0000 (05:05 +0000)]
Fixed test case in rL255749: [SelectionDAGBuilder] Adds support for landingpads of token type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255750 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SelectionDAGBuilder] Adds support for landingpads of token type
Chen Li [Wed, 16 Dec 2015 04:48:42 +0000 (04:48 +0000)]
[SelectionDAGBuilder] Adds support for landingpads of token type

Summary: This patch adds a check in visitLandingPad to see if landingpad's result type is token type. If so, do not create DAG nodes for its exception pointer and selector value. This patch enables the back end to handle landingpads of token type.

Reviewers: JosephTremoulet, majnemer, rnk

Subscribers: sanjoy, llvm-commits

Differential Revision: http://reviews.llvm.org/D15405

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255749 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFuzzer: Fix library dependencies.
Peter Collingbourne [Wed, 16 Dec 2015 02:14:57 +0000 (02:14 +0000)]
Fuzzer: Fix library dependencies.

Newer versions of libstdc++ (4.9+), as well as libc++, depend directly on
libpthread from the standard library headers, so libfuzzer needs to declare
a standard library dependency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255745 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSpeculative fix for windows build
Philip Reames [Wed, 16 Dec 2015 01:24:05 +0000 (01:24 +0000)]
Speculative fix for windows build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255743 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[EarlyCSE] DSE of stores which write back loaded values
Philip Reames [Wed, 16 Dec 2015 01:01:30 +0000 (01:01 +0000)]
[EarlyCSE] DSE of stores which write back loaded values

Extend EarlyCSE with an additional style of dead store elimination. If we write back a value just read from that memory location, we can eliminate the store under the assumption that the value hasn't changed.

I'm implementing this mostly because I noticed the omission when looking at the code. It seemed strange to have InstCombine have a peephole which was more powerful than EarlyCSE. :)

Differential Revision: http://reviews.llvm.org/D15397

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255739 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IR] Add support for floating pointer atomic loads and stores
Philip Reames [Wed, 16 Dec 2015 00:49:36 +0000 (00:49 +0000)]
[IR] Add support for floating pointer atomic loads and stores

This patch allows atomic loads and stores of floating point to be specified in the IR and adds an adapter to allow them to be lowered via existing backend support for bitcast-to-equivalent-integer idiom.

Previously, the only way to specify a atomic float operation was to bitcast the pointer to a i32, load the value as an i32, then bitcast to a float. At it's most basic, this patch simply moves this expansion step to the point we start lowering to the backend.

This patch does not add canonicalization rules to convert the bitcast idioms to the appropriate atomic loads. I plan to do that in the future, but for now, let's simply add the support. I'd like to get instruction selection working through at least one backend (x86-64) without the bitcast conversion before canonicalizing into this form.

Similarly, I haven't yet added the target hooks to opt out of the lowering step I added to AtomicExpand. I figured it would more sense to add those once at least one backend (x86) was ready to actually opt out.

As you can see from the included tests, the generated code quality is not great. I plan on submitting some patches to fix this, but help from others along that line would be very welcome. I'm not super familiar with the backend and my ramp up time may be material.

Differential Revision: http://reviews.llvm.org/D15471

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255737 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[sancov] blacklist support.
Mike Aizatsky [Wed, 16 Dec 2015 00:31:48 +0000 (00:31 +0000)]
[sancov] blacklist support.

Using the blacklist the user can filter own unwanted functions
from all outputs. By default blacklist contains "fun:__sancov*" line.

Differential Revision: http://reviews.llvm.org/D15364

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255732 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo in r255720
Justin Bogner [Wed, 16 Dec 2015 00:17:34 +0000 (00:17 +0000)]
Fix typo in r255720

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255724 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTest commit: fixed spelling error in comment.
Wolfgang Pieb [Wed, 16 Dec 2015 00:08:18 +0000 (00:08 +0000)]
Test commit: fixed spelling error in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255721 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLPM: Simplify how passes mark loops for deletion. NFC
Justin Bogner [Wed, 16 Dec 2015 00:01:02 +0000 (00:01 +0000)]
LPM: Simplify how passes mark loops for deletion. NFC

When a pass removes a loop it currently has to reach up into the
LPPassManager's internals to update the state of the iteration over
loops. This reverse dependency results in a pretty awkward interplay
of the LPPassManager and its Passes.

Here, we change this to instead keep track of when a loop has become
"unlooped" in the Loop objects themselves, then the LPPassManager can
check this and manipulate its own state directly. This opens the door
to allow most of the loop passes to work without a backreference to
the LPPassManager.

I've kept passes calling the LPPassManager::deleteLoopFromQueue API
now so I could put an assert in to prove that this is NFC, but a later
pass will update passes just to preserve the LoopInfo directly and
stop referencing the LPPassManager completely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255720 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove one of the void casts used to suppress unused variable warning.
Richard Trieu [Tue, 15 Dec 2015 23:47:17 +0000 (23:47 +0000)]
Remove one of the void casts used to suppress unused variable warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255709 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUn-XFAIL JIT EH tests under [am]san.
Peter Collingbourne [Tue, 15 Dec 2015 23:46:21 +0000 (23:46 +0000)]
Un-XFAIL JIT EH tests under [am]san.

These tests started passing after libcxxabi's r255559, which fixed a problem
relating to how libcxxabi links its EH library. The test failures were
caused by an issue with libc++, not the sanitizers (confirmed by building a
pre-r255559 revision with libc++/libc++abi and without sanitizers), so they
should never have been XFAILed under the sanitizers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255708 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Make llvm.x86.seh.recoverfp work on x64
Reid Kleckner [Tue, 15 Dec 2015 23:40:58 +0000 (23:40 +0000)]
[WinEH] Make llvm.x86.seh.recoverfp work on x64

It adjusts from RSP-after-prologue to RBP, which is what SEH filters
need to do before they can use llvm.localrecover.

Fixes SEH filter captures, which were broken in r250088.

Issue reported by Alex Crichton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255707 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSuppress unused variable warning in the no-asserts build.
Evgeniy Stepanov [Tue, 15 Dec 2015 23:30:29 +0000 (23:30 +0000)]
Suppress unused variable warning in the no-asserts build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255706 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCast variable to void to resolve unused variable warning in non-asserts builds.
Richard Trieu [Tue, 15 Dec 2015 23:25:34 +0000 (23:25 +0000)]
Cast variable to void to resolve unused variable warning in non-asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255704 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix "Not having LAHF/SAHF" assert.
Hans Wennborg [Tue, 15 Dec 2015 23:21:46 +0000 (23:21 +0000)]
Fix "Not having LAHF/SAHF" assert.

It wants to assert that the subtarget is 64-bit, not the register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255703 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Set the code object work group segment size when targeting HSA
Tom Stellard [Tue, 15 Dec 2015 23:15:25 +0000 (23:15 +0000)]
AMDGPU/SI: Set the code object work group segment size when targeting HSA

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255702 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-objdump/MachODump] Shrink code a little bit. NFC.
Davide Italiano [Tue, 15 Dec 2015 23:14:21 +0000 (23:14 +0000)]
[llvm-objdump/MachODump] Shrink code a little bit. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255701 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] inline calls to fmaxf / llvm.maxnum.f32 using maxss (PR24475)
Sanjay Patel [Tue, 15 Dec 2015 23:11:43 +0000 (23:11 +0000)]
[x86] inline calls to fmaxf / llvm.maxnum.f32 using maxss (PR24475)

This patch improves on the suggested codegen from PR24475:

but only for the fmaxf() case to start, so we can sort out any bugs before
extending to fmin, f64, and vectors.

The fmax / maxnum definitions provide us flexibility for signed zeros, so the
only thing we have to worry about in this replacement sequence is NaN handling.

Note 1: It may be better to implement this as lowerFMAXNUM(), but that exposes
a problem: SelectionDAGBuilder::visitSelect() transforms compare/select
instructions into FMAXNUM nodes if we declare FMAXNUM legal or custom. Perhaps
that should be checking for NaN inputs or global unsafe-math before transforming?
As it stands, that bypasses a big set of optimizations that the x86 backend
already has in PerformSELECTCombine().

Note 2: The v2f32 test reveals another bug; the vector is extended to v4f32, so
we have completely unnecessary operations happening on undef elements of the

Differential Revision: http://reviews.llvm.org/D15294

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255700 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc] Tweak r255668: Use llvm_unreachable.
James Y Knight [Tue, 15 Dec 2015 23:07:16 +0000 (23:07 +0000)]
[Sparc] Tweak r255668: Use llvm_unreachable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255698 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCross-DSO control flow integrity (LLVM part).
Evgeniy Stepanov [Tue, 15 Dec 2015 23:00:08 +0000 (23:00 +0000)]
Cross-DSO control flow integrity (LLVM part).

An LTO pass that generates a __cfi_check() function that validates a
call based on a hash of the call-site-known type and the target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255693 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Set the code objects private segment size when targeting HSA.
Tom Stellard [Tue, 15 Dec 2015 22:55:30 +0000 (22:55 +0000)]
AMDGPU/SI: Set the code objects private segment size when targeting HSA.

Summary: I'm not sure how things worked before without this.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255692 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVectorizer] Refine loop vectorizer's register usage calculator by ignoring speci...
Cong Hou [Tue, 15 Dec 2015 22:45:09 +0000 (22:45 +0000)]
[LoopVectorizer] Refine loop vectorizer's register usage calculator by ignoring specific instructions.

(This is the third attempt to check in this patch, and the first two are r255454
and r255460. The once failed test file reg-usage.ll is now moved to
test/Transform/LoopVectorize/X86 directory with target datalayout and target
triple indicated.)

LoopVectorizationCostModel::calculateRegisterUsage() is used to estimate the
register usage for specific VFs. However, it takes into account many
instructions that won't be vectorized, such as induction variables,
GetElementPtr instruction, etc.. This makes the loop vectorizer too conservative
when choosing VF. In this patch, the induction variables that won't be
vectorized plus GetElementPtr instruction will be added to ValuesToIgnore set
so that their register usage won't be considered any more.

Differential revision: http://reviews.llvm.org/D15177

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255691 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA
Tom Stellard [Tue, 15 Dec 2015 22:39:36 +0000 (22:39 +0000)]
AMDGPU/SI: Emit constant variables in the .hsatext section when targeting HSA

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15426

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255689 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWrap include of <future> in some warning suppression pragmas
Reid Kleckner [Tue, 15 Dec 2015 22:10:30 +0000 (22:10 +0000)]
Wrap include of <future> in some warning suppression pragmas

Eventually we may need to sink this include to the .cpp file or
something to suport LLVM_ENABLE_THREADS=OFF, but this solves my
immediate problem of fixing the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255682 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Implement instruction selection for constant offsets in addresses.
Dan Gohman [Tue, 15 Dec 2015 22:01:29 +0000 (22:01 +0000)]
[WebAssembly] Implement instruction selection for constant offsets in addresses.

Add instruction patterns for matching load and store instructions with constant
offsets in addresses. The code is fairly redundant due to the need to replicate
everything between imm, tglobaldadr, and texternalsym, but this appears to be
common tablegen practice. The main alternative appears to be to introduce
matching functions with C++ code, but sticking with purely generated matchers
seems better for now.

Also note that this doesn't yet support offsets from getelementptr, which will
be the most common case; that will depend on a change in target-independent code
in order to set the NoUnsignedWrap flag, which I'll submit separately. Until
then, the testcase uses ptrtoint+add+inttoptr with a nuw on the add.

Also implement isLegalAddressingMode with an approximation of this.

Differential Revision: http://reviews.llvm.org/D15538

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255681 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInitialize all bytes in vp data (msan error)
Xinliang David Li [Tue, 15 Dec 2015 21:57:08 +0000 (21:57 +0000)]
Initialize all bytes in vp data (msan error)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255680 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for the .debug_macro section of the forthcoming DWARF 5 spec.
Eric Christopher [Tue, 15 Dec 2015 21:50:27 +0000 (21:50 +0000)]
Add support for the .debug_macro section of the forthcoming DWARF 5 spec.

Patch by B. Sivachandra Reddy!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255679 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix clang-cl self-host with MSVC 2013 STL std::bind implementation
Reid Kleckner [Tue, 15 Dec 2015 21:41:58 +0000 (21:41 +0000)]
Fix clang-cl self-host with MSVC 2013 STL std::bind implementation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255678 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Remove unused intrinsic llvm.x86.seh.restoreframe
Reid Kleckner [Tue, 15 Dec 2015 21:41:34 +0000 (21:41 +0000)]
[WinEH] Remove unused intrinsic llvm.x86.seh.restoreframe

We can clean this up now that we have the X86 CATCHRET instruction to
restore the FP, SP, and BP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255677 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Use operand bundles to describe call sites
David Majnemer [Tue, 15 Dec 2015 21:27:27 +0000 (21:27 +0000)]
[WinEH] Use operand bundles to describe call sites

SimplifyCFG allows tail merging with code which terminates in
unreachable which, in turn, makes it possible for an invoke to end up in
a funclet which it was not originally part of.

Using operand bundles on invokes allows us to determine whether or not
an invoke was part of a funclet in the source program.

Furthermore, it allows us to unambiguously answer questions about the
legality of inlining into call sites which the personality may have
trouble with.

Differential Revision: http://reviews.llvm.org/D15517

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255674 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTest cleanup -- remove duplicate run lines
Xinliang David Li [Tue, 15 Dec 2015 21:15:06 +0000 (21:15 +0000)]
Test cleanup -- remove duplicate run lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255673 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions
Tom Stellard [Tue, 15 Dec 2015 20:55:55 +0000 (20:55 +0000)]
AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instructions

We were previously selecting all constant loads to SMRD instructions and legalizing
the SMRDs with non-uniform addresses during the SIFixSGPRCopesPass.

This new solution is more simple and also generates much better code, because
the instruction selector is able to take advantage of all the MUBUF addressing
modes that are legalization pass wasn't able to.

We also no longer need to generate v_add_* instructions when we
have a uniform pointer and a non-uniform offset, as this is now folded into the
MUBUF instruction during instruction selection.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255672 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLLVM tutorial: fix broken links/anchors
Alex Denisov [Tue, 15 Dec 2015 20:50:29 +0000 (20:50 +0000)]
LLVM tutorial: fix broken links/anchors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255671 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCoverage code refactoring /NFC
Xinliang David Li [Tue, 15 Dec 2015 19:44:45 +0000 (19:44 +0000)]
Coverage code refactoring /NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255670 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLPM: Stop threading `Pass *` through all of the loop utility APIs. NFC
Justin Bogner [Tue, 15 Dec 2015 19:40:57 +0000 (19:40 +0000)]
LPM: Stop threading `Pass *` through all of the loop utility APIs. NFC

A large number of loop utility functions take a `Pass *` and reach
into it to find out which analyses to preserve. There are a number of
problems with this:

- The APIs have access to pretty well any Pass state they want, so
  it's hard to tell what they may or may not do.

- Other APIs have copied these and pass around a `Pass *` even though
  they don't even use it. Some of these just hand a nullptr to the API
  since the callers don't even have a pass available.

- Passes in the new pass manager don't work like the current ones, so
  the APIs can't be used as is there.

Instead, we should explicitly thread the analysis results that we
actually care about through these APIs. This is both simpler and more

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255669 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc] Fix handling of double incoming arguments on sparc little-endian.
James Y Knight [Tue, 15 Dec 2015 19:23:12 +0000 (19:23 +0000)]
[Sparc] Fix handling of double incoming arguments on sparc little-endian.

On SparcV8, doubles get passed in two 32-bit integer registers. The call
code was already handling endianness correctly, but the incoming
argument code was not -- it got the two halves in opposite order.

Also remove some dead code in LowerFormalArguments_32 to handle
less-than-32bit values, which can't actually happen.

Finally, add some test cases for the 32-bit calling convention, cribbed
from the 64abi.ll test, and run for both big and little-endian.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255668 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Docs] Fix Unexpected indentation errors.
Akira Hatanaka [Tue, 15 Dec 2015 19:11:48 +0000 (19:11 +0000)]
[Docs] Fix Unexpected indentation errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255665 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] MOVPC32r should only emit CFI adjustments when needed
Michael Kuperstein [Tue, 15 Dec 2015 18:50:32 +0000 (18:50 +0000)]
[X86] MOVPC32r should only emit CFI adjustments when needed

We only want to emit CFI adjustments when actually using DWARF.
This fixes PR25828.

Differential Revision: http://reviews.llvm.org/D15522

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255664 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Implement AMDGPUTargetTransformInfo::isSourceOfDivergence()
Tom Stellard [Tue, 15 Dec 2015 18:04:38 +0000 (18:04 +0000)]
AMDGPU/SI: Implement AMDGPUTargetTransformInfo::isSourceOfDivergence()

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15476

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255661 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SimplifyCFG] allow speculation of exactly one expensive instruction (PR24818)
Sanjay Patel [Tue, 15 Dec 2015 17:38:29 +0000 (17:38 +0000)]
[SimplifyCFG] allow speculation of exactly one expensive instruction (PR24818)

This is the last general step to allow more IR-level speculation with a safety harness in place in CodeGenPrepare.

The intent is to restore the behavior enabled by:

but prevent bad performance such as:

Earlier patches in this sequence:
D12882 (disable SimplifyCFG speculation for expensive instructions)
D13297 (have CGP despeculate expensive ops)
D14630 (have CGP despeculate special versions of cttz/ctlz)

As shown in the test cases, we only have two instructions currently affected: ctz for some x86 and fdiv generally.
Allowing exactly one expensive instruction is a bit of a hack, but it lines up with what is currently implemented
in CGP. If we make the despeculation more general in CGP, we can make the speculation here more liberal.

A follow-up patch will adjust the cost for sqrt and possibly other typically expensive math intrinsics (currently
everything is cheap by default). GPU targets would likely want to override those expensive default costs (just as
they probably should already override the cost of div/rem) because just about any math is cheaper than control-flow
on those targets.

Differential Revision: http://reviews.llvm.org/D15213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255660 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-profdata] Add support for weighted merge of profile data (2nd try)
Nathan Slingerland [Tue, 15 Dec 2015 17:37:09 +0000 (17:37 +0000)]
[llvm-profdata] Add support for weighted merge of profile data (2nd try)

This change adds support for specifying a weight when merging profile data with the llvm-profdata tool.
Weights are specified by using the --weighted-input=<weight>,<filename> option. Input files not specified
with this option (normal positional list after options) are given a default weight of 1.

Adding support for arbitrary weighting of input profile data allows for relative importance to be placed on the
input data from multiple training runs.

Both sampled and instrumented profiles are supported.

Reviewers: davidxl, dnovillo, bogner, silvas

Subscribers: silvas, davidxl, llvm-commits

Differential Revision: http://reviews.llvm.org/D15306

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255659 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: mark ldexp LibCalls as unavailable
Nicolai Hahnle [Tue, 15 Dec 2015 17:24:15 +0000 (17:24 +0000)]
AMDGPU: mark ldexp LibCalls as unavailable

The LibCallSimplifier will turn llvm.exp2.* intrinsics into ldexp* libcalls
which do not make sense with the AMDGPU backend.

In the long run, we'll want an llvm.ldexp.* intrinsic to properly make use of
this optimization, but this works around the problem for now.

See also: http://reviews.llvm.org/D14327 (suggested llvm.ldexp.* implementation)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709

Reviewers: arsenm, tstellarAMD

Differential Revision: http://reviews.llvm.org/D14990

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255658 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix bitcast between v2f32 and f64
Tom Stellard [Tue, 15 Dec 2015 17:11:17 +0000 (17:11 +0000)]
AMDGPU/SI: Fix bitcast between v2f32 and f64

The radeonsi fp64 support can hit these now that some redundant bitcasts
are folded.

Patch by: Michel Dänzer

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255657 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Smaller code for materializing 32-bit 1 and -1 constants
Hans Wennborg [Tue, 15 Dec 2015 17:10:28 +0000 (17:10 +0000)]
[X86] Smaller code for materializing 32-bit 1 and -1 constants

"movl $-1, %eax" is 5 bytes, "xorl %eax, %eax; decl %eax" is 3 bytes.
This commit makes LLVM use the latter when optimizing for size.

Differential Revision: http://reviews.llvm.org/D14971

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255656 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: update expected torture test failures
JF Bastien [Tue, 15 Dec 2015 17:07:07 +0000 (17:07 +0000)]
WebAssembly: update expected torture test failures

We now have 252 expected failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255654 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Preprocess mapped instructions before lowering to MC
Krzysztof Parzyszek [Tue, 15 Dec 2015 17:05:45 +0000 (17:05 +0000)]
[Hexagon] Preprocess mapped instructions before lowering to MC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255653 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add llvm.amdgcn.mbcnt.* intrinsics
Tom Stellard [Tue, 15 Dec 2015 17:02:52 +0000 (17:02 +0000)]
AMDGPU/SI: Add llvm.amdgcn.mbcnt.* intrinsics

These are meant to be used instead of the llvm.SI.tid intrinsic which will
be deprecated at some point.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15475

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255652 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsics
Tom Stellard [Tue, 15 Dec 2015 17:02:49 +0000 (17:02 +0000)]
AMDGPU/SI: Add llvm.amdgcn.v.interp.p[12] intrinsics

These are meant to be used instead of the llvm.SI.fs.interp intrinsic which
will be deprecated at some point.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255651 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add getShaderType() function to Utils/
Tom Stellard [Tue, 15 Dec 2015 16:26:16 +0000 (16:26 +0000)]
AMDGPU/SI: Add getShaderType() function to Utils/

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15424

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255650 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcasts between FP and INT values using direct moves
Nemanja Ivanovic [Tue, 15 Dec 2015 14:50:34 +0000 (14:50 +0000)]
Bitcasts between FP and INT values using direct moves

This patch corresponds to review:

This patch was meant to land in revision 255246, but I accidentally uploaded
the patch that corresponds to http://reviews.llvm.org/D15372 in that revision

Thereby, this patch is the actual Bitcasts using direct moves patch, whereas
http://reviews.llvm.org/rL255246 actually corresponds to

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255649 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] adding PKU feature flag
Asaf Badouh [Tue, 15 Dec 2015 13:35:29 +0000 (13:35 +0000)]
[x86] adding PKU feature flag

the feature flag is essential for RDPKRU and WRPKRU instruction
more about the instruction can be found in the SDM rev 56, vol 2 from http://www.intel.com/sdm

Differential Revision: http://reviews.llvm.org/D15491

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255644 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDo not try to use i8 and i16 versions of FP_TO_U/SINT soft float library calls
Michael Kuperstein [Tue, 15 Dec 2015 12:55:50 +0000 (12:55 +0000)]
Do not try to use i8 and i16 versions of FP_TO_U/SINT soft float library calls

It appears that neither compiler-rt nor the gnu soft-float libraries actually
implement these conversions. Instead of emitting calls to library functions
that don't exist, handle it similarly to the way we handle i8 -> float and
i16 -> float conversions: call the i32 library function, and adjust the type.

Differential Revision: http://reviews.llvm.org/D15151

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255643 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDefine a feature for __float128 support in the PPC back end
Nemanja Ivanovic [Tue, 15 Dec 2015 12:19:34 +0000 (12:19 +0000)]
Define a feature for __float128 support in the PPC back end

This patch corresponds to review:

In preparation for supporting IEEE Quad precision floating point,
this patch simply defines a feature to specify the target supports this.
For now, nothing is done with the target feature, we just don't want
warnings from the Clang FE when a user specifies -mfloat128.
Calling convention and other related work will add to this patch in
the near future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255642 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove the successor list update in TailDuplication.cpp.
Cong Hou [Tue, 15 Dec 2015 10:10:40 +0000 (10:10 +0000)]
Improve the successor list update in TailDuplication.cpp.

This patch improves a temporary fix in r255530 so that we can normalize
successor list without trigger assertion failures in tail duplication pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255638 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstCombineLoadStoreAlloca.cpp: Avoid instantiating Twine.
NAKAMURA Takumi [Tue, 15 Dec 2015 09:37:31 +0000 (09:37 +0000)]
InstCombineLoadStoreAlloca.cpp: Avoid instantiating Twine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255637 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PassManagerBuilder] Add a few more scalar optimization passes
James Molloy [Tue, 15 Dec 2015 09:24:01 +0000 (09:24 +0000)]
[PassManagerBuilder] Add a few more scalar optimization passes

This patch does two things:
  1. mem2reg is now run immediately after globalopt. Now that globalopt
     can localize variables more aggressively, it makes sense to lower
     them to SSA form earlier rather than later so they can benefit from
     the full set of optimization passes.

  2. More scalar optimizations are run after the loop optimizations in
     LTO mode. The loop optimizations (especially indvars) can clean up
     scalar code sufficiently to make it worthwhile running more scalar
     passes. I've particularly added SCCP here as it isn't run anywhere
     else in the LTO pass pipeline.

Mem2reg is super cheap and shouldn't affect compilation time at all. The
rest of the added passes are in the LTO pipeline only so doesn't affect
the vast majority of compilations, just the link step.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255634 91177308-0d34-0410-b5e6-96231b3b80d8