oota-llvm.git
10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:23:13 +0000 (00:23 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160482 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:17:40 +0000 (00:17 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160480 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:15:11 +0000 (00:15 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160479 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTweak prose.
Chad Rosier [Thu, 19 Jul 2012 00:11:45 +0000 (00:11 +0000)]
Tweak prose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160478 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:11:40 +0000 (00:11 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160477 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:06:06 +0000 (00:06 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160476 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:04:14 +0000 (00:04 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160475 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:01:33 +0000 (00:01 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160473 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Thu, 19 Jul 2012 00:01:00 +0000 (00:01 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160472 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tabs.
Bill Wendling [Wed, 18 Jul 2012 23:58:37 +0000 (23:58 +0000)]
Remove tabs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160471 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove around some enum elements so that lastMRM corrects gets assigned 56, which
Richard Trieu [Wed, 18 Jul 2012 23:04:22 +0000 (23:04 +0000)]
Move around some enum elements so that lastMRM corrects gets assigned 56, which
is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160465 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTblGen: Tweak to pretty-print DAGISel.inc a bit better.
Jim Grosbach [Wed, 18 Jul 2012 22:41:03 +0000 (22:41 +0000)]
TblGen: Tweak to pretty-print DAGISel.inc a bit better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160463 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAllow PointerIntPairs to be created from const void *.
Jordan Rose [Wed, 18 Jul 2012 21:58:49 +0000 (21:58 +0000)]
Allow PointerIntPairs to be created from const void *.

For a measure of safety, this conversion is only permitted if the
stored pointer type can also be created from a const void *.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160456 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoX86: remove redundant cmp against zero.
Manman Ren [Wed, 18 Jul 2012 21:40:01 +0000 (21:40 +0000)]
X86: remove redundant cmp against zero.

Updated OptimizeCompare in peephole to remove redundant cmp against zero.
We only remove Compare if CF and OF are not used.

rdar://11855129

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160454 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoThis patch fixes 8 out of 20 unexpected failures in "make check"
Preston Gurd [Wed, 18 Jul 2012 20:49:17 +0000 (20:49 +0000)]
This patch fixes 8 out of 20 unexpected failures in "make check"
when run on an Intel Atom processor. The failures have arisen due
to changes elsewhere in the trunk over the past 8 weeks or so.

These failures were not detected by the Atom buildbot because the
CPU on the Atom buildbot was not being detected as an Atom CPU.
The fix for this problem is in Host.cpp and X86Subtarget.cpp, but
shall remain commented out until the current set of Atom test failures
are fixed.

Patch by Andy Zhang and Tyler Nowicki!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdding some debug information to PassManager
Victor Oliveira [Wed, 18 Jul 2012 19:59:29 +0000 (19:59 +0000)]
Adding some debug information to PassManager

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160446 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoWhitespace.
Chad Rosier [Wed, 18 Jul 2012 19:35:16 +0000 (19:35 +0000)]
Whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160445 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix a somewhat nasty crasher in PR13378. This crashes inside of
Chandler Carruth [Wed, 18 Jul 2012 18:58:22 +0000 (18:58 +0000)]
Fix a somewhat nasty crasher in PR13378. This crashes inside of
LiveIntervals due to the two-addr pass generating bogus MI code.

The crux of the issue was a loop nesting problem. The intent of the code
which attempts to transform instructions before converting them to
two-addr form is to defer and reprocess any transformed instructions as
the second processing is likely to have more opportunities to coalesce
copies, etc. Unfortunately, there was one section of processing that was
not deferred -- the INSERT_SUBREG rewriting. Due to quirks of how this
rewriting proceeded, not only did it occur early, it removed the bits of
information needed for the deferred processing to correctly generate the
necessary two address form (specifically inserting a copy), but didn't
trigger any immediate assertions and produced what appeared to be
already valid two-address from code. Thus, the assertion only fired much
later in the pipeline.

The fix is to hoist the transformation logic up layer to where it can
more firmly defer all further processing, and to teach the normal
processing to handle an edge case previously handled as part of the
transformation logic. This edge case (already matched tied register
operands) needs to *not* defer any steps.

As has been brought up repeatedly in the process: wow does this code
need refactoring. I *may* squeeze in some time to at least bring sanity
to this loop... but wow... =]

Thanks to Jakob for helpful hints on the way here, and the review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160443 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.
Andrew Trick [Wed, 18 Jul 2012 18:34:27 +0000 (18:34 +0000)]
Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.

Based on Evan's suggestion without a commitable test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160441 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agowhitespace
Andrew Trick [Wed, 18 Jul 2012 18:34:24 +0000 (18:34 +0000)]
whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160440 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdded unit test for PR13361: LSR + SCEV "hangs" on reasonably sized test.
Andrew Trick [Wed, 18 Jul 2012 18:07:52 +0000 (18:07 +0000)]
Added unit test for PR13361: LSR + SCEV "hangs" on reasonably sized test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160439 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agotest commit
Victor Oliveira [Wed, 18 Jul 2012 17:53:05 +0000 (17:53 +0000)]
test commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160438 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd some missed ELF constants definitions:
Simon Atanasyan [Wed, 18 Jul 2012 14:12:32 +0000 (14:12 +0000)]
Add some missed ELF constants definitions:
- section types
- dynamic table entries tags
- state flags for DT_FLAGS_1 entry

The patch reviewed by Rafael Espindola.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160433 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoUpdate config.h.cmake corresponding to config.h.in.
NAKAMURA Takumi [Wed, 18 Jul 2012 09:17:02 +0000 (09:17 +0000)]
Update config.h.cmake corresponding to config.h.in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160431 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoThe vbroadcast family of instructions has 'fallback patterns' in case where the
Nadav Rotem [Wed, 18 Jul 2012 08:14:48 +0000 (08:14 +0000)]
The vbroadcast family of instructions has 'fallback patterns' in case where the
load source operand is used by multiple nodes. The v2i64 broadcast was emulated
by shuffling the two lower i32 elements to the upper two.
We had a bug in the immediate used for the broadcast.
Replacing 0 to 0x44.
0x44 means [01|00|01|00] which corresponds to the correct lane.

Patch by Michael Kuperstein.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160430 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMips specific inline asm operand modifier 'M':
Jack Carter [Wed, 18 Jul 2012 06:41:36 +0000 (06:41 +0000)]
Mips specific inline asm operand modifier 'M':

Print the high order register of a double word register operand.

In 32 bit mode, a 64 bit double word integer will be represented
by 2 32 bit registers. This modifier causes the high order register
to be used in the asm expression. It is useful if you are using
doubles in assembler and continue to control register to variable
relationships.

This patch also fixes a related bug in a previous patch:

    case 'D': // Second part of a double word register operand
    case 'L': // Low order register of a double word register operand
    case 'M': // High order register of a double word register operand

I got 'D' and 'M' confused. The second part of a double word operand
will only match 'M' for one of the endianesses. I had 'L' and 'D'
be the opposite twins when 'L' and 'M' are.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160429 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoSCEVTraversal: Add a visited set.
Andrew Trick [Wed, 18 Jul 2012 05:14:03 +0000 (05:14 +0000)]
SCEVTraversal: Add a visited set.

Expression trees may be DAGs. Make sure traversal has linear complexity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160426 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove tab characters.
Craig Topper [Wed, 18 Jul 2012 04:59:16 +0000 (04:59 +0000)]
Remove tab characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160425 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix typo in error message and remove some tab characters.
Craig Topper [Wed, 18 Jul 2012 04:36:35 +0000 (04:36 +0000)]
Fix typo in error message and remove some tab characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160423 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoindvars: drive by heuristics fix.
Andrew Trick [Wed, 18 Jul 2012 04:35:13 +0000 (04:35 +0000)]
indvars: drive by heuristics fix.

Minor oversight noticed by inspection. Sorry no unit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160422 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoindvars: Linear function test replace should avoid reusing undef.
Andrew Trick [Wed, 18 Jul 2012 04:35:10 +0000 (04:35 +0000)]
indvars: Linear function test replace should avoid reusing undef.

Fixes PR13371: indvars pass incorrectly substitutes 'undef' values.

I do not like this fix. It's needed until/unless the meaning of undef
changes. It attempts to be complete according to the IR spec, but I
don't have much confidence in the implementation given the difficulty
testing undefined behavior. Worse, this invalidates some of my
hard-fought work on indvars and LSR to optimize pointer induction
variables. It results benchmark regressions, which I'll track
internally. On x86_64 no LTO I see:

-3% huffbench
-3% 400.perlbench
-8% fhourstones

My only suggestion for recovering is to change the meaning of
undef. If we could trust an arbitrary instruction to produce a some
real value that can be manipulated (e.g. incremented) according to
non-undef rules, then this case could be easily handled with SCEV.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160421 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake x86 asm parser to check for xmm vs ymm for index register in gather instructions...
Craig Topper [Wed, 18 Jul 2012 04:11:12 +0000 (04:11 +0000)]
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFixed few warnings.
Galina Kistanova [Wed, 18 Jul 2012 04:06:49 +0000 (04:06 +0000)]
Fixed few warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160419 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoignore 'invoke @llvm.donothing', but still keep the edge to the continuation BB
Nuno Lopes [Wed, 18 Jul 2012 00:07:17 +0000 (00:07 +0000)]
ignore 'invoke @llvm.donothing', but still keep the edge to the continuation BB

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160411 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMore replacing of target-dependent intrinsics with target-indepdent
Joel Jones [Wed, 18 Jul 2012 00:02:16 +0000 (00:02 +0000)]
More replacing of  target-dependent intrinsics with target-indepdent
intrinsics.  The second instruction(s) to be handled are the vector versions
of count set bits (ctpop).

The changes here are to clang so that it generates a target independent
vector ctpop when it sees an ARM dependent vector bits set count.  The changes
in llvm are to match the target independent vector ctpop and in
VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM
dependent vector pop counts with target-independent ctpops.  There are also
changes to an existing test case in llvm for ARM vector count instructions and
to a test for the bitcode upgrade.

<rdar://problem/11892519>

There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoApparently it's possible to do an 'invoke asm'.
Nuno Lopes [Tue, 17 Jul 2012 23:51:33 +0000 (23:51 +0000)]
Apparently it's possible to do an 'invoke asm'.
Update the language reference to reflect that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160408 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoClean up Mips16InstrFormats.td and Mips16InstrInfo.td.
Akira Hatanaka [Tue, 17 Jul 2012 22:55:34 +0000 (22:55 +0000)]
Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.

Patch by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd test case for r160387
Evan Cheng [Tue, 17 Jul 2012 19:40:05 +0000 (19:40 +0000)]
Add test case for r160387

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160389 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoBack out r160101 and instead implement a dag combine to recover from instcombine...
Evan Cheng [Tue, 17 Jul 2012 18:54:11 +0000 (18:54 +0000)]
Back out r160101 and instead implement a dag combine to recover from instcombine transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160387 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTableGen: Pattern<> references to null_frag are a nop.
Jim Grosbach [Tue, 17 Jul 2012 18:39:36 +0000 (18:39 +0000)]
TableGen: Pattern<> references to null_frag are a nop.

A standalone pattern defined in a multiclass expansion should handle
null_frag references just like patterns on instructions. Follow-up to
r160333.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160384 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix broken ipo_ext_iterator constructors.
Jakob Stoklund Olesen [Tue, 17 Jul 2012 17:57:25 +0000 (17:57 +0000)]
Fix broken ipo_ext_iterator constructors.

These functions have obviously never been used before.
They should be identical to the idf_ext_iterator counterparts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160381 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd some trace output to TwoAddressInstructionPass.
Jakob Stoklund Olesen [Tue, 17 Jul 2012 17:57:23 +0000 (17:57 +0000)]
Add some trace output to TwoAddressInstructionPass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160380 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRemove unused variable.
Benjamin Kramer [Tue, 17 Jul 2012 17:00:11 +0000 (17:00 +0000)]
Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160372 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agosimplify getSetSize() per Duncan's comments
Nuno Lopes [Tue, 17 Jul 2012 15:43:59 +0000 (15:43 +0000)]
simplify getSetSize() per Duncan's comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160368 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agollvm/test/Transforms/LoopRotate/PhiRename-1.ll: FileCheck-ize. It fixes PR13301.
NAKAMURA Takumi [Tue, 17 Jul 2012 15:43:17 +0000 (15:43 +0000)]
llvm/test/Transforms/LoopRotate/PhiRename-1.ll: FileCheck-ize. It fixes PR13301.

It began choking since Chandler's r159547, possibly due to improper expression on grep from TclParser to ShParser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160367 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAllow for customized graph edge pruning in PostOrderIterator.h
Jakob Stoklund Olesen [Tue, 17 Jul 2012 15:35:40 +0000 (15:35 +0000)]
Allow for customized graph edge pruning in PostOrderIterator.h

Make it possible to prune individual graph edges from a post-order
traversal by specializing the po_iterator_storage template. Previously,
it was only possible to prune full graph nodes. Edge pruning makes it
possible to remove loop back-edges, for example.

Also replace the existing DFSetTraits customization hook with a
po_iterator_storage method for observing the post-order. DFSetTraits was
only used by LoopIterator.h which now provides a po_iterator_storage
specialization.

Thanks to Sean and Chandler for reviewing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160366 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoImprove behavior of DebugInfoEntryMinimal::getSubprogramName() introduced in r159512.
Alexey Samsonov [Tue, 17 Jul 2012 15:28:35 +0000 (15:28 +0000)]
Improve behavior of DebugInfoEntryMinimal::getSubprogramName() introduced in r159512.
To fetch a subprogram name we should not only inspect the DIE for this subprogram, but optionally inspect
its specification, or its abstract origin (even if there is no inlining), or even specification of an abstract origin.

Reviewed by Benjamin Kramer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160365 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] more code to merge crash callbacks. Doesn't fully work yet, but allows to...
Kostya Serebryany [Tue, 17 Jul 2012 11:04:12 +0000 (11:04 +0000)]
[asan] more code to merge crash callbacks. Doesn't fully work yet, but allows to hold performance experiments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160361 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix a crash in the legalization of large vectors.
Nadav Rotem [Tue, 17 Jul 2012 09:07:37 +0000 (09:07 +0000)]
Fix a crash in the legalization of large vectors.
When truncating a result of a vector that is split we need
to use the result of the split vector, and not re-split the dead node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160357 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoImplement r160312 as target indepedenet dag combine.
Evan Cheng [Tue, 17 Jul 2012 08:31:11 +0000 (08:31 +0000)]
Implement r160312 as target indepedenet dag combine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert commit r160307. We decide to move builtins selection to the backend.
Simon Atanasyan [Tue, 17 Jul 2012 08:14:45 +0000 (08:14 +0000)]
Revert commit r160307. We decide to move builtins selection to the backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160352 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake sure constant bitwidth is <= 64 bit before calling getSExtValue().
Evan Cheng [Tue, 17 Jul 2012 07:47:50 +0000 (07:47 +0000)]
Make sure constant bitwidth is <= 64 bit before calling getSExtValue().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160350 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoThis is another case where instcombine demanded bits optimization created
Evan Cheng [Tue, 17 Jul 2012 06:53:39 +0000 (06:53 +0000)]
This is another case where instcombine demanded bits optimization created
large immediates. Add dag combine logic to recover in case the large
immediates doesn't fit in cmp immediate operand field.

int foo(unsigned long l) {
  return (l>> 47) == 1;
}

we produce

  %shr.mask = and i64 %l, -140737488355328
  %cmp = icmp eq i64 %shr.mask, 140737488355328
  %conv = zext i1 %cmp to i32
  ret i32 %conv

which codegens to

movq    $0xffff800000000000,%rax
andq    %rdi,%rax
movq    $0x0000800000000000,%rcx
cmpq    %rcx,%rax
sete    %al
movzbl    %al,%eax
ret

TargetLowering::SimplifySetCC would transform
(X & -256) == 256 -> (X >> 8) == 1
if the immediate fails the isLegalICmpImmediate() test. For x86,
that's immediates which are not a signed 32-bit immediate.

Based on a patch by Eli Friedman.

PR10328
rdar://9758774

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoReapply r160340. LSR: Limit CollectSubexprs.
Andrew Trick [Tue, 17 Jul 2012 05:30:37 +0000 (05:30 +0000)]
Reapply r160340. LSR: Limit CollectSubexprs.

Speculatively fix crashes by code inspection. Can't reproduce them yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160344 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "LSR: try not to blow up solving combinatorial problems brute force."
Andrew Trick [Tue, 17 Jul 2012 05:05:21 +0000 (05:05 +0000)]
Revert "LSR: try not to blow up solving combinatorial problems brute force."

Some units tests crashed on a different platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160341 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoLSR: try not to blow up solving combinatorial problems brute force.
Andrew Trick [Tue, 17 Jul 2012 05:00:56 +0000 (05:00 +0000)]
LSR: try not to blow up solving combinatorial problems brute force.

This places limits on CollectSubexprs to constrains the number of
reassociation possibilities. It limits the recursion depth and skips
over chains of nested recurrences outside the current loop.

Fixes PR13361. Although underlying SCEV behavior is still potentially bad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160340 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTableGen: Allow conditional instruction pattern in multiclass.
Jim Grosbach [Tue, 17 Jul 2012 00:47:06 +0000 (00:47 +0000)]
TableGen: Allow conditional instruction pattern in multiclass.

Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.

For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
  def _x : myI<(outs rc:), (ins rc:), []>;
  def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}

defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.
Akira Hatanaka [Mon, 16 Jul 2012 23:56:51 +0000 (23:56 +0000)]
Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160329 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDefer checking for registers in the MC AsmMatcher until the after user-defined match...
Owen Anderson [Mon, 16 Jul 2012 23:20:09 +0000 (23:20 +0000)]
Defer checking for registers in the MC AsmMatcher until the after user-defined match classes have been checked.  This allows the creation of MatchClass's that are supersets of a register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agofix PR13339 (remove the predecessor from the unwind BB when removing an invoke)
Nuno Lopes [Mon, 16 Jul 2012 22:49:40 +0000 (22:49 +0000)]
fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160325 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoteach ConstantRange that zero times X is always zero
Nuno Lopes [Mon, 16 Jul 2012 20:47:16 +0000 (20:47 +0000)]
teach ConstantRange that zero times X is always zero

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160317 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFor something like
Evan Cheng [Mon, 16 Jul 2012 19:35:43 +0000 (19:35 +0000)]
For something like
uint32_t hi(uint64_t res)
{
        uint_32t hi = res >> 32;
        return !hi;
}

llvm IR looks like this:
define i32 @hi(i64 %res) nounwind uwtable ssp {
entry:
  %lnot = icmp ult i64 %res, 4294967296
  %lnot.ext = zext i1 %lnot to i32
  ret i32 %lnot.ext
}

The optimizer has optimize away the right shift and truncate but the resulting
constant is too large to fit in the 32-bit immediate field. The resulting x86
code is worse as a result:
        movabsq $4294967296, %rax       ## imm = 0x100000000
        cmpq    %rax, %rdi
        sbbl    %eax, %eax
        andl    $1, %eax

This patch teaches the x86 lowering code to handle ult against a large immediate
with trailing zeros. It will issue a right shift and a truncate followed by
a comparison against a shifted immediate.
        shrq    $32, %rdi
        testl   %edi, %edi
        sete    %al
        movzbl  %al, %eax

It also handles a ugt comparison against a large immediate with trailing bits
set. i.e. X >  0x0ffffffff -> (X >> 32) >= 1

rdar://11866926

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMinor cleanup and docs.
Nadav Rotem [Mon, 16 Jul 2012 18:56:39 +0000 (18:56 +0000)]
Minor cleanup and docs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160311 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMIPS: Create two definitions for __builtin_mips_shll_qb builtin.
Simon Atanasyan [Mon, 16 Jul 2012 18:51:39 +0000 (18:51 +0000)]
MIPS: Create two definitions for __builtin_mips_shll_qb builtin.
The first variant accepts immediate number as the second argument.
The second variant accepts register operand as the second argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160307 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMake ComputeDemandedBits return a deterministic result when computing an AssertZext...
Nadav Rotem [Mon, 16 Jul 2012 18:34:53 +0000 (18:34 +0000)]
Make ComputeDemandedBits return a deterministic result when computing an AssertZext value.
In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits
reported that some of the bits were both known to be one and known to be zero.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160305 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "AMDGPU: Add core backend files for R600/SI codegen v6"
Tom Stellard [Mon, 16 Jul 2012 18:19:53 +0000 (18:19 +0000)]
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"

This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "include/llvm: Add R600 Intrinsics v6"
Tom Stellard [Mon, 16 Jul 2012 18:19:48 +0000 (18:19 +0000)]
Revert "include/llvm: Add R600 Intrinsics v6"

This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160302 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Build script changes for R600/SI Codegen v6"
Tom Stellard [Mon, 16 Jul 2012 18:19:46 +0000 (18:19 +0000)]
Revert "Build script changes for R600/SI Codegen v6"

This reverts commit e3013202259ed1e006c21817c63cf25d75982721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160301 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "test/CodeGen/R600: Add some basic tests v6"
Tom Stellard [Mon, 16 Jul 2012 18:19:43 +0000 (18:19 +0000)]
Revert "test/CodeGen/R600: Add some basic tests v6"

This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160300 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder...
Tom Stellard [Mon, 16 Jul 2012 18:19:41 +0000 (18:19 +0000)]
Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>"

This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160299 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCom...
Tom Stellard [Mon, 16 Jul 2012 18:19:40 +0000 (18:19 +0000)]
Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen."

This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160298 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional...
Tom Stellard [Mon, 16 Jul 2012 18:19:38 +0000 (18:19 +0000)]
Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator..."

This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160297 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn...
Tom Stellard [Mon, 16 Jul 2012 18:19:37 +0000 (18:19 +0000)]
Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0)."

This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160296 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert "Target/AMDGPU: Fix includes, or msvc build failed."
Tom Stellard [Mon, 16 Jul 2012 18:19:32 +0000 (18:19 +0000)]
Revert "Target/AMDGPU: Fix includes, or msvc build failed."

This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160295 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agomake ConstantRange::getSetSize() properly compute the size of wrapped and full sets.
Nuno Lopes [Mon, 16 Jul 2012 18:08:12 +0000 (18:08 +0000)]
make ConstantRange::getSetSize() properly compute the size of wrapped and full sets.
Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160294 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoWith r160248 in place this code is no longer needed.
Chad Rosier [Mon, 16 Jul 2012 17:42:13 +0000 (17:42 +0000)]
With r160248 in place this code is no longer needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] a bit more refactoring, addressed some of the style comments from chandlerc...
Kostya Serebryany [Mon, 16 Jul 2012 17:12:07 +0000 (17:12 +0000)]
[asan] a bit more refactoring, addressed some of the style comments from chandlerc, partially implemented crash callback merging (under flag)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160290 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMSVC's implementation of isalnum will assert on characters > 255, so we need to use...
Aaron Ballman [Mon, 16 Jul 2012 16:18:18 +0000 (16:18 +0000)]
MSVC's implementation of isalnum will assert on characters > 255, so we need to use an unsigned char to ensure the integer promotion happens properly.  This fixes an assert in debug builds with CodeGen\X86\utf8.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160286 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] refactor instrumentation to allow merging the crash callbacks (not fully imple...
Kostya Serebryany [Mon, 16 Jul 2012 16:15:40 +0000 (16:15 +0000)]
[asan] refactor instrumentation to allow merging the crash callbacks (not fully implemented yet, no functionality change except the BB order)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160284 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTarget/AMDGPU: Fix includes, or msvc build failed.
NAKAMURA Takumi [Mon, 16 Jul 2012 15:43:50 +0000 (15:43 +0000)]
Target/AMDGPU: Fix includes, or msvc build failed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160280 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTarget/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function...
NAKAMURA Takumi [Mon, 16 Jul 2012 15:43:09 +0000 (15:43 +0000)]
Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160279 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTarget/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator...
NAKAMURA Takumi [Mon, 16 Jul 2012 15:42:35 +0000 (15:42 +0000)]
Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160278 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoDoubleword Shift Left Logical Plus 32
Jack Carter [Mon, 16 Jul 2012 15:14:51 +0000 (15:14 +0000)]
Doubleword Shift Left Logical Plus 32

Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTarget/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen.
NAKAMURA Takumi [Mon, 16 Jul 2012 15:09:11 +0000 (15:09 +0000)]
Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTarget/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and...
NAKAMURA Takumi [Mon, 16 Jul 2012 15:08:47 +0000 (15:08 +0000)]
Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix tests that failed on i686-win32 after r160248:
Alexey Samsonov [Mon, 16 Jul 2012 14:33:36 +0000 (14:33 +0000)]
Fix tests that failed on i686-win32 after r160248:
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp.
2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of
vector add.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160274 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agotest/CodeGen/R600: Add some basic tests v6
Tom Stellard [Mon, 16 Jul 2012 14:17:19 +0000 (14:17 +0000)]
test/CodeGen/R600: Add some basic tests v6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoBuild script changes for R600/SI Codegen v6
Tom Stellard [Mon, 16 Jul 2012 14:17:16 +0000 (14:17 +0000)]
Build script changes for R600/SI Codegen v6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoinclude/llvm: Add R600 Intrinsics v6
Tom Stellard [Mon, 16 Jul 2012 14:17:14 +0000 (14:17 +0000)]
include/llvm: Add R600 Intrinsics v6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160271 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAMDGPU: Add core backend files for R600/SI codegen v6
Tom Stellard [Mon, 16 Jul 2012 14:17:08 +0000 (14:17 +0000)]
AMDGPU: Add core backend files for R600/SI codegen v6

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8

10 years ago[asan] initialize asan error callbacks in runOnModule instead of doing that on-demand
Kostya Serebryany [Mon, 16 Jul 2012 14:09:42 +0000 (14:09 +0000)]
[asan] initialize asan error callbacks in runOnModule instead of doing that on-demand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoFix a bug in the 3-address conversion of LEA when one of the operands is an
Nadav Rotem [Mon, 16 Jul 2012 10:52:25 +0000 (10:52 +0000)]
Fix a bug in the 3-address conversion of LEA when one of the operands is an
undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoRevert r160254 temporarily.
Chandler Carruth [Mon, 16 Jul 2012 10:01:02 +0000 (10:01 +0000)]
Revert r160254 temporarily.

It turns out that ASan relied on the at-the-end block insertion order to
(purely by happenstance) disable some LLVM optimizations, which in turn
start firing when the ordering is made more "normal". These
optimizations in turn merge many of the instrumentation reporting calls
which breaks the return address based error reporting in ASan.

We're looking at several different options for fixing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160256 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoTeach AddressSanitizer to create basic blocks in a more natural order.
Chandler Carruth [Mon, 16 Jul 2012 08:58:53 +0000 (08:58 +0000)]
Teach AddressSanitizer to create basic blocks in a more natural order.
This is particularly useful to the backend code generators which try to
process things in the incoming function order.

Also, cleanup some uses of IRBuilder to be a bit simpler and more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160254 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a basic test for AddressSanitizer. This is just a bare-bones
Chandler Carruth [Mon, 16 Jul 2012 08:56:46 +0000 (08:56 +0000)]
Add a basic test for AddressSanitizer. This is just a bare-bones
functionality test.

In general, unless the functionality is substantially separated, we
should lump more basic testing into this file. The test running
infrastructure likes having a few test files with more comprehensive
testing within them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160253 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd support for attaching branch weight metadata directly from the IRBuilder.
Chandler Carruth [Mon, 16 Jul 2012 07:45:06 +0000 (07:45 +0000)]
Add support for attaching branch weight metadata directly from the IRBuilder.

Added a basic unit test for this with CreateCondBr. I didn't go all the
way and test the switch side as the boilerplate for setting up the
switch IRBuilder unit tests is a lot more. Fortunately, the two share
all the interesting code paths.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160251 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoAdd a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.
Chandler Carruth [Mon, 16 Jul 2012 07:44:51 +0000 (07:44 +0000)]
Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.

This is in anticipation of changing CreateCondBr and wanting to test
those changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160250 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove the IRBuilder unittest from Support to VMCore. This got missed in
Chandler Carruth [Mon, 16 Jul 2012 07:44:45 +0000 (07:44 +0000)]
Move the IRBuilder unittest from Support to VMCore. This got missed in
the original move of IRBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160249 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoThis CL changes the function prologue and epilogue emitted on X86 when stack needs...
Alexey Samsonov [Mon, 16 Jul 2012 06:54:09 +0000 (06:54 +0000)]
This CL changes the function prologue and epilogue emitted on X86 when stack needs realignment.
It is intended to fix PR11468.

Old prologue and epilogue looked like this:
push %rbp
mov %rsp, %rbp
and $alignment, %rsp
push %r14
push %r15
...
pop %r15
pop %r14
mov %rbp, %rsp
pop %rbp

The problem was to reference the locations of callee-saved registers in exception handling:
locations of callee-saved had to be re-calculated regarding the stack alignment operation. It would
take some effort to implement this in LLVM, as currently MachineLocation can only have the form
"Register + Offset". Funciton prologue and epilogue are now changed to:

push %rbp
mov %rsp, %rbp
push %14
push %15
and $alignment, %rsp
...
lea -$size_of_saved_registers(%rbp), %rsp
pop %r15
pop %r14
pop %rbp

Reviewed by Chad Rosier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160248 91177308-0d34-0410-b5e6-96231b3b80d8

10 years agoMove llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completes
Chandler Carruth [Sun, 15 Jul 2012 23:45:24 +0000 (23:45 +0000)]
Move llvm/Support/TypeBuilder.h -> llvm/TypeBuilder.h. This completes
the move of *Builder classes into the Core library.

No uses of this builder in Clang or DragonEgg I could find.

If there is a desire to have an IR-building-support library that
contains all of these builders, that can be easily added, but currently
it seems likely that these add no real overhead to VMCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160243 91177308-0d34-0410-b5e6-96231b3b80d8