Tolerate a null parent pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116533 91177308-0d34-0410-b5e6-96231b3b80d8

Added basic support for CPack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116516 91177308-0d34-0410-b5e6-96231b3b80d8

Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
pseudonym.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116512 91177308-0d34-0410-b5e6-96231b3b80d8

Always use binary mode for output stream. This is important to prevent unwanted end of line conversion on Windows. Should not affect Unix where O_BINARY is not defined. This fix /clang/test/lexer/preamble.c XFAIL on WIN32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116509 91177308-0d34-0410-b5e6-96231b3b80d8

MOVi16 and MOVT ARM mode encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8

Only split around a loop if the live range has uses outside the loop periphery.

Before we would also split around a loop if any peripheral block had multiple
uses. This could cause repeated splitting when splitting a different live range
would insert uses into the periphery.

Now -spiller=inline passes the nightly test suite again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116494 91177308-0d34-0410-b5e6-96231b3b80d8

Try again at implementing thread-safe lazy pass initialization, without depending on static local initialization
being threadsafe AND ensuring that initialization is complete by the time the initializeFooPass method returns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116492 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r116489.  It included some changes I didn't intend to commit, and broke the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116491 91177308-0d34-0410-b5e6-96231b3b80d8

Apparently MSVC doesn't support thread-safe static local initialization.  Roll our own solution instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116489 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify encoding information and add 'dst' operand info for TAILJMP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116488 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some code duplication.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116484 91177308-0d34-0410-b5e6-96231b3b80d8

Remove explicit dependency of LLVMARMCodeGen on LLVMARMAsmPrinter. It
creates a cyclic dependency that breaks the build when
BUILD_SHARED_LIBS=ON

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116480 91177308-0d34-0410-b5e6-96231b3b80d8

When building shared libraries, link to required system libraries.

PR 8375

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116479 91177308-0d34-0410-b5e6-96231b3b80d8

Comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116476 91177308-0d34-0410-b5e6-96231b3b80d8

Forward -march correctly.

Also includes some cosmetic changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116475 91177308-0d34-0410-b5e6-96231b3b80d8

Handle more complex GEP based loads and add a few TODOs to deal with
GEP + alloca.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116474 91177308-0d34-0410-b5e6-96231b3b80d8

Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8

Add encoding for 'fmstat'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8

Register pressure and instruction latency aware machine LICM. Work in progress.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116465 91177308-0d34-0410-b5e6-96231b3b80d8

- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8

fix a bug I introduced, no idea how this didn't repro right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116462 91177308-0d34-0410-b5e6-96231b3b80d8

hack to unbreak buildbots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116461 91177308-0d34-0410-b5e6-96231b3b80d8

Regenerate. No functional change, just cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116459 91177308-0d34-0410-b5e6-96231b3b80d8

Teach PerfectShuffle to not generate files with embedded tab characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116458 91177308-0d34-0410-b5e6-96231b3b80d8

add uadd_ov/usub_ov to apint, consolidate constant folding
logic to use the new APInt methods.  Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold

which comes from "clang -ftrapv", originally brought to my attention from PR8221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116457 91177308-0d34-0410-b5e6-96231b3b80d8

missed a line :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116456 91177308-0d34-0410-b5e6-96231b3b80d8

constify these methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116455 91177308-0d34-0410-b5e6-96231b3b80d8

Detabify and clean up 80 column violations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116454 91177308-0d34-0410-b5e6-96231b3b80d8

add a few operations for signed operations that also
return an overflow flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116452 91177308-0d34-0410-b5e6-96231b3b80d8

A few 80 column fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116451 91177308-0d34-0410-b5e6-96231b3b80d8

trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116450 91177308-0d34-0410-b5e6-96231b3b80d8

Add a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116449 91177308-0d34-0410-b5e6-96231b3b80d8

Add operand encoding bits for SMC and SVC in ARM mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116447 91177308-0d34-0410-b5e6-96231b3b80d8

More encoding cleanup. Also add register Rd operands for indirect branches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116444 91177308-0d34-0410-b5e6-96231b3b80d8

CallGraphSCC passes implicity require CallGraph analysis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116443 91177308-0d34-0410-b5e6-96231b3b80d8

Conversely, Analysis-implementations do NOT need to initialize the AnalysisGroup.  It will only matter when
someone tries to require that AG, in which case it is the requester's responsibility to initialize it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116442 91177308-0d34-0410-b5e6-96231b3b80d8

Analysis groups need to initialize their default implementations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116441 91177308-0d34-0410-b5e6-96231b3b80d8

Simplify some ARM encoding information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116440 91177308-0d34-0410-b5e6-96231b3b80d8

Update comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116438 91177308-0d34-0410-b5e6-96231b3b80d8

Add a FIXME. The ADR instruction is a bit odd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116437 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8

Add MC encodings for VCVT* instrunctions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8

Add a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116428 91177308-0d34-0410-b5e6-96231b3b80d8

Make a few more bits of some simple instructions explicit. nop, yield, wfe,
wfi, sel, sev and bkpt. All would disassemble properly before, but more
explicitness is good, especially with the integrated assembler coming in
the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116427 91177308-0d34-0410-b5e6-96231b3b80d8

Take advantage of C++'s thread-safe static local initialization to simplify thread-safe pass initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116426 91177308-0d34-0410-b5e6-96231b3b80d8

GetTargetTriple.cmake: detect MinGW 64 bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116424 91177308-0d34-0410-b5e6-96231b3b80d8

Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8

Fix encoding for compares. No Rd register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8

Add ARM mode operand encoding information for ADDE/SUBE instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8

Fix another case where we were preferring instructions with large
immediates instead of 8 bits ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116410 91177308-0d34-0410-b5e6-96231b3b80d8

Remove noisy semicolon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116407 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
8 bit constants can be used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116403 91177308-0d34-0410-b5e6-96231b3b80d8

Add Region::isTopLevelRegion().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116402 91177308-0d34-0410-b5e6-96231b3b80d8

Start handling more global variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116401 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Fix trivial error that slipped in last minute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116400 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Update RegionInfo after a BB was split.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116398 91177308-0d34-0410-b5e6-96231b3b80d8

RegioInfo: Add getExpandedRegion().

getExpandedRegion() enables us to create non canonical regions. Those regions
can be used to define the largerst region, that fullfills a certain property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116397 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Allow to update exit and entry of a region.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116396 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Enhance addSubregion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116395 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Allow to set the parent region of a basic block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116394 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR8313 by changing ValueToValueMap use a TrackingVH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116390 91177308-0d34-0410-b5e6-96231b3b80d8

Limit load / store issues (at least until we have a true multi-issue aware scheduler).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116389 91177308-0d34-0410-b5e6-96231b3b80d8

Be more consistent in using ValueToValueMapTy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116387 91177308-0d34-0410-b5e6-96231b3b80d8

Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8

Add encodings for VCVT instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8

Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8

Add VCMPZ and VABS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8

RegionInfo: Free the RegionNodes in cache.

Contributed by: ether

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116380 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor VCMP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8

Add the rest of the ARM so_reg encoding options (register shifted register)
and move to a custom operand encoder. Remove the last of the special handling
stuff from ARMMCCodeEmitter::EncodeInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116377 91177308-0d34-0410-b5e6-96231b3b80d8

FileCheckize this in a hope to quiet a valgrind warning on grep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116376 91177308-0d34-0410-b5e6-96231b3b80d8

Add encodings for VNMUL[SD].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8

Add encodings for VDIV and VMUL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8

Turn some fp stackifier assertion into errors to avoid silently generating bad code when assertions are off. rdar://8540457.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116368 91177308-0d34-0410-b5e6-96231b3b80d8

Move the ARM so_imm encoding into a custom operand encoder and remove the
explicit handling of the instructions referencing it from the MC code
emitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116367 91177308-0d34-0410-b5e6-96231b3b80d8

Be nitpicky and line up the comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8

Refactor some of the encoding logic into a base class. This keeps us from having
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116362 91177308-0d34-0410-b5e6-96231b3b80d8

Add custom encoder for the 's' bit denoting whether an ARM arithmetic
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8

Add encoding for VSUB and VCMP.

Fear not! I'm going to try a refactoring right now. :)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8

Don't need to specify calling convention. Add 'readnone' to functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8

Allow targets to optionally specify custom binary encoder functions for
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8

Encoding for VADDD. Plus a test for the VFP instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8

Split out the "size" field from the encoding. The newer documentation has it as
a separate bit in the coding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116347 91177308-0d34-0410-b5e6-96231b3b80d8

Fix thinko in arm fast isel alloca rewrite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116339 91177308-0d34-0410-b5e6-96231b3b80d8

Encoding for ARM-mode VADD.F32 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116338 91177308-0d34-0410-b5e6-96231b3b80d8

Begin adding static dependence information to passes, which will allow us to
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116334 91177308-0d34-0410-b5e6-96231b3b80d8

Combine these together - should probably have some text associated
that says what why what we just asserted is wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116333 91177308-0d34-0410-b5e6-96231b3b80d8

KillTheDoctor: Fix VS2008 build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116330 91177308-0d34-0410-b5e6-96231b3b80d8

Mark variable 'NoImplicitFloatOps' used only in an assert as used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116323 91177308-0d34-0410-b5e6-96231b3b80d8

Comment grammar tweakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116322 91177308-0d34-0410-b5e6-96231b3b80d8

Add MOVi ARM encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8

Initial va_arg support for x86-64. Patch by David Meyer!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116319 91177308-0d34-0410-b5e6-96231b3b80d8

Nuke unused wrapper function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8

Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.

The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8

Add encoding information for the remainder of the generic arithmetic
ARM instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8

PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8

Rework alloca handling so that we can load or store from casted
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116296 91177308-0d34-0410-b5e6-96231b3b80d8

Fix the last two commits to configure - configure is a generated file.
Made necessary edits to configure.ac and regenerated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116291 91177308-0d34-0410-b5e6-96231b3b80d8

Handle a wider arrangement of loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116284 91177308-0d34-0410-b5e6-96231b3b80d8

Fix spelling error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116282 91177308-0d34-0410-b5e6-96231b3b80d8