oota-llvm.git
8 years ago[X86] Optimize stackmap shadows on X86.
Lang Hames [Thu, 24 Jul 2014 20:40:55 +0000 (20:40 +0000)]
[X86] Optimize stackmap shadows on X86.

This patch minimizes the number of nops that must be emitted on X86 to satisfy
stackmap shadow constraints.

To minimize the number of nops inserted, the X86AsmPrinter now records the
size of the most recent stackmap's shadow in the StackMapShadowTracker class,
and tracks the number of instruction bytes emitted since the that stackmap
instruction was encountered. Padding is emitted (if it is required at all)
immediately before the next stackmap/patchpoint instruction, or at the end of
the basic block.

This optimization should reduce code-size and improve performance for people
using the llvm stackmap intrinsic on X86.

<rdar://problem/14959522>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213892 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReplace an assertion with a fatal error
Reid Kleckner [Thu, 24 Jul 2014 19:53:33 +0000 (19:53 +0000)]
Replace an assertion with a fatal error

Frontends are responsible for putting inalloca on parameters that would
be passed in memory and not registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213891 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse the same .eh_frame encoding for 32bit PPC as on i386.
Joerg Sonnenberger [Thu, 24 Jul 2014 19:25:16 +0000 (19:25 +0000)]
Use the same .eh_frame encoding for 32bit PPC as on i386.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213890 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTry to fix the bots again by moving test to X86 directory.
Manman Ren [Thu, 24 Jul 2014 17:57:09 +0000 (17:57 +0000)]
Try to fix the bots again by moving test to X86 directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213884 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: correct library call setup for Windows itanium
Saleem Abdulrasool [Thu, 24 Jul 2014 17:46:36 +0000 (17:46 +0000)]
X86: correct library call setup for Windows itanium

This target is identical to the Windows MSVC (and follows Microsoft ABI for C).
Correct the library call setup for this target.  The same set of library calls
are missing on this environment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213883 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Add FMA instructions for Evergreen
Matt Arsenault [Thu, 24 Jul 2014 17:41:01 +0000 (17:41 +0000)]
R600: Add FMA instructions for Evergreen

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213882 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTry to fix the bots. If this does not work, I am going to move it to X86 directory.
Manman Ren [Thu, 24 Jul 2014 17:18:33 +0000 (17:18 +0000)]
Try to fix the bots. If this does not work, I am going to move it to X86 directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213880 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: silence sign comparison warning
Saleem Abdulrasool [Thu, 24 Jul 2014 17:12:06 +0000 (17:12 +0000)]
X86: silence sign comparison warning

GCC 4.8 detected a signed compare [-Wsign-compare].  Add a cast for the
destination index.  Add an assert to catch a potential overflow however unlikely
it may be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213878 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Add new functions for splitting vector loads and stores.
Matt Arsenault [Thu, 24 Jul 2014 17:10:35 +0000 (17:10 +0000)]
R600: Add new functions for splitting vector loads and stores.

These will be used in future patches and shouldn't change anything yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213877 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLet the integrated assembler understand .exitm, PR20426.
Nico Weber [Thu, 24 Jul 2014 17:08:39 +0000 (17:08 +0000)]
Let the integrated assembler understand .exitm, PR20426.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213876 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove unused field MacroInstantiation::TheMacro. No behavior change.
Nico Weber [Thu, 24 Jul 2014 16:29:04 +0000 (16:29 +0000)]
Remove unused field MacroInstantiation::TheMacro. No behavior change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213874 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLet the integrated assembler understand .warning, PR20428.
Nico Weber [Thu, 24 Jul 2014 16:26:06 +0000 (16:26 +0000)]
Let the integrated assembler understand .warning, PR20428.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213873 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInclude relative path for header outside the current directory.
Joerg Sonnenberger [Thu, 24 Jul 2014 16:04:46 +0000 (16:04 +0000)]
Include relative path for header outside the current directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213872 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove dead code.
Rafael Espindola [Thu, 24 Jul 2014 16:02:28 +0000 (16:02 +0000)]
Remove dead code.

Every user has been switched to using EngineBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213871 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAArch64: refactor ReconstructShuffle function
Tim Northover [Thu, 24 Jul 2014 15:39:55 +0000 (15:39 +0000)]
AArch64: refactor ReconstructShuffle function

Quite a bit of cruft had accumulated as we realised the various different cases
it had to handle and squeezed them in where possible. This refactoring mostly
flattens the logic and special-cases. The result is slightly longer, but I
think clearer.

Should be no functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213867 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix r213824 on windows
Duncan P. N. Exon Smith [Thu, 24 Jul 2014 15:16:23 +0000 (15:16 +0000)]
Fix r213824 on windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213866 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd scoped-noalias metadata
Hal Finkel [Thu, 24 Jul 2014 14:25:39 +0000 (14:25 +0000)]
Add scoped-noalias metadata

This commit adds scoped noalias metadata. The primary motivations for this
feature are:
  1. To preserve noalias function attribute information when inlining
  2. To provide the ability to model block-scope C99 restrict pointers

Neither of these two abilities are added here, only the necessary
infrastructure. In fact, there should be no change to existing functionality,
only the addition of new features. The logic that converts noalias function
parameters into this metadata during inlining will come in a follow-up commit.

What is added here is the ability to generally specify noalias memory-access
sets. Regarding the metadata, alias-analysis scopes are defined similar to TBAA
nodes:

!scope0 = metadata !{ metadata !"scope of foo()" }
!scope1 = metadata !{ metadata !"scope 1", metadata !scope0 }
!scope2 = metadata !{ metadata !"scope 2", metadata !scope0 }
!scope3 = metadata !{ metadata !"scope 2.1", metadata !scope2 }
!scope4 = metadata !{ metadata !"scope 2.2", metadata !scope2 }

Loads and stores can be tagged with an alias-analysis scope, and also, with a
noalias tag for a specific scope:

... = load %ptr1, !alias.scope !{ !scope1 }
... = load %ptr2, !alias.scope !{ !scope1, !scope2 }, !noalias !{ !scope1 }

When evaluating an aliasing query, if one of the instructions is associated
with an alias.scope id that is identical to the noalias scope associated with
the other instruction, or is a descendant (in the scope hierarchy) of the
noalias scope associated with the other instruction, then the two memory
accesses are assumed not to alias.

Note that is the first element of the scope metadata is a string, then it can
be combined accross functions and translation units. The string can be replaced
by a self-reference to create globally unqiue scope identifiers.

[Note: This overview is slightly stylized, since the metadata nodes really need
to just be numbers (!0 instead of !scope0), and the scope lists are also global
unnamed metadata.]

Existing noalias metadata in a callee is "cloned" for use by the inlined code.
This is necessary because the aliasing scopes are unique to each call site
(because of possible control dependencies on the aliasing properties). For
example, consider a function: foo(noalias a, noalias b) { *a = *b; } that gets
inlined into bar() { ... if (...) foo(a1, b1); ... if (...) foo(a2, b2); } --
now just because we know that a1 does not alias with b1 at the first call site,
and a2 does not alias with b2 at the second call site, we cannot let inlining
these functons have the metadata imply that a1 does not alias with b2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213864 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFixing an MSVC conversion warning about implicitly converting the shift results to...
Aaron Ballman [Thu, 24 Jul 2014 14:24:59 +0000 (14:24 +0000)]
Fixing an MSVC conversion warning about implicitly converting the shift results to 64-bits. No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213863 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Target] Teach the query interfaces for lowering of extloads and
Chandler Carruth [Thu, 24 Jul 2014 12:20:53 +0000 (12:20 +0000)]
[Target] Teach the query interfaces for lowering of extloads and
truncstores to support EVTs and return expand for non-simple ones.

This makes them more consistent with the isLegal... query style methods
and makes using them simpler in many scenarios.

No functionality actually changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213860 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAA metadata refactoring (introduce AAMDNodes)
Hal Finkel [Thu, 24 Jul 2014 12:16:19 +0000 (12:16 +0000)]
AA metadata refactoring (introduce AAMDNodes)

In order to enable the preservation of noalias function parameter information
after inlining, and the representation of block-level __restrict__ pointer
information (etc.), additional kinds of aliasing metadata will be introduced.
This metadata needs to be carried around in AliasAnalysis::Location objects
(and MMOs at the SDAG level), and so we need to generalize the current scheme
(which is hard-coded to just one TBAA MDNode*).

This commit introduces only the necessary refactoring to allow for the
introduction of other aliasing metadata types, but does not actually introduce
any (that will come in a follow-up commit). What it does introduce is a new
AAMDNodes structure to hold all of the aliasing metadata nodes associated with
a particular memory-accessing instruction, and uses that structure instead of
the raw MDNode* in AliasAnalysis::Location, etc.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213859 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPrune redundant libdeps.
NAKAMURA Takumi [Thu, 24 Jul 2014 11:45:27 +0000 (11:45 +0000)]
Prune redundant libdeps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213857 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPrune dependency to MC from each target disassembler.
NAKAMURA Takumi [Thu, 24 Jul 2014 11:45:11 +0000 (11:45 +0000)]
Prune dependency to MC from each target disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213856 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[CMake] tools/lto: Prune redundant libdep(s).
NAKAMURA Takumi [Thu, 24 Jul 2014 11:44:44 +0000 (11:44 +0000)]
[CMake] tools/lto: Prune redundant libdep(s).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213855 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[CMake] LineEditorTests: Add Support to link_components.
NAKAMURA Takumi [Thu, 24 Jul 2014 11:44:33 +0000 (11:44 +0000)]
[CMake] LineEditorTests: Add Support to link_components.

Even if LLVMSupport is added in add_unittests, LLVMSupport may be here as consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213854 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.
Tilmann Scheller [Thu, 24 Jul 2014 09:55:46 +0000 (09:55 +0000)]
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRH instructions.

The ARM ARM prohibits STRH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRH instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213850 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Fix ll and sc instructions
Daniel Sanders [Thu, 24 Jul 2014 09:47:14 +0000 (09:47 +0000)]
[mips] Fix ll and sc instructions

Summary: The ll and sc instructions for r6 and non-r6 are misplaced. This patch fixes that.

Patch by Jyun-Yan You

Differential Revision: http://reviews.llvm.org/D4578

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213847 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Match rcp node on pre-SI
Matt Arsenault [Thu, 24 Jul 2014 06:59:24 +0000 (06:59 +0000)]
R600: Match rcp node on pre-SI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213844 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Fix LowerSDIV24
Matt Arsenault [Thu, 24 Jul 2014 06:59:20 +0000 (06:59 +0000)]
R600: Fix LowerSDIV24

Use ComputeNumSignBits instead of checking for i8 / i16 which only
worked when AMDIL was lying about having legal i8 / i16.

If an integer is known to fit in 24-bits, we can
do division faster with float ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213843 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove unused substitution.
Rafael Espindola [Thu, 24 Jul 2014 04:09:04 +0000 (04:09 +0000)]
Remove unused substitution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213839 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Fix comment from r213824
Duncan P. N. Exon Smith [Thu, 24 Jul 2014 02:56:59 +0000 (02:56 +0000)]
IR: Fix comment from r213824

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213836 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove a stray semicolon. [-Wpedantic]
NAKAMURA Takumi [Thu, 24 Jul 2014 02:11:24 +0000 (02:11 +0000)]
Remove a stray semicolon. [-Wpedantic]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213833 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate library dependencies.
NAKAMURA Takumi [Thu, 24 Jul 2014 02:10:42 +0000 (02:10 +0000)]
Update library dependencies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213832 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Implement enableClusterLoads()
Matt Arsenault [Thu, 24 Jul 2014 02:10:17 +0000 (02:10 +0000)]
R600: Implement enableClusterLoads()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213831 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Fix a bug generating incorrect instruction when building small vector.
Kevin Qin [Thu, 24 Jul 2014 02:05:42 +0000 (02:05 +0000)]
[AArch64] Fix a bug generating incorrect instruction when building small vector.

This bug is introduced by r211144. The element of operand may be
smaller than the element of result, but previous commit can
only handle the contrary condition. This commit is to handle this
scenario and generate optimized codes like ZIP1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213830 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Disable some optimization cases for type conversion from sint to fp, becaus...
Jiangning Liu [Thu, 24 Jul 2014 01:29:59 +0000 (01:29 +0000)]
[AArch64] Disable some optimization cases for type conversion from sint to fp, because those optimization cases are micro-architecture dependent and only make sense for Cyclone. A new predicate Cyclone is introduced in .td file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213827 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFixed PR20411 - bug in getINSERTPS()
Filipe Cabecinhas [Thu, 24 Jul 2014 01:28:21 +0000 (01:28 +0000)]
Fixed PR20411 - bug in getINSERTPS()

When we had a vector_shuffle where we had an input from each vector, we
could miscompile it because we were assuming the input from V2 wouldn't
be moved from where it was on the vector.

Added a test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213826 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Add Value::sortUseList()
Duncan P. N. Exon Smith [Thu, 24 Jul 2014 00:53:19 +0000 (00:53 +0000)]
IR: Add Value::sortUseList()

Add `Value::sortUseList()`, templated on the comparison function to use.

The sort is an iterative merge sort that uses a binomial vector of
already-merged lists to limit the size overhead to `O(1)`.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213824 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a VS "14" msbuild toolset
Reid Kleckner [Wed, 23 Jul 2014 23:49:16 +0000 (23:49 +0000)]
Add a VS "14" msbuild toolset

This allows people to try clang inside MSBuild with the VS "14" CTP
releases.

Fixes PR20341.

Patch by Marcel Raad!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213819 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSimplifyCFG: fix a bug in switch to table conversion
Manman Ren [Wed, 23 Jul 2014 23:13:23 +0000 (23:13 +0000)]
SimplifyCFG: fix a bug in switch to table conversion

We use gep to access the global array "switch.table", and the table index
should be treated as unsigned. When the highest bit is 1, this commit
zero-extends the index to an integer type with larger size.

For a switch on i2, we used to generate:
%switch.tableidx = sub i2 %0, -2
getelementptr inbounds [4 x i64]* @switch.table, i32 0, i2 %switch.tableidx

It is incorrect when %switch.tableidx is 2 or 3. The fix is to generate
%switch.tableidx = sub i2 %0, -2
%switch.tableidx.zext = zext i2 %switch.tableidx to i3
getelementptr inbounds [4 x i64]* @switch.table, i32 0, i3 %switch.tableidx.zext

rdar://17735071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213815 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix the build when building with only the ARM backend.
Rafael Espindola [Wed, 23 Jul 2014 22:54:28 +0000 (22:54 +0000)]
Fix the build when building with only the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213814 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDocument what backwards compatibility we provide for bitcode.
Rafael Espindola [Wed, 23 Jul 2014 22:43:22 +0000 (22:43 +0000)]
Document what backwards compatibility we provide for bitcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213813 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLet llvm/test/CodeGen/X86/avx512*-mask-op.ll(s) aware of Win32 x64 calling convention.
NAKAMURA Takumi [Wed, 23 Jul 2014 22:38:25 +0000 (22:38 +0000)]
Let llvm/test/CodeGen/X86/avx512*-mask-op.ll(s) aware of Win32 x64 calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213812 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix indenting.
Eric Christopher [Wed, 23 Jul 2014 22:34:13 +0000 (22:34 +0000)]
Fix indenting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213811 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Rip out some broken test cases for avx512 i1 store support.
Chandler Carruth [Wed, 23 Jul 2014 22:29:19 +0000 (22:29 +0000)]
[x86] Rip out some broken test cases for avx512 i1 store support.

It isn't reasonable to test storing things using undef pointers --
storing through those is at best "good luck" and really should be
transformed to "unreachable". Random changes in the combiner can
randomly break these tests for no good reason. I'm following up on the
original commit regarding the right long-term strategy here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213810 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReorganize and simplify local variables.
Eric Christopher [Wed, 23 Jul 2014 22:27:10 +0000 (22:27 +0000)]
Reorganize and simplify local variables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213809 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFinish inverting the MC -> Object dependency.
Rafael Espindola [Wed, 23 Jul 2014 22:26:07 +0000 (22:26 +0000)]
Finish inverting the MC -> Object dependency.

There were still some disassembler bits in lib/MC, but their use of Object
was only visible in the includes they used, not in the symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213808 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld][AArch64] Update relocation tests and also add a simple GOT test.
Juergen Ributzka [Wed, 23 Jul 2014 22:23:17 +0000 (22:23 +0000)]
[RuntimeDyld][AArch64] Update relocation tests and also add a simple GOT test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213807 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove the query for TargetMachine and TargetInstrInfo since we're
Eric Christopher [Wed, 23 Jul 2014 22:12:03 +0000 (22:12 +0000)]
Remove the query for TargetMachine and TargetInstrInfo since we're
already inside TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213806 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoArgPromo+DebugInfo: Handle updating debug info over multiple applications of argument...
David Blaikie [Wed, 23 Jul 2014 22:09:29 +0000 (22:09 +0000)]
ArgPromo+DebugInfo: Handle updating debug info over multiple applications of argument promotion.

While the subprogram map cache used by Dead Argument Elimination works
there, I made a mistake when reusing it for Argument Promotion in
r212128 because ArgPromo may transform functions more than once whereas
DAE transforms each function only once, removing all the dead arguments
in one go.

To address this, ensure that the map is updated after each argument
promotion.

In retrospect it might be a little wasteful to create a map of all
subprograms when only handling a single CGSCC, but the alternative is
walking the debug info for each function in the CGSCC that gets updated.
It's not clear to me what the right tradeoff is there, but since the
current tradeoff seems to be working OK (and the code to keep things
updated is very cheap), let's stick with that for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213805 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTest debug info in arg promotion with an actual promotion case, rather than a degener...
David Blaikie [Wed, 23 Jul 2014 21:30:59 +0000 (21:30 +0000)]
Test debug info in arg promotion with an actual promotion case, rather than a degenerate arg promotion that's actually DAE performed by ArgPromo

Also the debug location I had here was bogus, describing the location of
the call site as in the callee - and unnecessary, so just drop it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213803 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse an explicit triple in testcase.
Jim Grosbach [Wed, 23 Jul 2014 20:46:32 +0000 (20:46 +0000)]
Use an explicit triple in testcase.

Make the test work better on non-darwin hosts. Hopefully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213801 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86,AArch64] Extend vcmp w/ unary op combine to work w/ more constants.
Jim Grosbach [Wed, 23 Jul 2014 20:41:43 +0000 (20:41 +0000)]
[X86,AArch64] Extend vcmp w/ unary op combine to work w/ more constants.

The transform to constant fold unary operations with an AND across a
vector comparison applies when the constant is not a splat of a scalar
as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213800 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: restrict combine to when type sizes are safe.
Jim Grosbach [Wed, 23 Jul 2014 20:41:38 +0000 (20:41 +0000)]
X86: restrict combine to when type sizes are safe.

The folding of unary operations through a vector compare and mask operation
is only safe if the unary operation result is of the same size as its input.
For example, it's not safe for [su]itofp from v4i32 to v4f64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213799 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDAG: fp->int conversion for non-splat constants.
Jim Grosbach [Wed, 23 Jul 2014 20:41:31 +0000 (20:41 +0000)]
DAG: fp->int conversion for non-splat constants.

Constant fold the lanes of the input constant build_vector individually
so we correctly handle when the vector elements are not all the same
constant value.

PR20394

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213798 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types
Justin Holewinski [Wed, 23 Jul 2014 20:23:49 +0000 (20:23 +0000)]
[NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213794 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[NVPTX] Silence a GCC warning found by the buildbots
Justin Holewinski [Wed, 23 Jul 2014 20:23:47 +0000 (20:23 +0000)]
[NVPTX] Silence a GCC warning found by the buildbots

The cast to NVPTXTargetLowering was missing a 'const', but let's
just access the right pointer through the subtarget anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213793 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDo not add unroll disable metadata after unrolling pass for loops with #pragma clang...
Mark Heffernan [Wed, 23 Jul 2014 20:05:44 +0000 (20:05 +0000)]
Do not add unroll disable metadata after unrolling pass for loops with #pragma clang loop unroll(full).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213789 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Fix return type in FastLowerCall.
Juergen Ributzka [Wed, 23 Jul 2014 20:03:13 +0000 (20:03 +0000)]
[FastISel][AArch64] Fix return type in FastLowerCall.

I used the wrong method to obtain the return type inside FinishCall. This fix
simply uses the return type from FastLowerCall, which we already determined to
be a valid type.

Reduced test case from Chad. Thanks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213788 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[NVPTX] mul.wide generation works for any smaller integer source types, not just...
Justin Holewinski [Wed, 23 Jul 2014 18:46:03 +0000 (18:46 +0000)]
[NVPTX] mul.wide generation works for any smaller integer source types, not just the next smaller power of two

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213784 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SKX] Added missed test files for rev 213757
Robert Khasanov [Wed, 23 Jul 2014 18:17:49 +0000 (18:17 +0000)]
[SKX] Added missed test files for rev 213757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213780 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAsmParser: remove deprecated LLIR support
Saleem Abdulrasool [Wed, 23 Jul 2014 18:09:31 +0000 (18:09 +0000)]
AsmParser: remove deprecated LLIR support

linker_private and linker_private_weak were deprecated in 3.5.  Remove support
for them now that the 3.5 branch has been created.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213777 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoExecutionEngine: remove a stray semicolon
Saleem Abdulrasool [Wed, 23 Jul 2014 18:09:28 +0000 (18:09 +0000)]
ExecutionEngine: remove a stray semicolon

Detected via GCC 4.8 [-Wpedantic].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213776 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SKX] Fix lowercase "error:" in rev 213757
Robert Khasanov [Wed, 23 Jul 2014 17:42:13 +0000 (17:42 +0000)]
[SKX] Fix lowercase "error:" in rev 213757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213774 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled
Justin Holewinski [Wed, 23 Jul 2014 17:40:45 +0000 (17:40 +0000)]
[NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled

With optimizations disabled, we disable the isel patterns for mul.wide; but we
were still generating MULWIDE ISD nodes.  Now, we only try to generate MULWIDE
ISD nodes in DAGCombine if the optimization level is not zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213773 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIn unroll pragma syntax and loop hint metadata, change "enable" forms to a new form...
Mark Heffernan [Wed, 23 Jul 2014 17:31:37 +0000 (17:31 +0000)]
In unroll pragma syntax and loop hint metadata, change "enable" forms to a new form using the string "full".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213772 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agotest commit: remove trailing space
Alex Lorenz [Wed, 23 Jul 2014 17:18:05 +0000 (17:18 +0000)]
test commit: remove trailing space

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213770 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Lower sdiv x, pow2 using add + select + shift.
Chad Rosier [Wed, 23 Jul 2014 14:57:52 +0000 (14:57 +0000)]
[AArch64] Lower sdiv x, pow2 using add + select + shift.

The target-independent DAGcombiner will generate:
asr w1, X, #31 w1 = splat sign bit.
add X, X, w1, lsr #28 X = X + 0 or pow2-1
asr w0, X, asr #4 w0 = X/pow2

However, the add + shifts is expensive, so generate:
add w0, X, 15 w0 = X + pow2-1
cmp X, wzr X - 0
csel X, w0, X, lt X = (X < 0) ? X + pow2-1 : X;
asr w0, X, asr 4 w0 = X/pow2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213758 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SKX] Enabling mask instructions: encoding, lowering
Robert Khasanov [Wed, 23 Jul 2014 14:49:42 +0000 (14:49 +0000)]
[SKX] Enabling mask instructions: encoding, lowering
KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213757 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: spot SBFX-compatbile code expressed with sign_extend_inreg
Tim Northover [Wed, 23 Jul 2014 13:59:12 +0000 (13:59 +0000)]
ARM: spot SBFX-compatbile code expressed with sign_extend_inreg

We were assuming all SBFX-like operations would have the shl/asr form, but
often when the field being extracted is an i8 or i16, we end up with a
SIGN_EXTEND_INREG acting on a shift instead. Simple enough to check for though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213754 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: add patterns for [su]xta[bh] from just a shift.
Tim Northover [Wed, 23 Jul 2014 13:59:07 +0000 (13:59 +0000)]
ARM: add patterns for [su]xta[bh] from just a shift.

Although the final shifter operand is a rotate, this actually only matters for
the half-word extends when the amount == 24. Otherwise folding a shift in is
just as good.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213753 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoEnable partial libcall inlining for all targets by default.
James Molloy [Wed, 23 Jul 2014 13:33:00 +0000 (13:33 +0000)]
Enable partial libcall inlining for all targets by default.

This pass attempts to speculatively use a sqrt instruction if one exists on the target, falling back to a libcall if the target instruction returned NaN.

This was enabled for MIPS and System-Z, but is well guarded and is good for most targets - GCC does this for (that I've checked) X86, ARM and AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213752 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions.
Tilmann Scheller [Wed, 23 Jul 2014 13:03:47 +0000 (13:03 +0000)]
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STRB instructions.

The ARM ARM prohibits STRB instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STRB instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213750 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdded release notes for MIPS.
Daniel Sanders [Wed, 23 Jul 2014 12:59:26 +0000 (12:59 +0000)]
Added release notes for MIPS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213749 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAArch64: remove "arm64_be" support in favour of "aarch64_be".
Tim Northover [Wed, 23 Jul 2014 12:58:11 +0000 (12:58 +0000)]
AArch64: remove "arm64_be" support in favour of "aarch64_be".

There really is no arm64_be: it was a useful fiction to test big-endian support
while both backends existed in parallel, but now the only platform that uses
the name (iOS) doesn't have a big-endian variant, let alone one called
"arm64_be".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213748 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions.
Tilmann Scheller [Wed, 23 Jul 2014 12:38:17 +0000 (12:38 +0000)]
[ARM] Make the assembler reject unpredictable pre/post-indexed ARM STR instructions.

The ARM ARM prohibits STR instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling STR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213745 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAArch64: remove arm64 triple enumerator.
Tim Northover [Wed, 23 Jul 2014 12:32:47 +0000 (12:32 +0000)]
AArch64: remove arm64 triple enumerator.

Having both Triple::arm64 and Triple::aarch64 is extremely confusing, and
invites bugs where only one is checked. In reality, the only legitimate
difference between the two (arm64 usually means iOS) is also present in the OS
part of the triple and that's what should be checked.

We still parse the "arm64" triple, just canonicalise it to Triple::aarch64, so
there aren't any LLVM-side test changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213743 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r211771. It was: "[X86] Improve the selection of SSE3/AVX addsub instructions".
Andrea Di Biagio [Wed, 23 Jul 2014 11:20:24 +0000 (11:20 +0000)]
Revert r211771. It was: "[X86] Improve the selection of SSE3/AVX addsub instructions".

This chang fully reverts r211771.
That revision added a canonicalization rule which has the potential to causes a
combine-cycle in the target-independent canonicalizing DAG combine.

The plan is to move the logic that forms target specific addsub nodes as part of
the lowering of shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213736 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Clean up a test case to use check labels and spell out the exact
Chandler Carruth [Wed, 23 Jul 2014 09:11:48 +0000 (09:11 +0000)]
[x86] Clean up a test case to use check labels and spell out the exact
instruction sequences with CHECK-NEXT for these test cases.

This notably exposes how absolutely horrible the generated code is for
several of these test cases, and will make any future updates to the
test as our vector instruction selection gets better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213732 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Add regression test for the earlyclobber constraint of ARM STRB.
Tilmann Scheller [Wed, 23 Jul 2014 08:39:50 +0000 (08:39 +0000)]
[ARM] Add regression test for the earlyclobber constraint of ARM STRB.

The constraint was added in r213369.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213730 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions.
Tilmann Scheller [Wed, 23 Jul 2014 08:12:51 +0000 (08:12 +0000)]
[ARM] Add earlyclobber constraint to pre/post-indexed ARM STRH instructions.

The post-indexed instructions were missing the constraint, causing unpredictable STRH instructions to be emitted.

The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213729 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate
Chandler Carruth [Wed, 23 Jul 2014 07:08:53 +0000 (07:08 +0000)]
[SDAG] Make the DAGCombine worklist not grow endlessly due to duplicate
insertions.

The old behavior could cause arbitrarily bad memory usage in the DAG
combiner if there was heavy traffic of adding nodes already on the
worklist to it. This commit switches the DAG combine worklist to work
the same way as the instcombine worklist where we null-out removed
entries and only add new entries to the worklist. My measurements of
codegen time shows slight improvement. The memory utilization is
unsurprisingly dominated by other factors (the IR and DAG itself
I suspect).

This change results in subtle, frustrating churn in the particular order
in which DAG combines are applied which causes a number of minor
regressions where we fail to match a pattern previously matched by
accident. AFAICT, all of these should be using AddToWorklist to directly
or should be written in a less brittle way. None of the changes seem
drastically bad, and a few of the changes seem distinctly better.

A major change required to make this work is to significantly harden the
way in which the DAG combiner handle nodes which become dead
(zero-uses). Previously, we relied on the ability to "priority-bump"
them on the combine worklist to achieve recursive deletion of these
nodes and ensure that the frontier of remaining live nodes all were
added to the worklist. Instead, I've introduced a routine to just
implement that precise logic with no indirection. It is a significantly
simpler operation than that of the combiner worklist proper. I suspect
this will also fix some other problems with the combiner.

I think the x86 changes are really minor and uninteresting, but the
avx512 change at least is hiding a "regression" (despite the test case
being just noise, not testing some performance invariant) that might be
looked into. Not sure if any of the others impact specific "important"
code paths, but they didn't look terribly interesting to me, or the
changes were really minor. The consensus in review is to fix any
regressions that show up after the fact here.

Thanks to the other reviewers for checking the output on other
architectures. There is a specific regression on ARM that Tim already
has a fix prepped to commit.

Differential Revision: http://reviews.llvm.org/D4616

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213727 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoWe may visit a call that uses an alloca multiple times in callUsesLocalStack, sometim...
Nick Lewycky [Wed, 23 Jul 2014 06:24:49 +0000 (06:24 +0000)]
We may visit a call that uses an alloca multiple times in callUsesLocalStack, sometimes with IsNocapture true and sometimes with IsNocapture false. We accidentally skipped work we needed to do in the IsNocapture=false case if we were called with IsNocapture=true the first time. Fixes PR20405!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213726 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRework to let RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s pass on win32.
NAKAMURA Takumi [Wed, 23 Jul 2014 04:32:21 +0000 (04:32 +0000)]
Rework to let RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s pass on win32.

FIXME: "llvm-rtdyld -verify -check" is still sensitive to path separator.
Fix searching StubMap to be tolerant of both '/' and '\\' on Win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213723 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSuppress a test on win32 for now, llvm/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86...
NAKAMURA Takumi [Wed, 23 Jul 2014 04:05:58 +0000 (04:05 +0000)]
Suppress a test on win32 for now, llvm/test/ExecutionEngine/RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s.

FIXME: Fix searching StubMap with '/' and '\\' on Win32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213721 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRuntimeDyld/X86/MachO_x86-64_PIC_relocations.s: Use %/T here, or sed(1) would be...
NAKAMURA Takumi [Wed, 23 Jul 2014 04:05:46 +0000 (04:05 +0000)]
RuntimeDyld/X86/MachO_x86-64_PIC_relocations.s: Use %/T here, or sed(1) would be confused with dos path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213720 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTrailing whitespace.
NAKAMURA Takumi [Wed, 23 Jul 2014 00:42:52 +0000 (00:42 +0000)]
Trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213711 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRuntimeDyldMachOAArch64.h: Fix a warning. [-Wunused-variable]
NAKAMURA Takumi [Wed, 23 Jul 2014 00:17:44 +0000 (00:17 +0000)]
RuntimeDyldMachOAArch64.h: Fix a warning. [-Wunused-variable]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213710 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Make stub_addr functionality in RuntimeDyldChecker work in release mode.
Lang Hames [Tue, 22 Jul 2014 23:50:51 +0000 (23:50 +0000)]
[MCJIT] Make stub_addr functionality in RuntimeDyldChecker work in release mode.

There's no reason to restrict this particular piece of RuntimeDyldChecker
functionality to +Asserts builds.

This should fix failures in MachO_x86-64_PIC_relocations.s on release bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213708 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Teach RuntimeDyldChecker to handle underscores at the start of symbols.
Lang Hames [Tue, 22 Jul 2014 23:17:21 +0000 (23:17 +0000)]
[MCJIT] Teach RuntimeDyldChecker to handle underscores at the start of symbols.

RuntimeDyldChecker had been testing isalpha(Expr[0]) to recognise symbol tokens,
and throwing unrecognized token errors when it hit symbols with leading
underscores. This fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213706 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoXFAIL the test on MIPS
Juergen Ributzka [Tue, 22 Jul 2014 23:15:01 +0000 (23:15 +0000)]
XFAIL the test on MIPS

Not sure how to debug this one without a MIPS machine. Any takers?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213705 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastIsel][AArch64] Add support for the FastLowerCall and FastLowerIntrinsicCall...
Juergen Ributzka [Tue, 22 Jul 2014 23:14:58 +0000 (23:14 +0000)]
[FastIsel][AArch64] Add support for the FastLowerCall and FastLowerIntrinsicCall target-hooks.

This commit modifies the existing call lowering functions to be used as the
FastLowerCall and FastLowerIntrinsicCall target-hooks instead.

This enables patchpoint intrinsic lowering for AArch64.

This fixes <rdar://problem/17733076>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213704 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Use CHECK-LABEL in ARM64 ABI unit tests.
Juergen Ributzka [Tue, 22 Jul 2014 23:14:54 +0000 (23:14 +0000)]
[AArch64] Use CHECK-LABEL in ARM64 ABI unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213703 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Improve stub_addr file-not-found diagnostic to help track down a
Lang Hames [Tue, 22 Jul 2014 23:07:52 +0000 (23:07 +0000)]
[MCJIT] Improve stub_addr file-not-found diagnostic to help track down a
buildbot failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213701 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Refactor and add stub inspection to the RuntimeDyldChecker framework.
Lang Hames [Tue, 22 Jul 2014 22:47:39 +0000 (22:47 +0000)]
[MCJIT] Refactor and add stub inspection to the RuntimeDyldChecker framework.

This patch introduces a 'stub_addr' builtin that can be used to find the address
of the stub for a given (<file>, <section>, <symbol>) tuple. This address can be
used both to verify the contents of stubs (by loading from the returned address)
and to verify references to stubs (by comparing against the returned address).

Example (1) - Verifying stub contents:

Load 8 bytes (assuming a 64-bit target) from the stub for 'x' in the __text
section of f.o, and compare that value against the addres of 'x'.

# rtdyld-check: *{8}(stub_addr(f.o, __text, x) = x

Example (2) - Verifying references to stubs:

Decode the immediate of the instruction at label 'l', and verify that it's
equal to the offset from the next instruction's PC to the stub for 'y' in the
__text section of f.o (i.e. it's the correct PC-rel difference).

# rtdyld-check: decode_operand(l, 4) = stub_addr(f.o, __text, y) - next_pc(l)
l:
        movq    y@GOTPCREL(%rip), %rax

Since stub inspection requires cooperation with RuntimeDyldImpl this patch
pimpl-ifies RuntimeDyldChecker. Its implementation is moved in to a new class,
RuntimeDyldCheckerImpl, that has access to the definition of RuntimeDyldImpl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213698 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAppease the buildbots.
Juergen Ributzka [Tue, 22 Jul 2014 22:02:19 +0000 (22:02 +0000)]
Appease the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213694 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld][MachO][AArch64] Add a helper function for encoding addends in instructions.
Juergen Ributzka [Tue, 22 Jul 2014 21:42:55 +0000 (21:42 +0000)]
[RuntimeDyld][MachO][AArch64] Add a helper function for encoding addends in instructions.

Factor out the addend encoding into a helper function and simplify the
processRelocationRef.

Also add a few simple rtdyld tests. More tests to come once GOTs can be tested too.

Related to <rdar://problem/17768539>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213689 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld][MachO][AArch64] Implement the decodeAddend method.
Juergen Ributzka [Tue, 22 Jul 2014 21:42:51 +0000 (21:42 +0000)]
[RuntimeDyld][MachO][AArch64] Implement the decodeAddend method.

This adds the required functionality to decode the immediate encoded in an
instruction that is referenced in a relocation entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213688 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld][MachO][AArch64] Add assertion to check for duplicate addend definition.
Juergen Ributzka [Tue, 22 Jul 2014 21:42:49 +0000 (21:42 +0000)]
[RuntimeDyld][MachO][AArch64] Add assertion to check for duplicate addend definition.

In MachO for AArch64 it is possible to have an explicit addend defined by
the ARM64_RELOC_ADDEND relocation or having an addend encoded within the
instruction. Only one of them are allowed per relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213687 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld] Change the return type of decodeAddend to match the storage type.
Juergen Ributzka [Tue, 22 Jul 2014 21:42:46 +0000 (21:42 +0000)]
[RuntimeDyld] Change the return type of decodeAddend to match the storage type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213686 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoThis patch implements optimization as mentioned in PR19753: Optimize comparisons...
Suyog Sarda [Tue, 22 Jul 2014 19:19:36 +0000 (19:19 +0000)]
This patch implements optimization as mentioned in PR19753: Optimize comparisons with "ashr/lshr exact" of a constanst.
It handles the errors which were seen in PR19958 where wrong code was being emitted due to earlier patch.
Added code for lshr as well as non-exact right shifts.

It implements :
(icmp eq/ne (ashr/lshr const2, A), const1)" ->
(icmp eq/ne A, Log2(const2/const1)) ->
(icmp eq/ne A, Log2(const2) - Log2(const1))

Differential Revision: http://reviews.llvm.org/D4068

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213678 91177308-0d34-0410-b5e6-96231b3b80d8