oota-llvm.git
9 years agoBe more specific and capitalize filenames.
Eric Christopher [Tue, 21 May 2013 21:22:34 +0000 (21:22 +0000)]
Be more specific and capitalize filenames.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182424 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDefine BYTE_ORDER on Solaris.
Jakob Stoklund Olesen [Tue, 21 May 2013 20:36:13 +0000 (20:36 +0000)]
Define BYTE_ORDER on Solaris.

Solaris doesn't have an endian.h header, but SPARC is the only
big-endian architecture that runs Solaris, so just use that to detect
endianness at compile time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182419 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPut RTDyldMemoryManager into its own file, and make it linked into
Filip Pizlo [Tue, 21 May 2013 20:24:07 +0000 (20:24 +0000)]
Put RTDyldMemoryManager into its own file, and make it linked into
libExecutionEngine. Move method implementations that aren't specific to
allocation out of SectionMemoryManager and into RTDyldMemoryManager.

This is in preparation for exposing RTDyldMemoryManager through the C
API.

This is a fixed version of r182407 and r182411. That first revision
broke builds because I forgot to move the conditional includes of
various POSIX headers from SectionMemoryManager into
RTDyldMemoryManager. Those includes are necessary because of how
getPointerToNamedFunction works around the glibc libc_nonshared.a thing.
The latter revision still broke things because I forgot to include
llvm/Config/config.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182418 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRoll out r182411 and 182412 because it's still broken.
Filip Pizlo [Tue, 21 May 2013 20:17:14 +0000 (20:17 +0000)]
Roll out r182411 and 182412 because it's still broken.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182415 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix busted comment. This conditional include block used to be in SectionMemoryManager...
Filip Pizlo [Tue, 21 May 2013 20:11:01 +0000 (20:11 +0000)]
Fix busted comment. This conditional include block used to be in SectionMemoryManager, but is now in RTDyldMemoryManager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182412 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPut RTDyldMemoryManager into its own file, and make it linked into
Filip Pizlo [Tue, 21 May 2013 20:07:12 +0000 (20:07 +0000)]
Put RTDyldMemoryManager into its own file, and make it linked into
libExecutionEngine. Move method implementations that aren't specific to
allocation out of SectionMemoryManager and into RTDyldMemoryManager.

This is in preparation for exposing RTDyldMemoryManager through the C
API.

This is a fixed version of r182407. That revision broke builds because I
forgot to move the conditional includes of various POSIX headers from
SectionMemoryManager into RTDyldMemoryManager. Those includes are
necessary because of how getPointerToNamedFunction works around the
glibc libc_nonshared.a thing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182411 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRoll out r182407 and r182408 because they broke builds.
Filip Pizlo [Tue, 21 May 2013 20:03:01 +0000 (20:03 +0000)]
Roll out r182407 and r182408 because they broke builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182409 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExpose the RTDyldMemoryManager through the C API. This allows clients of
Filip Pizlo [Tue, 21 May 2013 20:00:56 +0000 (20:00 +0000)]
Expose the RTDyldMemoryManager through the C API. This allows clients of
the C API to provide their own way of allocating JIT memory (both code
and data) and finalizing memory permissions (page protections, cache
flush).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182408 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPut RTDyldMemoryManager into its own file, and make it linked into
Filip Pizlo [Tue, 21 May 2013 19:56:00 +0000 (19:56 +0000)]
Put RTDyldMemoryManager into its own file, and make it linked into
libExecutionEngine. Move method implementations that aren't specific to
allocation out of SectionMemoryManager and into RTDyldMemoryManager.

This is in preparation for exposing RTDyldMemoryManager through the C
API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182407 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUse std::list so that we have a stable iterator.
Rafael Espindola [Tue, 21 May 2013 18:53:50 +0000 (18:53 +0000)]
Use std::list so that we have a stable iterator.

I will try to avoid creating these std::strings, but for now this gets
the tests passing with libc++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182405 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove duplicated comment.
Benjamin Kramer [Tue, 21 May 2013 18:06:33 +0000 (18:06 +0000)]
Remove duplicated comment.

Found by -Wdocumentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182402 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegenerate configure.
Rafael Espindola [Tue, 21 May 2013 17:59:15 +0000 (17:59 +0000)]
Regenerate configure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182401 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Rename option to make it compatible with gcc.
Akira Hatanaka [Tue, 21 May 2013 17:17:59 +0000 (17:17 +0000)]
[mips] Rename option to make it compatible with gcc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182397 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Add instruction selection patterns for blez and bgez.
Akira Hatanaka [Tue, 21 May 2013 17:13:47 +0000 (17:13 +0000)]
[mips] Add instruction selection patterns for blez and bgez.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182396 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic
Justin Holewinski [Tue, 21 May 2013 16:51:30 +0000 (16:51 +0000)]
[NVPTX] Add @llvm.nvvm.sqrt.f() intrinsic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182394 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoHexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.
Jyotsna Verma [Tue, 21 May 2013 15:54:32 +0000 (15:54 +0000)]
Hexagon: SelectionDAG should not use MVT::Other to check the legality of BR_CC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182390 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDrop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.
Justin Holewinski [Tue, 21 May 2013 14:37:16 +0000 (14:37 +0000)]
Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.

The intrinsic calls are dropped, but the annotated value is propagated.

Fixes PR 15253

Original patch by Zeng Bin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182387 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix PPC branch selection for counter-based branches
Hal Finkel [Tue, 21 May 2013 14:21:09 +0000 (14:21 +0000)]
Fix PPC branch selection for counter-based branches

Although I had added some support for the BDZ/BDNZ branches into the selector
(in r158204), I had not correctly adjusted the condition at the top of the
loop. As a result, these branches were still essentially unsupported.

This fixes PR16086. Unfortunately, any test case would be very large (because
it would need to force the loop backedge to exceed the range of the 16-bit
immediate).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182385 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoremoved commented lines
Elena Demikhovsky [Tue, 21 May 2013 13:27:44 +0000 (13:27 +0000)]
removed commented lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182377 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[msan] A no-op implementation of VarArg handling.
Evgeniy Stepanov [Tue, 21 May 2013 12:27:47 +0000 (12:27 +0000)]
[msan] A no-op implementation of VarArg handling.

This stuff is used on platforms where MSan does not have a proper VarArg
implementation (anything other than x86_64 at the moment).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182375 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemoved SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare...
Elena Demikhovsky [Tue, 21 May 2013 12:04:22 +0000 (12:04 +0000)]
Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar compare instructions, like COMISS, COMISD.
No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAlternative fix for problem addressed in r182233
Ulrich Weigand [Tue, 21 May 2013 10:30:59 +0000 (10:30 +0000)]
Alternative fix for problem addressed in r182233

Revision r182233 partially reverted the change in r181200 to simplify
JIT unif test #ifdefs, because that change caused a link error on some
host operating systems where the export list requires the following
symbols to be defined:

 JITTest_AvailableExternallyFunction
 JITTest_AvailableExternallyGlobal

As discussed on the list, the commit reverts r182233 (and re-installs
the full r181200 change), and instead fixes the link problem by moving
those two symbols to the top of the file and unconditionally defining
them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182367 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoX86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller...
Benjamin Kramer [Tue, 21 May 2013 09:58:54 +0000 (09:58 +0000)]
X86: When emulating unsigned PCMPGTQ with PCMPGTD, fix the sign bit for the smaller type.

Otherwise we'll get a mix of signed and unsigned compares.
Fixes PR15977.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182364 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SystemZ] Tighten branch tests
Richard Sandiford [Tue, 21 May 2013 08:53:17 +0000 (08:53 +0000)]
[SystemZ] Tighten branch tests

After r182274, the branches in these tests must always be short.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182358 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.
Benjamin Kramer [Tue, 21 May 2013 08:51:09 +0000 (08:51 +0000)]
DAGCombine: Avoid an edge case where it tried to create an i0 type for (x & 0) == 0.

Fixes PR16083.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182357 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix indentation
Richard Sandiford [Tue, 21 May 2013 08:48:24 +0000 (08:48 +0000)]
Fix indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182356 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd cmake bits for md5.
Eric Christopher [Tue, 21 May 2013 01:30:38 +0000 (01:30 +0000)]
Add cmake bits for md5.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182349 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd an md5 library derived from a public domain implementation for dwarf4
Eric Christopher [Tue, 21 May 2013 01:28:35 +0000 (01:28 +0000)]
Add an md5 library derived from a public domain implementation for dwarf4
type signature computation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182348 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd checks that the proper predeined stubs are being called to the test case.
Reed Kotler [Tue, 21 May 2013 01:27:36 +0000 (01:27 +0000)]
Add checks that the proper predeined stubs are being called to the test case.
These were accidentally omitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182347 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDwarf: use a single line table to generate assembly when .loc is used.
Manman Ren [Tue, 21 May 2013 00:57:22 +0000 (00:57 +0000)]
Dwarf: use a single line table to generate assembly when .loc is used.

This is to fix PR15408 where an undefined symbol Lline_table_start1 is used.
Since we do not generate the debug_line section when .loc is used,
Lline_table_start1 is not emitted and we can't refer to it when calculating
at_stmt_list for a compile unit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182344 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd some additional functions to the list of helper functions for
Reed Kotler [Tue, 21 May 2013 00:50:30 +0000 (00:50 +0000)]
Add some additional functions to the list of helper functions for
pic calls. These need to be there so we don't try and use helper
functions when we call those.

As part of this, make sure that we properly exclude helper functions in pic
mode when indirect calls are involved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182343 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoComment update: these things are called "configuration names" these days, not
Richard Smith [Mon, 20 May 2013 23:55:41 +0000 (23:55 +0000)]
Comment update: these things are called "configuration names" these days, not
"triples". Also remove the implication that they're only used for specifying a
target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182335 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLangRef.rst: Clarify how basic blocks without named label are handled.
Sean Silva [Mon, 20 May 2013 23:31:12 +0000 (23:31 +0000)]
LangRef.rst: Clarify how basic blocks without named label are handled.

Describe that they are assigned numbered label using the same counter
as for unnamed temporaries.

Based on http://llvm.org/bugs/show_bug.cgi?id=16043 and mailing list
discussion.

Patch by Paul Sokolovsky!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182332 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPR14606: Debug Info for namespace aliases/DW_TAG_imported_module
David Blaikie [Mon, 20 May 2013 22:50:35 +0000 (22:50 +0000)]
PR14606: Debug Info for namespace aliases/DW_TAG_imported_module

This resolves the last of the PR14606 failures in the GDB 7.5 test
suite by implementing an optional name field for
DW_TAG_imported_modules/DIImportedEntities and using that to implement
C++ namespace aliases (eg: "namespace X = Y;").

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182328 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[docs] Minor doc tweaks.
Daniel Dunbar [Mon, 20 May 2013 22:39:48 +0000 (22:39 +0000)]
[docs] Minor doc tweaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182324 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoThe DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like...
Bill Wendling [Mon, 20 May 2013 21:54:18 +0000 (21:54 +0000)]
The DWARF EH pass doesn't need the TargetMachine, only the TargetLoweringBase like the other EH passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182321 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoNo need to store the TargetMachine variable in this class.
Bill Wendling [Mon, 20 May 2013 21:28:28 +0000 (21:28 +0000)]
No need to store the TargetMachine variable in this class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182317 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove unused #include.
Bill Wendling [Mon, 20 May 2013 20:59:12 +0000 (20:59 +0000)]
Remove unused #include.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182315 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRename LoopSimplify.h to LoopUtils.h
Hal Finkel [Mon, 20 May 2013 20:46:30 +0000 (20:46 +0000)]
Rename LoopSimplify.h to LoopUtils.h

As discussed, LoopUtils.h is a better name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182314 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoadd polly to check-all
Sebastian Pop [Mon, 20 May 2013 18:49:15 +0000 (18:49 +0000)]
add polly to check-all

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182308 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Add (setne $lhs, 0) instruction selection pattern.
Akira Hatanaka [Mon, 20 May 2013 18:18:07 +0000 (18:18 +0000)]
[mips] Add (setne $lhs, 0) instruction selection pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182307 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Trap on integer division by zero.
Akira Hatanaka [Mon, 20 May 2013 18:07:43 +0000 (18:07 +0000)]
[mips] Trap on integer division by zero.

By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182306 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove copied preheader insertion logic from PPCCTRLoops
Hal Finkel [Mon, 20 May 2013 16:47:10 +0000 (16:47 +0000)]
Remove copied preheader insertion logic from PPCCTRLoops

Now that the preheader insertion logic in LoopSimplify is externally exposed,
use it, and remove the copy-and-pasted version.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182300 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoExpose InsertPreheaderForLoop from LoopSimplify to other passes
Hal Finkel [Mon, 20 May 2013 16:47:07 +0000 (16:47 +0000)]
Expose InsertPreheaderForLoop from LoopSimplify to other passes

Other passes, PPC counter-loop formation for example, also need to add loop
preheaders outside of the regular loop simplification pass. This makes
InsertPreheaderForLoop a global function so that it can be used by other
passes.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182299 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter. This was causing a symbol...
Justin Holewinski [Mon, 20 May 2013 16:42:18 +0000 (16:42 +0000)]
[NVPTX] Fix mis-use of CurrentFnSym in NVPTXAsmPrinter.  This was causing a symbol name error in the output PTX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182298 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] Add programmatic interface to NVVMReflect pass
Justin Holewinski [Mon, 20 May 2013 16:42:16 +0000 (16:42 +0000)]
[NVPTX] Add programmatic interface to NVVMReflect pass

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182297 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRename PPC MTCTRse to MTCTRloop
Hal Finkel [Mon, 20 May 2013 16:08:37 +0000 (16:08 +0000)]
Rename PPC MTCTRse to MTCTRloop

As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd a PPCCTRLoops verification pass
Hal Finkel [Mon, 20 May 2013 16:08:17 +0000 (16:08 +0000)]
Add a PPCCTRLoops verification pass

When asserts are enabled, this adds a verification pass for PPC counter-loop
formation. Unfortunately, without sacrificing code quality, there is no better
way of forming counter-based loops except at the (late) IR level. This means
that we need to recognize, at the IR level, anything which might turn into a
function call (or indirect branch). Because this is currently a finite set of
things, and because SelectionDAG lowering is basic-block local, this can be
done. Nevertheless, it is fragile, and failure results in a miscompile. This
verification pass checks that all (reachable) counter-based branches are
dominated by a loop mtctr instruction, and that no instructions in between
clobber the counter register. If these conditions are not satisfied, then an
ICE will be triggered.

In short, this is to help us sleep better at night.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182295 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Fix bug detected by GCC warning.
Benjamin Kramer [Mon, 20 May 2013 15:58:43 +0000 (15:58 +0000)]
R600: Fix bug detected by GCC warning.

R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182293 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Fix rotr.ll on non-asserts builds
Tom Stellard [Mon, 20 May 2013 15:28:48 +0000 (15:28 +0000)]
R600: Fix rotr.ll on non-asserts builds

The -debug-only option is only available on asserts builds.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182291 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Use a multiclass for MUBUF_Load_Helper
Tom Stellard [Mon, 20 May 2013 15:02:31 +0000 (15:02 +0000)]
R600/SI: Use a multiclass for MUBUF_Load_Helper

This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182288 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions
Tom Stellard [Mon, 20 May 2013 15:02:28 +0000 (15:02 +0000)]
R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182287 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add pattern for rotr
Tom Stellard [Mon, 20 May 2013 15:02:24 +0000 (15:02 +0000)]
R600/SI: Add pattern for rotr

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182286 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600: Swap the legality of rotl and rotr
Tom Stellard [Mon, 20 May 2013 15:02:19 +0000 (15:02 +0000)]
R600: Swap the legality of rotl and rotr

The hardware supports rotr and not rotl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Add patterns for 64-bit shift operations
Tom Stellard [Mon, 20 May 2013 15:02:12 +0000 (15:02 +0000)]
R600/SI: Add patterns for 64-bit shift operations

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182284 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Use the same names for VOP3 operands and encoding fields
Tom Stellard [Mon, 20 May 2013 15:02:08 +0000 (15:02 +0000)]
R600/SI: Use the same names for VOP3 operands and encoding fields

This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoR600/SI: Make fitsRegClass() operands const
Tom Stellard [Mon, 20 May 2013 15:02:01 +0000 (15:02 +0000)]
R600/SI: Make fitsRegClass() operands const

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoVSTn instructions have a number of encoding constraints which are not implemented...
Mihai Popa [Mon, 20 May 2013 14:57:05 +0000 (14:57 +0000)]
VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182281 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoQ registers are encoded in fields of the same length as D registers. As Q registers...
Mihai Popa [Mon, 20 May 2013 14:42:43 +0000 (14:42 +0000)]
Q registers are encoded in fields of the same length as D registers. As Q registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182279 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SystemZ] Add long branch pass
Richard Sandiford [Mon, 20 May 2013 14:23:08 +0000 (14:23 +0000)]
[SystemZ] Add long branch pass

Before this change, the SystemZ backend would use BRCL for all branches
and only consider shortening them to BRC when generating an object file.
E.g. a branch on equal would use the JGE alias of BRCL in assembly output,
but might be shortened to the JE alias of BRC in ELF output.  This was
a useful first step, but it had two problems:

(1) The z assembler isn't traditionally supposed to perform branch shortening
    or branch relaxation.  We followed this rule by not relaxing branches
    in assembler input, but that meant that generating assembly code and
    then assembling it would not produce the same result as going directly
    to object code; the former would give long branches everywhere, whereas
    the latter would use short branches where possible.

(2) Other useful branches, like COMPARE AND BRANCH, do not have long forms.
    We would need to do something else before supporting them.

    (Although COMPARE AND BRANCH does not change the condition codes,
    the plan is to model COMPARE AND BRANCH as a CC-clobbering instruction
    during codegen, so that we can safely lower it to a separate compare
    and long branch where necessary.  This is not a valid transformation
    for the assembler proper to make.)

This patch therefore moves branch relaxation to a pre-emit pass.
For now, calls are still shortened from BRASL to BRAS by the assembler,
although this too is not really the traditional behaviour.

The first test takes about 1.5s to run, and there are likely to be
more tests in this vein once further branch types are added.  The feeling
on IRC was that 1.5s is a bit much for a single test, so I've restricted
it to SystemZ hosts for now.

The patch exposes (and fixes) some typos in the main CodeGen/SystemZ tests.
A later patch will remove the {{g}}s from that directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182274 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoEnable pod-like optimizations for pred and succ iterators.
Benjamin Kramer [Mon, 20 May 2013 13:12:58 +0000 (13:12 +0000)]
Enable pod-like optimizations for pred and succ iterators.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182257 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs
Justin Holewinski [Mon, 20 May 2013 12:13:32 +0000 (12:13 +0000)]
[NVPTX] Add GenericToNVVM IR converter to better handle idiomatic LLVM IR inputs

This converter currently only handles global variables in address space 0. For
these variables, they are promoted to address space 1 (global memory), and all
uses are updated to point to the result of a cvta.global instruction on the new
variable.

The motivation for this is address space 0 global variables are illegal since we
cannot declare variables in the generic address space.  Instead, we place the
variables in address space 1 and explicitly convert the pointer to address
space 0. This is primarily intended to help new users who expect to be able to
place global variables in the default address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182254 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[NVPTX] Fix i1 kernel parameters and global variables. ABI rules say we need to...
Justin Holewinski [Mon, 20 May 2013 12:13:28 +0000 (12:13 +0000)]
[NVPTX] Fix i1 kernel parameters and global variables.  ABI rules say we need to use .u8 for i1 parameters for kernels.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182253 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPR15868 fix.
Stepan Dyatkovskiy [Mon, 20 May 2013 08:01:34 +0000 (08:01 +0000)]
PR15868 fix.

Introduction:
In case when stack alignment is 8 and GPRs parameter part size is not N*8:
we add padding to GPRs part, so part's last byte must be recovered at
address K*8-1.
We need to do it, since remained (stack) part of parameter starts from
address K*8, and we need to "attach" "GPRs head" without gaps to it:

Stack:
|---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
[ [padding] [GPRs head] ] [ ------ Tail passed via stack  ------ ...

FIX:
Note, once we added padding we need to correct *all* Arg offsets that are going
after padded one. That's why we need this fix: Arg offsets were never corrected
before this patch. See new test-cases included in patch.

We also don't need to insert padding for byval parameters that are stored in GPRs
only. We need pad only last byval parameter and only in case it outsides GPRs
and stack alignment = 8.
Though, stack area, allocated for recovered byval params, must satisfy
"Size mod 8 = 0" restriction.

This patch reduces stack usage for some cases:
We can reduce ArgRegsSaveArea since inner N*4 bytes sized byval params my be
"packed" with alignment 4 in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182237 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDisable remote MCJIT on pre-v6 ARM
Renato Golin [Mon, 20 May 2013 07:46:06 +0000 (07:46 +0000)]
Disable remote MCJIT on pre-v6 ARM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182235 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPartially revert change in r181200 that tried to simplify JIT unit test #ifdefs.
Bob Wilson [Mon, 20 May 2013 06:13:09 +0000 (06:13 +0000)]
Partially revert change in r181200 that tried to simplify JIT unit test #ifdefs.

The export list for this test requires the following symbols to be available:
  JITTest_AvailableExternallyFunction
  JITTest_AvailableExternallyGlobal
The change in r181200 commented them out, which caused the test to fail to
link, at least on Darwin. I have only reverted the change for arm, since I
can't test the other targets and since it sounds like that change was fixing
real problems for those other targets. It should be possible to rearrange the
code to keep those definitions outside the #ifdefs, but that should be done by
someone who can reproduce the problems that r181200 was trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182233 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAlso expand 64-bit bitcasts.
Jakob Stoklund Olesen [Mon, 20 May 2013 01:01:43 +0000 (01:01 +0000)]
Also expand 64-bit bitcasts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImplement spill and fill of I64Regs.
Jakob Stoklund Olesen [Mon, 20 May 2013 00:53:25 +0000 (00:53 +0000)]
Implement spill and fill of I64Regs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182228 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMark i64 SETCC as expand so it is turned into a SELECT_CC.
Jakob Stoklund Olesen [Mon, 20 May 2013 00:28:36 +0000 (00:28 +0000)]
Mark i64 SETCC as expand so it is turned into a SELECT_CC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182227 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReplace some bit operations with simpler ones. No functionality change.
Benjamin Kramer [Sun, 19 May 2013 22:01:57 +0000 (22:01 +0000)]
Replace some bit operations with simpler ones. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182226 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't use %g0 to materialize 0 directly.
Jakob Stoklund Olesen [Sun, 19 May 2013 21:47:13 +0000 (21:47 +0000)]
Don't use %g0 to materialize 0 directly.

The wired physreg doesn't work on tied operands like on MOVXCC.

Add a README note to fix this later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182225 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSelect i64 values with %icc conditions.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:38:21 +0000 (20:38 +0000)]
Select i64 values with %icc conditions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182224 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>
Bob Wilson [Sun, 19 May 2013 20:33:51 +0000 (20:33 +0000)]
Remove declaration of __clear_cache for __APPLE__. <rdar://problem/13924072>

This fixes a bootstrapping problem with builds for Apple ARM targets.
Clang had the wrong prototype for __clear_cache with ARM targets.  Rafael
fixed that in clang svn r181784 and r181810, but without those changes,
we can't build this code for ARM because clang reports an error about the
declaration in Memory.inc not matching the builtin declaration. Some of our
buildbots need to use an older compiler that doesn't have the clang fix.
Since __clear_cache is never used here when __APPLE__ is defined, I'm just
conditionalizing the declaration to match that. I also moved the declaration
of sys_icache_invalidate inside the conditional for __APPLE__ while I was at
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182223 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd floating point selects on %xcc predicates.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:33:11 +0000 (20:33 +0000)]
Add floating point selects on %xcc predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182222 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoImplement SPselectfcc for i64 operands.
Jakob Stoklund Olesen [Sun, 19 May 2013 20:20:54 +0000 (20:20 +0000)]
Implement SPselectfcc for i64 operands.

Also clean up the arguments to all the MOVCC instructions so the
operands always are (true-val, false-val, cond-code).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182221 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSubArch support in MCJIT unittest
Renato Golin [Sun, 19 May 2013 20:10:10 +0000 (20:10 +0000)]
SubArch support in MCJIT unittest

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182220 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Sparc] Rearrange integer registers' allocation order so that register allocator...
Venkatraman Govindaraju [Sun, 19 May 2013 20:07:20 +0000 (20:07 +0000)]
[Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers.

Also, enable registers %g2-%g4 to be used in application and %g5 in 64 bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182219 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAArch64: enable MCJIT unittests
Tim Northover [Sun, 19 May 2013 19:44:56 +0000 (19:44 +0000)]
AArch64: enable MCJIT unittests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182217 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoHandle i64 FrameIndex nodes in SPARC v9 mode.
Jakob Stoklund Olesen [Sun, 19 May 2013 19:14:24 +0000 (19:14 +0000)]
Handle i64 FrameIndex nodes in SPARC v9 mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182216 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAArch64: make RuntimeDyld relocations idempotent
Tim Northover [Sun, 19 May 2013 15:39:03 +0000 (15:39 +0000)]
AArch64: make RuntimeDyld relocations idempotent

AArch64 ELF uses .rela relocations so there's no need to actually make
use of the bits we're setting in the destination  However, we should
make sure all bits are cleared properly since multiple runs of
resolveRelocations are possible and these could combine to produce
invalid results if stale versions remain in the code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182214 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoInvalidate instruction cache when setting memory to be executable.
Tim Northover [Sun, 19 May 2013 15:28:16 +0000 (15:28 +0000)]
Invalidate instruction cache when setting memory to be executable.

lli's remote MCJIT code calls setExecutable just prior to running
code. In line with Darwin behaviour this seems to be the place to
invalidate any caches needed so that relocations can take effect
properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182213 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTemporarily disable this test because it is failing when using libc++.
Bob Wilson [Sun, 19 May 2013 14:59:08 +0000 (14:59 +0000)]
Temporarily disable this test because it is failing when using libc++.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182212 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMove the remaining simplify-libcalls tests to instcombine, merging most of them into...
Benjamin Kramer [Sun, 19 May 2013 13:28:39 +0000 (13:28 +0000)]
Move the remaining simplify-libcalls tests to instcombine, merging most of them into a single file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182211 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoPrint uint64_t -debug text correctly on 32-bit hosts
Tim Northover [Sun, 19 May 2013 09:55:06 +0000 (09:55 +0000)]
Print uint64_t -debug text correctly on 32-bit hosts

On 32-bit hosts %p can print garbage when given a uint64_t, we should
use %llx instead. This only affects the output of the debugging text
produced by lli.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182209 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoUnsupported remote JIT on ARM
Renato Golin [Sat, 18 May 2013 19:42:07 +0000 (19:42 +0000)]
Unsupported remote JIT on ARM

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182201 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoisKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.
David Majnemer [Sat, 18 May 2013 19:30:37 +0000 (19:30 +0000)]
isKnownToBeAPowerOfTwo: (X & Y) + Y is a power of 2 or zero if y is also.

This is useful if something that looks like (x & (1 << y)) ? 64 : 32 is
the divisor in a modulo operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182200 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoLoopVectorize: Handle single edge PHIs
Arnold Schwaighofer [Sat, 18 May 2013 18:38:34 +0000 (18:38 +0000)]
LoopVectorize: Handle single edge PHIs

We might encouter single edge PHIs - handle them with an identity select.

Fixes PR15990.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182199 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agodocs/Passes: fix some typos
Dmitri Gribenko [Sat, 18 May 2013 18:01:44 +0000 (18:01 +0000)]
docs/Passes: fix some typos

Patch by Yacine Belkadi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182197 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd basic support for ELF32-ppc relocations to llvm-dwarfdump.
Benjamin Kramer [Sat, 18 May 2013 16:00:35 +0000 (16:00 +0000)]
Add basic support for ELF32-ppc relocations to llvm-dwarfdump.

Should help the ppc32 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182194 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCheck InlineAsm clobbers in PPCCTRLoops
Hal Finkel [Sat, 18 May 2013 09:20:39 +0000 (09:20 +0000)]
Check InlineAsm clobbers in PPCCTRLoops

We don't need to reject all inline asm as using the counter register (most does
not). Only those that explicitly clobber the counter register need to prevent
the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182191 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAArch64: add CMake dependency to fix very parallel builds
Tim Northover [Sat, 18 May 2013 08:17:47 +0000 (08:17 +0000)]
AArch64: add CMake dependency to fix very parallel builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182190 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoX86: Bad peephole interaction between adc, MOV32r0
David Majnemer [Sat, 18 May 2013 01:02:03 +0000 (01:02 +0000)]
X86: Bad peephole interaction between adc, MOV32r0

The peephole tries to reorder MOV32r0 instructions such that they are
before the instruction that modifies EFLAGS.

The problem is that the peephole does not consider the case where the
instruction that modifies EFLAGS also depends on the previous state of
EFLAGS.

Instead, walk backwards until we find an instruction that has a def for
EFLAGS but does not have a use.
If we find such an instruction, insert the MOV32r0 before it.
If it cannot find such an instruction, skip the optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove duplicated comment
Matt Arsenault [Sat, 18 May 2013 00:24:09 +0000 (00:24 +0000)]
Remove duplicated comment

The same comment is already made in the header

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182181 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd LLVMContext argument to getSetCCResultType
Matt Arsenault [Sat, 18 May 2013 00:21:46 +0000 (00:21 +0000)]
Add LLVMContext argument to getSetCCResultType

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSupport unaligned load/store on more ARM targets
JF Bastien [Fri, 17 May 2013 23:49:01 +0000 (23:49 +0000)]
Support unaligned load/store on more ARM targets

This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.

The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).

The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.

I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the configure build.
Rafael Espindola [Fri, 17 May 2013 23:20:58 +0000 (23:20 +0000)]
Fix the configure build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182172 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoConvert obj2yaml to use yamlio.
Rafael Espindola [Fri, 17 May 2013 22:58:42 +0000 (22:58 +0000)]
Convert obj2yaml to use yamlio.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182169 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix the build in c++11 mode.
Rafael Espindola [Fri, 17 May 2013 22:45:52 +0000 (22:45 +0000)]
Fix the build in c++11 mode.

The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182168 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReplace redundant code
Matt Arsenault [Fri, 17 May 2013 21:43:43 +0000 (21:43 +0000)]
Replace redundant code

Use EVT::changeExtendedVectorElementTypeToInteger instead of doing the
same thing that it does

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182165 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd missing -*- C++ -*- to headers
Matt Arsenault [Fri, 17 May 2013 21:43:39 +0000 (21:43 +0000)]
Add missing -*- C++ -*- to headers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182164 91177308-0d34-0410-b5e6-96231b3b80d8