8 years agoProgrammersManual.rst: fix a typo
Hans Wennborg [Sat, 17 Jan 2015 03:19:21 +0000 (03:19 +0000)]
ProgrammersManual.rst: fix a typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226367 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoImprove DAG combine pass on certain IR vector patterns
Mehdi Amini [Sat, 17 Jan 2015 01:35:56 +0000 (01:35 +0000)]
Improve DAG combine pass on certain IR vector patterns

Loading 2 2x32-bit float vectors into the bottom half of a 256-bit vector
produced suboptimal code in AVX2 mode with certain IR combinations.

In particular, the IR optimizer folded 2f32 + 2f32 -> 4f32, 4f32 + 4f32
(undef) -> 8f32 into a 2f32 + 2f32 -> 8f32, which seems more canonical,
but then mysteriously generated rather bad code; the movq/movhpd combination
didn't match.

The problem lay in the BUILD_VECTOR optimization path. The 2f32 inputs
would get promoted to 4f32 by the type legalizer, eventually resulting
in a BUILD_VECTOR on two 4f32 into an 8f32. The BUILD_VECTOR then, recognizing
these were both half the output size, concatted them and then produced
a shuffle. However, the resulting concat + shuffle was more complex than
it should be; in the case where the upper half of the output is undef, we
probably want to generate shuffle + concat instead.

This enhancement causes the vector_shuffle combine step to recognize this
suboptimal pattern and correct it. I included it there instead of in BUILD_VECTOR
in case the same suboptimal pattern occurs for other reasons.

This results in the optimizer correctly producing the optimal movq + movhpd
sequence for all three variations on this IR, even with AVX2.

I've included a test case.

Radar link: rdar://problem/19287012
Fix for PR 21943.

From: Fiona Glaser <fglaser@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226360 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld] Tidy up emitCommonSymbols a little. NFC.
Lang Hames [Sat, 17 Jan 2015 00:55:05 +0000 (00:55 +0000)]
[RuntimeDyld] Tidy up emitCommonSymbols a little. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226358 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove std::move that was preventing return value optimization.
Richard Trieu [Sat, 17 Jan 2015 00:46:44 +0000 (00:46 +0000)]
Remove std::move that was preventing return value optimization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226356 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRegisterCoalescer: Cleanup and improved comment for a subtle detail.
Matthias Braun [Sat, 17 Jan 2015 00:33:13 +0000 (00:33 +0000)]
RegisterCoalescer: Cleanup and improved comment for a subtle detail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226353 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRegisterCoalescer: Cleanup by factoring out a common expression
Matthias Braun [Sat, 17 Jan 2015 00:33:11 +0000 (00:33 +0000)]
RegisterCoalescer: Cleanup by factoring out a common expression

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226352 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRegisterCoalescer: Cleanup comment style
Matthias Braun [Sat, 17 Jan 2015 00:33:09 +0000 (00:33 +0000)]
RegisterCoalescer: Cleanup comment style

- Consistenly put comments above the function declaration, not the
  definition. To achieve this some duplicate comments got merged and
  some comment parts describing implementation details got moved into their
- Consistently use doxygen comments above functions.
- Do not use doxygen comments inside functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226351 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRegisterCoalescer: Drive-by typo + whitespace fix
Matthias Braun [Sat, 17 Jan 2015 00:33:06 +0000 (00:33 +0000)]
RegisterCoalescer: Drive-by typo + whitespace fix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226350 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld] Remove the brace initialization that was introduced in r226341.
Lang Hames [Sat, 17 Jan 2015 00:32:56 +0000 (00:32 +0000)]
[RuntimeDyld] Remove the brace initialization that was introduced in r226341.
Evidently MSVC doesn't like it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226349 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoChange the test case for llvm-objdump’s -archive-headers option to not check the...
Kevin Enderby [Fri, 16 Jan 2015 23:29:07 +0000 (23:29 +0000)]
Change the test case for llvm-objdump’s -archive-headers option to not check the size
while I once again try to figure out why only the clang-cmake-armv7-a15-full bot
is getting that value wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226345 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate a comment
Philip Reames [Fri, 16 Jan 2015 23:21:07 +0000 (23:21 +0000)]
Update a comment

Be a bit more explicit about the fact that addrspace(1) is not reserved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226344 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoclang-format all the GC related files (NFC)
Philip Reames [Fri, 16 Jan 2015 23:16:12 +0000 (23:16 +0000)]
clang-format all the GC related files (NFC)

Nothing interesting here...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226342 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld] Track symbol visibility in RuntimeDyld.
Lang Hames [Fri, 16 Jan 2015 23:13:56 +0000 (23:13 +0000)]
[RuntimeDyld] Track symbol visibility in RuntimeDyld.

RuntimeDyld symbol info previously consisted of just a Section/Offset pair. This
patch replaces that pair type with a SymbolInfo class that also tracks symbol
visibility. A new method, RuntimeDyld::getExportedSymbolLoadAddress, is
introduced which only returns a non-zero result for exported symbols. For
non-exported or non-existant symbols this method will return zero. The
RuntimeDyld::getSymbolAddress method retains its current behavior, returning
non-zero results for all symbols regardless of visibility.

No in-tree clients of RuntimeDyld are changed. The newly introduced
functionality will be used by the Orc APIs.

No test case: Since this patch doesn't modify the behavior for any in-tree
clients we don't have a good tool to test this with yet. Once Orc is in we can
use it to write regression tests that test these changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226341 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Clean up floor tests
Matt Arsenault [Fri, 16 Jan 2015 22:11:00 +0000 (22:11 +0000)]
R600: Clean up floor tests

These were using different naming schemes,
not using multiple check prefixes and not using

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226333 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix the Archive::Child::getRawSize() method used by llvm-objdump’s -archive-headers...
Kevin Enderby [Fri, 16 Jan 2015 22:10:36 +0000 (22:10 +0000)]
Fix the Archive::Child::getRawSize() method used by llvm-objdump’s -archive-headers option
and tweak its use in llvm-objdump.  Add back the test case for the -archive-headers option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226332 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Kaleidoscope] Run clang-format over chapter 4 of kaleidoscope.
Lang Hames [Fri, 16 Jan 2015 21:42:07 +0000 (21:42 +0000)]
[Kaleidoscope] Run clang-format over chapter 4 of kaleidoscope.

I forgot to do this for r226308. Thanks to Eric Christopher for the reminder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226327 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Converting halfword to doubleword multiply intrinsics.
Colin LeMahieu [Fri, 16 Jan 2015 21:41:57 +0000 (21:41 +0000)]
[Hexagon] Converting halfword to doubleword multiply intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226326 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Converting accumulating halfword multiply intrinsics to patterns.
Colin LeMahieu [Fri, 16 Jan 2015 21:36:34 +0000 (21:36 +0000)]
[Hexagon] Converting accumulating halfword multiply intrinsics to patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226324 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitio...
Colin LeMahieu [Fri, 16 Jan 2015 20:38:54 +0000 (20:38 +0000)]
[Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions.  Converting halfword multiply intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226318 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[RuntimeDyld] Add 'stub_addr' to comment describing RuntimeDyldChecker's syntax.
Lang Hames [Fri, 16 Jan 2015 20:31:38 +0000 (20:31 +0000)]
[RuntimeDyld] Add 'stub_addr' to comment describing RuntimeDyldChecker's syntax.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226316 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added...
Colin LeMahieu [Fri, 16 Jan 2015 20:16:14 +0000 (20:16 +0000)]
[Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226315 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-readobj: add IMAGE_REL_ARM_MOV32(T) to the enumeration
Saleem Abdulrasool [Fri, 16 Jan 2015 20:16:09 +0000 (20:16 +0000)]
llvm-readobj: add IMAGE_REL_ARM_MOV32(T) to the enumeration

Add an additional based relocation to the enumeration of based relocation names.
The lack of the enumerator value causes issues when inspecting WoA binaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226314 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: fix comment typo in AsmParser
Saleem Abdulrasool [Fri, 16 Jan 2015 20:16:06 +0000 (20:16 +0000)]
X86: fix comment typo in AsmParser

Fix a typo.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226313 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove ownership of GCStrategy objects to LLVMContext
Philip Reames [Fri, 16 Jan 2015 20:07:33 +0000 (20:07 +0000)]
Move ownership of GCStrategy objects to LLVMContext

Note: This change ended up being slightly more controversial than expected.  Chandler has tentatively okayed this for the moment, but I may be revisiting this in the near future after we settle some high level questions.

Rather than have the GCStrategy object owned by the GCModuleInfo - which is an immutable analysis pass used mainly by gc.root - have it be owned by the LLVMContext. This simplifies the ownership logic (i.e. can you have two instances of the same strategy at once?), but more importantly, allows us to access the GCStrategy in the middle end optimizer. To this end, I add an accessor through Function which becomes the canonical way to get at a GCStrategy instance.

In the near future, this will allows me to move some of the checks from http://reviews.llvm.org/D6808 into the Verifier itself, and to introduce optimization legality predicates for some of the recent additions to InstCombine. (These will follow as separate changes.)

Differential Revision: http://reviews.llvm.org/D6811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226311 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Removing old duplicate atomic load/store patterns.
Colin LeMahieu [Fri, 16 Jan 2015 19:53:35 +0000 (19:53 +0000)]
[Hexagon] Removing old duplicate atomic load/store patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226309 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Kaleidoscope] Fix a bug in Chapter 4 of the Kaleidoscope tutorial where repeat
Lang Hames [Fri, 16 Jan 2015 19:44:46 +0000 (19:44 +0000)]
[Kaleidoscope] Fix a bug in Chapter 4 of the Kaleidoscope tutorial where repeat
calls to functions weren't evaluated correctly.

Patch by Charlie Turner. Thanks Charlie!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226308 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove gc.root's findCustomSafePoints mechanism
Philip Reames [Fri, 16 Jan 2015 19:33:28 +0000 (19:33 +0000)]
Remove gc.root's findCustomSafePoints mechanism

Searching all of the existing gc.root implementations I'm aware of (all three of them), there was exactly one use of this mechanism, and that was to implement a performance improvement that should have been applied to the default lowering.

Having this function is requiring a dependency on a CodeGen class (MachineFunction), in a class which is otherwise completely independent of CodeGen. I could solve this differently, but given that I see absolutely no value in preserving this mechanism, I going to just get rid of it.

Note: Tis is the first time I'm intentionally breaking previously supported gc.root functionality. Given 3.6 has branched, I believe this is a good time to do this.

Differential Revision: http://reviews.llvm.org/D7004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226305 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Converting old patterns to new versions using classes.
Colin LeMahieu [Fri, 16 Jan 2015 19:29:59 +0000 (19:29 +0000)]
[Hexagon] Converting old patterns to new versions using classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226304 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCheck commit access
Sumanth Gundapaneni [Fri, 16 Jan 2015 19:23:34 +0000 (19:23 +0000)]
Check commit access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226302 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Add intrinsics for masked aligned FP loads and stores
Adam Nemet [Fri, 16 Jan 2015 18:50:09 +0000 (18:50 +0000)]
[AVX512] Add intrinsics for masked aligned FP loads and stores

Similar to the unaligned cases.

Test was generated with update_llc_test_checks.py.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226296 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Remove trailing whitespaces in this test
Adam Nemet [Fri, 16 Jan 2015 18:50:07 +0000 (18:50 +0000)]
[AVX512] Remove trailing whitespaces in this test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226295 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Allow 16-bits for column info
Duncan P. N. Exon Smith [Fri, 16 Jan 2015 17:33:08 +0000 (17:33 +0000)]
IR: Allow 16-bits for column info

Raise the limit for column information from 8 bits to 16 bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226291 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Cleanup dead code, NFC
Duncan P. N. Exon Smith [Fri, 16 Jan 2015 17:31:29 +0000 (17:31 +0000)]
IR: Cleanup dead code, NFC

Line/column fixups already exist in `MDLocation`.  Delete the duplicated
logic in `DebugLoc`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226290 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Updating call/jump instruction patterns.
Colin LeMahieu [Fri, 16 Jan 2015 17:05:27 +0000 (17:05 +0000)]
[Hexagon] Updating call/jump instruction patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226288 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][DAG] Disable target specific combine on INSERTPS dag nodes at -O0.
Andrea Di Biagio [Fri, 16 Jan 2015 14:55:26 +0000 (14:55 +0000)]
[X86][DAG] Disable target specific combine on INSERTPS dag nodes at -O0.

This patch disables target specific combine on X86ISD::INSERTPS dag nodes
if optlevel is CodeGenOpt::None.

The backend currently implements a target specific combine rule that converts
a vector load used by an INSERTPS dag node into a scalar load plus a
scalar_to_vector. This allows ISel to select a single INSERTPSrm instead of
two instructions (i.e. a vector load plus INSERTPSrr).

However, the existing target combine rule on INSERTPS nodes only works under
the assumption that ISel will always be able to match an INSERTPSrm. This is
not true in general at -O0, since the backend only allows folding a load into
the memory operand of an instruction if the optimization level is not

In the example below:

__m128 test(__m128 a, __m128 *b) {
  __m128 c = _mm_insert_ps(a, *b, 1 << 6);
  return c;

Before this patch, at -O0, the backend would have canonicalized the load to 'b'
into a scalar load plus scalar_to_vector. Later on, ISel would have selected an
INSERTPSrr leaving the insertps mask in an inconsistent state:

  movss 4(%rdi), %xmm1
  insertps  $64, %xmm1, %xmm0 # xmm0 = xmm1[1],xmm0[1,2,3].

With this patch, the backend avoids folding the vector load into the operand of
the INSERTPS. The new codegen at -O0 is:

  movaps (%rdi), %xmm1
  insertps  $64, %xmm1, %xmm0 # %xmm1[1],xmm0[1,2,3].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226277 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Remove a redundant semicolon and add space before curly brackets. NFC.
Toma Tabacu [Fri, 16 Jan 2015 10:45:15 +0000 (10:45 +0000)]
[mips] Remove a redundant semicolon and add space before curly brackets. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226269 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Refactored stack memory folding tests to explicitly force register spilling
Simon Pilgrim [Fri, 16 Jan 2015 09:32:54 +0000 (09:32 +0000)]
[X86] Refactored stack memory folding tests to explicitly force register spilling

The current 'big vectors' stack folded reload testing pattern is very bulky and makes it difficult to test all instructions as big vectors will tend to use only the ymm instruction implementations.

This patch changes the tests to use a nop call that lists explicit xmm registers as sideeffects, with this we can force a partial register spill of the relevant registers and then check that the reload is correctly folded. The asm generated only adds the forced spill, a nop instruction and a couple of extra labels (a fraction of the current approach).

More exhaustive tests will follow shortly, I've added some extra tests (the xmm versions of some of the existing folding tests) as a starting point.

Differential Revision: http://reviews.llvm.org/D6932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226264 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r226242 - Revert Revert Don't create new comdats in CodeGen
Timur Iskhodzhanov [Fri, 16 Jan 2015 08:38:45 +0000 (08:38 +0000)]
Revert r226242 - Revert Revert Don't create new comdats in CodeGen

This breaks AddressSanitizer (ninja check-asan) on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226251 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse report_fatal_error instead of llvm_unreachable, so we don't crash on user input
Filipe Cabecinhas [Fri, 16 Jan 2015 04:54:12 +0000 (04:54 +0000)]
Use report_fatal_error instead of llvm_unreachable, so we don't crash on user input

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226248 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Adjust PatchPoints for ppc64le
Hal Finkel [Fri, 16 Jan 2015 04:40:58 +0000 (04:40 +0000)]
[PowerPC] Adjust PatchPoints for ppc64le

Bill Schmidt pointed out that some adjustments would be needed to properly
support powerpc64le (using the ELF V2 ABI). For one thing, R11 is not available
as a scratch register, so we need to use R12. R12 is also available under ELF
V1, so to maintain consistency, I flipped the order to make R12 the first
scratch register in the array under both ABIs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226247 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix Reassociate handling of constant in presence of undef float
Mehdi Amini [Fri, 16 Jan 2015 03:00:58 +0000 (03:00 +0000)]
Fix Reassociate handling of constant in presence of undef float


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226245 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "Revert Don't create new comdats in CodeGen"
Rafael Espindola [Fri, 16 Jan 2015 02:22:55 +0000 (02:22 +0000)]
Revert "Revert Don't create new comdats in CodeGen"

This reverts commit r226173, adding r226038 back.

No change in this commit, but clang was changed to also produce trivial comdats for
costructors, destructors and vtables when needed.

Original message:

Don't create new comdats in CodeGen.

This patch stops the implicit creation of comdats during codegen.

Clang now sets the comdat explicitly when it is required. With this patch clang and gcc
now produce the same result in pr19848.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226242 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoWork around to get the build bot clang-cmake-armv7-a15-full green by
Kevin Enderby [Fri, 16 Jan 2015 02:08:11 +0000 (02:08 +0000)]
Work around to get the build bot clang-cmake-armv7-a15-full green by
removing the macho-archive-headers.test added with r226228 that it is
failing on for now while I try to figure out what is going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226241 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAnother attempt to fix the build bot clang-cmake-armv7-a15-full failing on
Kevin Enderby [Fri, 16 Jan 2015 01:09:54 +0000 (01:09 +0000)]
Another attempt to fix the build bot clang-cmake-armv7-a15-full failing on
the macho-archive-headers.test added with r226228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226239 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a new pass "inductive range check elimination"
Sanjoy Das [Fri, 16 Jan 2015 01:03:22 +0000 (01:03 +0000)]
Add a new pass "inductive range check elimination"

IRCE eliminates range checks of the form

  0 <= A * I + B < Length

by splitting a loop's iteration space into three segments in a way
that the check is completely redundant in the middle segment.  As an
example, IRCE will convert

  len = < known positive >
  for (i = 0; i < n; i++) {
    if (0 <= i && i < len) {
    } else {


  len = < known positive >
  limit = smin(n, len)
  // no first segment
  for (i = 0; i < limit; i++) {
    if (0 <= i && i < len) { // this check is fully redundant
    } else {
  for (i = limit; i < n; i++) {
    if (0 <= i && i < len) {
    } else {

IRCE can deal with multiple range checks in the same loop (it takes
the intersection of the ranges that will make each of them redundant

Currently IRCE does not do any profitability analysis.  That is a

Please note that the status of this pass is *experimental*, and it is
not part of any default pass pipeline.  Having said that, I will love
to get feedback and general input from people interested in trying
this out.

This pass was originally r226201.  It was reverted because it used C++
features not supported by MSVC 2012.

Differential Revision: http://reviews.llvm.org/D6693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226238 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoThis should fix the build bot clang-cmake-armv7-a15-full failing on
Kevin Enderby [Fri, 16 Jan 2015 00:27:31 +0000 (00:27 +0000)]
This should fix the build bot clang-cmake-armv7-a15-full failing on
the macho-archive-headers.test added with r226228.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226232 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
Matt Arsenault [Thu, 15 Jan 2015 23:58:35 +0000 (23:58 +0000)]
R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226230 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix edge case when Start overflowed in 32 bit mode
Filipe Cabecinhas [Thu, 15 Jan 2015 23:50:44 +0000 (23:50 +0000)]
Fix edge case when Start overflowed in 32 bit mode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226229 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd the option, -archive-headers, used with -macho to print the Mach-O archive header...
Kevin Enderby [Thu, 15 Jan 2015 23:19:11 +0000 (23:19 +0000)]
Add the option, -archive-headers, used with -macho to print the Mach-O archive headers to llvm-objdump.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226228 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix trailing comma with modifiers
Matt Arsenault [Thu, 15 Jan 2015 23:17:03 +0000 (23:17 +0000)]
R600/SI: Fix trailing comma with modifiers

Instructions with 1 operand can still use source modifiers,
so make sure we don't print an extra comma afterwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226226 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Adding new-value store and bit reverse instructions.
Colin LeMahieu [Thu, 15 Jan 2015 23:10:29 +0000 (23:10 +0000)]
[Hexagon] Adding new-value store and bit reverse instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226224 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReport fatal errors instead of segfaulting/asserting on a few invalid accesses while...
Filipe Cabecinhas [Thu, 15 Jan 2015 22:52:38 +0000 (22:52 +0000)]
Report fatal errors instead of segfaulting/asserting on a few invalid accesses while reading MachO files.

Shift an older “invalid file” test to get a consistent naming for these tests.

Bugs found by afl-fuzz

Reviewers: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226219 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Object] Add SF_Exported flag. This flag will be set on all symbols that would
Lang Hames [Thu, 15 Jan 2015 22:33:30 +0000 (22:33 +0000)]
[Object] Add SF_Exported flag. This flag will be set on all symbols that would
be exported from a dylib if their containing object file were linked into one.

No test case: No command line tools query this flag, and there are no Object
unit tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226217 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r226201 (Add a new pass "inductive range check elimination")
Sanjoy Das [Thu, 15 Jan 2015 22:18:10 +0000 (22:18 +0000)]
Revert r226201 (Add a new pass "inductive range check elimination")

The change used C++11 features not supported by MSVC 2012.  I will fix
the change to use things supported MSVC 2012 and recommit shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226216 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInductiveRangeCheckElimination: Remove extra ';'
David Majnemer [Thu, 15 Jan 2015 21:55:16 +0000 (21:55 +0000)]
InductiveRangeCheckElimination: Remove extra ';'

This silences a GCC warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226215 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFixing pedantic build warnings.
Andrew Kaylor [Thu, 15 Jan 2015 21:50:53 +0000 (21:50 +0000)]
Fixing pedantic build warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226214 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simpl...
Colin LeMahieu [Thu, 15 Jan 2015 21:35:49 +0000 (21:35 +0000)]
[Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226210 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Loosen ELFv1 PPC64 func descriptor loads for indirect calls
Hal Finkel [Thu, 15 Jan 2015 21:17:34 +0000 (21:17 +0000)]
[PowerPC] Loosen ELFv1 PPC64 func descriptor loads for indirect calls

Function pointers under PPC64 ELFv1 (which is used on PPC64/Linux on the
POWER7, A2 and earlier cores) are really pointers to a function descriptor, a
structure with three pointers: the actual pointer to the code to which to jump,
the pointer to the TOC needed by the callee, and an environment pointer. We
used to chain these loads, and make them opaque to the rest of the optimizer,
so that they'd always occur directly before the call. This is not necessary,
and in fact, highly suboptimal on embedded cores. Once the function pointer is
known, the loads can be performed ahead of time; in fact, they can be hoisted
out of loops.

Now these function descriptors are almost always generated by the linker, and
thus the contents of the descriptors are invariant. As a result, by default,
we'll mark the associated loads as invariant (allowing them to be hoisted out
of loops). I've added a target feature to turn this off, however, just in case
someone needs that option (constructing an on-stack descriptor, casting it to a
function pointer, and then calling it cannot be well-defined C/C++ code, but I
can imagine some JIT-compilation system doing so).

Consider this simple test:
  $ cat call.c

  typedef void (*fp)();
  void bar(fp x) {
    for (int i = 0; i < 1600000000; ++i)

  $ cat main.c

  typedef void (*fp)();
  void bar(fp x);
  void foo() {}
  int main() {

On the PPC A2 (the BG/Q supercomputer), marking the function-descriptor loads
as invariant brings the execution time down to ~8 seconds from ~32 seconds with
the loads in the loop.

The difference on the POWER7 is smaller. Compiling with:

  gcc -std=c99 -O3 -mcpu=native call.c main.c : ~6 seconds [this is 4.8.2]

  clang -O3 -mcpu=native call.c main.c : ~5.3 seconds

  clang -O3 -mcpu=native call.c main.c -mno-invariant-function-descriptors : ~4 seconds
  (looks like we'd benefit from additional loop unrolling here, as a first
   guess, because this is faster with the extra loads)

The -mno-invariant-function-descriptors will be added to Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226207 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Updating indexed load-extend patterns and changing test to new expected...
Colin LeMahieu [Thu, 15 Jan 2015 21:07:52 +0000 (21:07 +0000)]
[Hexagon] Updating indexed load-extend patterns and changing test to new expected output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226206 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a new pass "inductive range check elimination"
Sanjoy Das [Thu, 15 Jan 2015 20:45:46 +0000 (20:45 +0000)]
Add a new pass "inductive range check elimination"

IRCE eliminates range checks of the form

  0 <= A * I + B < Length

by splitting a loop's iteration space into three segments in a way
that the check is completely redundant in the middle segment.  As an
example, IRCE will convert

  len = < known positive >
  for (i = 0; i < n; i++) {
    if (0 <= i && i < len) {
    } else {


  len = < known positive >
  limit = smin(n, len)
  // no first segment
  for (i = 0; i < limit; i++) {
    if (0 <= i && i < len) { // this check is fully redundant
    } else {
  for (i = limit; i < n; i++) {
    if (0 <= i && i < len) {
    } else {

IRCE can deal with multiple range checks in the same loop (it takes
the intersection of the ranges that will make each of them redundant

Currently IRCE does not do any profitability analysis.  That is a

Please note that the status of this pass is *experimental*, and it is
not part of any default pass pipeline.  Having said that, I will love
to get feedback and general input from people interested in trying
this out.

Differential Revision: http://reviews.llvm.org/D6693

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226201 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "r226086 - Revert "r226071 - [RegisterCoalescer] Remove copies to reserved...
Hal Finkel [Thu, 15 Jan 2015 20:32:09 +0000 (20:32 +0000)]
Revert "r226086 - Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers""

Reapply r226071 with fixes. Two fixes:

 1. We need to manually remove the old and create the new 'deaf defs'
    associated with physical register definitions when we move the definition of
    the physical register from the copy point to the point of the original vreg def.

    This problem was picked up by the machinstr verifier, and could trigger a
    verification failure on test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll, so I've
    turned on the verifier in the tests.

 2. When moving the def point of the phys reg up, we need to make sure that it
    is neither defined nor read in between the two instructions. We don't, however,
    extend the live ranges of phys reg defs to cover uses, so just checking for
    live-range overlap between the pair interval and the phys reg aliases won't
    pick up reads. As a result, we manually iterate over the range and check for

    A test soon to be committed to the PowerPC backend will test this change.

Original commit message:

[RegisterCoalescer] Remove copies to reserved registers

This allows the RegisterCoalescer to join "non-flipped" range pairs with a
physical destination register -- which allows the RegisterCoalescer to remove
copies like this:

<vreg> = something (maybe a load, for example)
... (things that don't use PHYSREG)

(with all of the restrictions normally applied by the RegisterCoalescer: having
compatible register classes, etc. )

Previously, the RegisterCoalescer handled only the opposite case (copying
*from* a physical register). I don't handle the problem fully here, but try to
get the common case where there is only one use of <vreg> (the COPY).

An upcoming commit to the PowerPC backend will make this pattern much more
common on PPC64/ELF systems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226200 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoStyle cleanup of old gc.root lowering code
Philip Reames [Thu, 15 Jan 2015 19:49:25 +0000 (19:49 +0000)]
Style cleanup of old gc.root lowering code

Use static functions for helpers rather than static member functions.  a) this changes the linking (minor at best), and b) this makes it obvious no object state is involved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226198 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Improve fpext / fptrunc test coverage
Matt Arsenault [Thu, 15 Jan 2015 19:39:42 +0000 (19:39 +0000)]
R600/SI: Improve fpext / fptrunc test coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226197 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoclang-format GCStrategy.cpp & GCRootLowering.cpp (NFC)
Philip Reames [Thu, 15 Jan 2015 19:39:17 +0000 (19:39 +0000)]
clang-format GCStrategy.cpp & GCRootLowering.cpp (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226196 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSplit GCStrategy.cpp into two files (NFC)
Philip Reames [Thu, 15 Jan 2015 19:29:42 +0000 (19:29 +0000)]
Split GCStrategy.cpp into two files (NFC)

This preparation for an update to http://reviews.llvm.org/D6811.  GCStrategy.cpp will hopefully be moving into IR/, where as the lowering logic needs to stay in CodeGen/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226195 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references...
Colin LeMahieu [Thu, 15 Jan 2015 19:28:32 +0000 (19:28 +0000)]
[Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226194 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Unify VOP2 instructions which are VOP3-only on VI
Marek Olsak [Thu, 15 Jan 2015 18:43:06 +0000 (18:43 +0000)]
R600/SI: Unify VOP2 instructions which are VOP3-only on VI

This removes some duplicated classes and definitions.

These instructions are defined:
  _e32 // pseudo
  _e64 // pseudo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226191 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
Marek Olsak [Thu, 15 Jan 2015 18:43:01 +0000 (18:43 +0000)]
R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226190 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
Marek Olsak [Thu, 15 Jan 2015 18:42:55 +0000 (18:42 +0000)]
R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI

These are VOP3-only on VI.

The new multiclass doesn't define VOP3 versions of VOP2 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226189 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Don't shrink instructions whose e32 encoding doesn't exist
Marek Olsak [Thu, 15 Jan 2015 18:42:51 +0000 (18:42 +0000)]
R600/SI: Don't shrink instructions whose e32 encoding doesn't exist

v2: modify hasVALU32BitEncoding instead
v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both
      hasVALU32BitEncoding and AMDGPUMCInstLower::lower
    - report an error if a pseudo can't be lowered

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226188 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add common class VOPAnyCommon
Marek Olsak [Thu, 15 Jan 2015 18:42:44 +0000 (18:42 +0000)]
R600/SI: Add common class VOPAnyCommon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226187 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Don't select SI-only VOP3 opcodes on VI
Marek Olsak [Thu, 15 Jan 2015 18:42:40 +0000 (18:42 +0000)]
R600/SI: Don't select SI-only VOP3 opcodes on VI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226186 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Adding vmux instruction. Removing old transfer instructions and updating...
Colin LeMahieu [Thu, 15 Jan 2015 18:16:00 +0000 (18:16 +0000)]
[Hexagon] Adding vmux instruction.  Removing old transfer instructions and updating references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226184 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agostatepoint tests: use statepoint-example gc
Ramkumar Ramachandra [Thu, 15 Jan 2015 18:10:44 +0000 (18:10 +0000)]
statepoint tests: use statepoint-example gc

Mechanical conversion of statepoint tests to use the example-statepoint

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226183 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSupport @PLT loads on 32bit x86.
Joerg Sonnenberger [Thu, 15 Jan 2015 17:59:02 +0000 (17:59 +0000)]
Support @PLT loads on 32bit x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226182 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Deleting old float comparison instruction and updating references to new...
Colin LeMahieu [Thu, 15 Jan 2015 17:28:14 +0000 (17:28 +0000)]
[Hexagon] Deleting old float comparison instruction and updating references to new ones.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226179 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Replacing old fadd/fsub instructions and updating references.
Colin LeMahieu [Thu, 15 Jan 2015 16:30:07 +0000 (16:30 +0000)]
[Hexagon] Replacing old fadd/fsub instructions and updating references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226176 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert Don't create new comdats in CodeGen
Timur Iskhodzhanov [Thu, 15 Jan 2015 16:14:34 +0000 (16:14 +0000)]
Revert Don't create new comdats in CodeGen

It breaks AddressSanitizer on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226173 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Fix a typo in the compare patterns for MIPS32r6/MIPS64r6.
Daniel Sanders [Thu, 15 Jan 2015 15:41:03 +0000 (15:41 +0000)]
[mips] Fix a typo in the compare patterns for MIPS32r6/MIPS64r6.

Summary: The patterns intended for the SETLE node were actually matching the SETLT node.

Reviewers: atanasyan, sstankovic, vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6997

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226171 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix the C-API MCJIT test for 32-bit big endian machines.
Vasileios Kalintiris [Thu, 15 Jan 2015 15:36:04 +0000 (15:36 +0000)]
Fix the C-API MCJIT test for 32-bit big endian machines.

Avoid using unions for storing the return value from
LLVMGetGlobalValueAddress() and LLVMGetFunctionAddress() and accessing it as
a pointer through another pointer member. This causes problems on 32-bit big
endian machines since the pointer gets the higher part of the return value of
the aforementioned functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226170 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd disassembler tests for mips64r6 platform. There are no functional changes.
Vladimir Medic [Thu, 15 Jan 2015 14:18:12 +0000 (14:18 +0000)]
Add disassembler tests for mips64r6 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226166 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd disassembler tests for mips32r6 platform. There are no functional changes.
Vladimir Medic [Thu, 15 Jan 2015 14:11:38 +0000 (14:11 +0000)]
Add disassembler tests for mips32r6 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226165 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd disassembler tests for mips64r2 platform. There are no functional changes.
Vladimir Medic [Thu, 15 Jan 2015 14:06:34 +0000 (14:06 +0000)]
Add disassembler tests for mips64r2 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226164 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix SelectionDAG -view-*-dags filtering
Mehdi Amini [Thu, 15 Jan 2015 12:03:32 +0000 (12:03 +0000)]
Fix SelectionDAG -view-*-dags filtering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226163 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReplace size method call of containers to empty method where appropriate
Alexander Kornienko [Thu, 15 Jan 2015 11:41:30 +0000 (11:41 +0000)]
Replace size method call of containers to empty method where appropriate

This patch was generated by a clang tidy checker that is being open sourced.
The documentation of that checker is the following:

/// The emptiness of a container should be checked using the empty method
/// instead of the size method. It is not guaranteed that size is a
/// constant-time function, and it is generally more efficient and also shows
/// clearer intent to use empty. Furthermore some containers may implement the
/// empty method but not implement the size method. Using empty whenever
/// possible makes it easier to switch to another container in the future.

Patch by Gábor Horváth!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226161 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PM] Port TargetLibraryInfo to the new pass manager, provided by the
Chandler Carruth [Thu, 15 Jan 2015 11:39:46 +0000 (11:39 +0000)]
[PM] Port TargetLibraryInfo to the new pass manager, provided by the
TargetLibraryAnalysis pass.

There are actually no direct tests of this already in the tree. I've
added the most basic test that the pass manager bits themselves work,
and the TLI object produced will be tested by an upcoming patches as
they port passes which rely on TLI.

This is starting to point out the awkwardness of the invalidate API --
it seems poorly fitting on the *result* object. I suspect I will change
it to live on the analysis instead, but that's not for this change, and
I'd rather have a few more passes ported in order to have more
experience with how this plays out.

I believe there is only one more analysis required in order to start
porting instcombine. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226160 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PM] Separate the TargetLibraryInfo object from the immutable pass.
Chandler Carruth [Thu, 15 Jan 2015 10:41:28 +0000 (10:41 +0000)]
[PM] Separate the TargetLibraryInfo object from the immutable pass.

The pass is really just a means of accessing a cached instance of the
TargetLibraryInfo object, and this way we can re-use that object for the
new pass manager as its result.

Lots of delta, but nothing interesting happening here. This is the
common pattern that is developing to allow analyses to live in both the
old and new pass manager -- a wrapper pass in the old pass manager
emulates the separation intrinsic to the new pass manager between the
result and pass for analyses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226157 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoHide some redundant AVX512 instructions from the asm parser, but force them to show...
Craig Topper [Thu, 15 Jan 2015 09:37:15 +0000 (09:37 +0000)]
Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226155 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd disassembler tests for mips64 platform. There are no functional changes.
Vladimir Medic [Thu, 15 Jan 2015 08:50:20 +0000 (08:50 +0000)]
Add disassembler tests for mips64 platform. There are no functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226151 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSimplifyIndVar: Remove unused variable
David Majnemer [Thu, 15 Jan 2015 07:11:23 +0000 (07:11 +0000)]
SimplifyIndVar: Remove unused variable

OtherOperandIdx is not used anymore, remove it to silence warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226138 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate libdeps since TLI was moved from Target to Analysis in r226078.
NAKAMURA Takumi [Thu, 15 Jan 2015 05:21:00 +0000 (05:21 +0000)]
Update libdeps since TLI was moved from Target to Analysis in r226078.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226126 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReorder.
NAKAMURA Takumi [Thu, 15 Jan 2015 05:20:46 +0000 (05:20 +0000)]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226125 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoutils/release/tag.sh: fix -revision vs. -rc check
Hans Wennborg [Thu, 15 Jan 2015 04:36:20 +0000 (04:36 +0000)]
utils/release/tag.sh: fix -revision vs. -rc check

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226124 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PM] Clean up the TLI doxygen comments prior to refactoring this code
Chandler Carruth [Thu, 15 Jan 2015 03:51:04 +0000 (03:51 +0000)]
[PM] Clean up the TLI doxygen comments prior to refactoring this code
for the new pass manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226089 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"
Hal Finkel [Thu, 15 Jan 2015 03:08:59 +0000 (03:08 +0000)]
Revert "r226071 - [RegisterCoalescer] Remove copies to reserved registers"

Reverting this while I investigate some bad behavior this is causing. As a
possibly-related issue, adding -verify-machineinstrs to one of the test cases
now fails because of this change:

  llc test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll -march=x86-64 -o - -verify-machineinstrs

*** Bad machine code: No instruction at def index ***
- function:    foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange:   [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0)  0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register:    %DS
Valno #3 is defined at 624r

*** Bad machine code: Live segment doesn't end at a valid instruction ***
- function:    foo
- basic block: BB#0 return (0x10007e21f10) [0B;736B)
- liverange:   [128r,128d:9)[160r,160d:8)[176r,176d:7)[336r,336d:6)[464r,464d:5)[480r,480d:4)[624r,624d:3)[752r,752d:2)[768r,768d:1)[78
4r,784d:0)  0@784r 1@768r 2@752r 3@624r 4@480r 5@464r 6@336r 7@176r 8@160r 9@128r
- register:    %DS
LLVM ERROR: Found 2 machine code errors.

where 624r corresponds exactly to the interval combining change:

624B    %RSP<def> = COPY %vreg16; GR64:%vreg16
        Considering merging %vreg16 with %RSP
                RHS = %vreg16 [608r,624r:0)  0@608r
                updated: 608B   %RSP<def> = MOV64rm <fi#3>, 1, %noreg, 0, %noreg; mem:LD8[%saved_stack.1]
        Success: %vreg16 -> %RSP
        Result = %RSP

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226086 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSwitch this header file to not hard-code Windows line endings.
Chandler Carruth [Thu, 15 Jan 2015 02:21:56 +0000 (02:21 +0000)]
Switch this header file to not hard-code Windows line endings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226081 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PM] Move TargetLibraryInfo into the Analysis library.
Chandler Carruth [Thu, 15 Jan 2015 02:16:27 +0000 (02:16 +0000)]
[PM] Move TargetLibraryInfo into the Analysis library.

While the term "Target" is in the name, it doesn't really have to do
with the LLVM Target library -- this isn't an abstraction which LLVM
targets generally need to implement or extend. It has much more to do
with modeling the various runtime libraries on different OSes and with
different runtime environments. The "target" in this sense is the more
general sense of a target of cross compilation.

This is in preparation for porting this analysis to the new pass

No functionality changed, and updates inbound for Clang and Polly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226078 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoWin64Exception.cpp: Try to fix crash for x64 EH. "Per" might be null there.
NAKAMURA Takumi [Thu, 15 Jan 2015 02:15:21 +0000 (02:15 +0000)]
Win64Exception.cpp: Try to fix crash for x64 EH. "Per" might be null there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226077 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix PR22222
Sanjoy Das [Thu, 15 Jan 2015 01:46:09 +0000 (01:46 +0000)]
Fix PR22222

The bug was introduced in r225282. r225282 assumed that sub X, Y is
the same as add X, -Y. This is not correct if we are going to upgrade
the sub to sub nuw. This change fixes the issue by making the
optimization ignore sub instructions.

Differential Revision: http://reviews.llvm.org/D6979

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226075 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[TableGen] Add support for negative immediates to AsmMatcherEmitter
Hal Finkel [Thu, 15 Jan 2015 01:33:00 +0000 (01:33 +0000)]
[TableGen] Add support for negative immediates to AsmMatcherEmitter

This adds support for creating an InstAlias with a negative immediate, i.e.:

  def NOT : InstAlias<"not $dst, $src", (XORI GR32:$dst, GR32:$src, -1)>;

by resolving this problem:

RISCVGenAsmMatcher.inc:95:11: error: expected '= constant-expression' or end of enumerator definition

Patch by Jordy Potman, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226073 91177308-0d34-0410-b5e6-96231b3b80d8