oota-llvm.git
7 years agoBitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)
Mehdi Amini [Wed, 9 Sep 2015 20:08:39 +0000 (20:08 +0000)]
Bitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247178 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x...
Renato Golin [Wed, 9 Sep 2015 19:44:40 +0000 (19:44 +0000)]
Revert "AVX512: Implemented encoding and intrinsics for   vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."

This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247177 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoallow unpredictable metadata on switch statements
Sanjay Patel [Wed, 9 Sep 2015 18:38:30 +0000 (18:38 +0000)]
allow unpredictable metadata on switch statements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247174 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSave LaneMask with livein registers
Matthias Braun [Wed, 9 Sep 2015 18:08:03 +0000 (18:08 +0000)]
Save LaneMask with livein registers

With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only keeps registers in the live-in list and therefore
enumerated all subregisters affected by the lanemask. This turned out to
be too conservative as the subregister may also cover additional parts
of the lanemask which are not live. Expressing a given lanemask by
enumerating a minimum set of subregisters is computationally expensive
so the best solution is to simply change the live-in list to store the
lanemasks as well. This will reduce memory usage for targets using
subregister liveness and slightly increase it for other targets

Differential Revision: http://reviews.llvm.org/D12442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247171 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVirtRegMap: Improve addMBBLiveIns() using SlotIndex::MBBIndexIterator; NFC
Matthias Braun [Wed, 9 Sep 2015 18:07:54 +0000 (18:07 +0000)]
VirtRegMap: Improve addMBBLiveIns() using SlotIndex::MBBIndexIterator; NFC

Now that we have an explicit iterator over the idx2MBBMap in SlotIndices
we can use the fact that segments and the idx2MBBMap is sorted by
SlotIndex position so can advance both simultaneously instead of
starting from the beginning for each segment.

This complicates the code for the subregister case somewhat but should
be more efficient and has the advantage that we get the final lanemask
for each block immediately which will be important for a subsequent
change.

Removes the now unused SlotIndexes::findMBBLiveIns function.

Differential Revision: http://reviews.llvm.org/D12443

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247170 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
Chandler Carruth [Wed, 9 Sep 2015 17:55:00 +0000 (17:55 +0000)]
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.

This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:

- FunctionAAResults is a type-erasing alias analysis results aggregation
  interface to walk a single query across a range of results from
  different alias analyses. Currently this is function-specific as we
  always assume that aliasing queries are *within* a function.

- AAResultBase is a CRTP utility providing stub implementations of
  various parts of the alias analysis result concept, notably in several
  cases in terms of other more general parts of the interface. This can
  be used to implement only a narrow part of the interface rather than
  the entire interface. This isn't really ideal, this logic should be
  hoisted into FunctionAAResults as currently it will cause
  a significant amount of redundant work, but it faithfully models the
  behavior of the prior infrastructure.

- All the alias analysis passes are ported to be wrapper passes for the
  legacy PM and new-style analysis passes for the new PM with a shared
  result object. In some cases (most notably CFL), this is an extremely
  naive approach that we should revisit when we can specialize for the
  new pass manager.

- BasicAA has been restructured to reflect that it is much more
  fundamentally a function analysis because it uses dominator trees and
  loop info that need to be constructed for each function.

All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.

The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.

This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.

Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.

One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.

Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.

Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.

Differential Revision: http://reviews.llvm.org/D12080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247167 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineVerifier: Check that SlotIndex MBBIndexList is sorted.
Matthias Braun [Wed, 9 Sep 2015 17:49:46 +0000 (17:49 +0000)]
MachineVerifier: Check that SlotIndex MBBIndexList is sorted.

This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247166 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Extract full 64-bit subregister and use subregs
Matt Arsenault [Wed, 9 Sep 2015 17:03:29 +0000 (17:03 +0000)]
AMDGPU: Extract full 64-bit subregister and use subregs

Instead of extracting both 32-bit components from the 128-bit
register. This produces fewer copies and is easier for
the copy peephole optimizer to understand and see the actual uses
as extracts from a reg_sequence.

This avoids needing to handle subregister composing in the
PeepholeOptimizer's ValueTracker for this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247162 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Remove unused multiclass argument
Matt Arsenault [Wed, 9 Sep 2015 17:03:18 +0000 (17:03 +0000)]
AMDGPU: Remove unused multiclass argument

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247161 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agollvm-config: Add --build-system option
Tom Stellard [Wed, 9 Sep 2015 16:39:30 +0000 (16:39 +0000)]
llvm-config: Add --build-system option

Summary:
This can be used for distinguishing between cmake and autoconf builds.
Users may need this in order to handle inconsistencies between the
outputs of the two build systems.

Reviewers: echristo, chandlerc, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11838

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247159 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Implement calls with void return types.
Dan Gohman [Wed, 9 Sep 2015 16:13:47 +0000 (16:13 +0000)]
[WebAssembly] Implement calls with void return types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247158 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fold operands through REG_SEQUENCE instructions
Tom Stellard [Wed, 9 Sep 2015 15:43:26 +0000 (15:43 +0000)]
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions

Summary:
This helps mostly when we use add instructions for address calculations
that contain immediates.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247157 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CostModel][AArch64] Remove amortization factor for some of the vector select instruc...
Silviu Baranga [Wed, 9 Sep 2015 15:35:02 +0000 (15:35 +0000)]
[CostModel][AArch64] Remove amortization factor for some of the vector select instructions

Summary:
We are not scalarizing the wide selects in codegen for i16 and i32 and
therefore we can remove the amortization factor. We still have issues
with i64 vectors in codegen though.

Reviewers: mcrosier

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247156 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodon't repeat function names in comments; NFC
Sanjay Patel [Wed, 9 Sep 2015 15:24:36 +0000 (15:24 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247154 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Tidy up some unneeded newline characters.
Dan Gohman [Wed, 9 Sep 2015 15:13:36 +0000 (15:13 +0000)]
[WebAssembly] Tidy up some unneeded newline characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247152 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Flag recursive cmake invocations for cross-compile
Joseph Tremoulet [Wed, 9 Sep 2015 14:57:06 +0000 (14:57 +0000)]
[CMake] Flag recursive cmake invocations for cross-compile

Summary:
Cross-compilation uses recursive cmake invocations to build native host
tools.  These recursive invocations only forward a fixed set of
variables/options, since the native environment is generally the default.
This change adds -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE to the recursive
cmake invocations, so that cmake files can distinguish these recursive
invocations from top-level ones, which can explain why expected options
are unset.

LLILC will use this to avoid trying to generate its build rules in the
crosscompile native host target (where it is not needed), which would fail
if attempted because LLILC requires a cmake variable passed on the command
line, which is not forwarded in the recursive invocation.

Reviewers: rnk, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247151 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofunction names start with a lower case letter; NFC
Sanjay Patel [Wed, 9 Sep 2015 14:54:29 +0000 (14:54 +0000)]
function names start with a lower case letter; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247150 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX512: Implemented encoding and intrinsics for
Igor Breger [Wed, 9 Sep 2015 14:35:09 +0000 (14:35 +0000)]
AVX512: Implemented encoding and intrinsics for
  vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247149 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodon't repeat function names in comments; NFC
Sanjay Patel [Wed, 9 Sep 2015 14:34:26 +0000 (14:34 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247148 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instr...
Zoran Jovanovic [Wed, 9 Sep 2015 13:55:45 +0000 (13:55 +0000)]
[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247146 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix PR 24633 - Handle undef values when parsing standalone constants.
Alex Lorenz [Wed, 9 Sep 2015 13:44:33 +0000 (13:44 +0000)]
Fix PR 24633 - Handle undef values when parsing standalone constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247145 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename ExitCount to BackedgeTakenCount, because that's what it is.
James Molloy [Wed, 9 Sep 2015 12:51:10 +0000 (12:51 +0000)]
Rename ExitCount to BackedgeTakenCount, because that's what it is.

We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247140 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDelay predication of stores until near the end of vector code generation
James Molloy [Wed, 9 Sep 2015 12:51:06 +0000 (12:51 +0000)]
Delay predication of stores until near the end of vector code generation

Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions.

Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247139 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Alexandros Lamprineas [Wed, 9 Sep 2015 11:20:48 +0000 (11:20 +0000)]
LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Removed "cortex-r5f" and "cortex-m4f" from Target Parser, sinced they are
unknown cpu names for llvm and clang. Also updated default FPUs for R5 and M4
accordingly.

Differential Revision: http://reviews.llvm.org/D12692

Change-Id: Ib81c7216521a361d8ee1296e4b6a2aa00bd479c5

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247136 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix vector splitting for extract_vector_elt and vector elements of <8-bits.
Daniel Sanders [Wed, 9 Sep 2015 09:53:20 +0000 (09:53 +0000)]
Fix vector splitting for extract_vector_elt and vector elements of <8-bits.

Summary:
One of the vector splitting paths for extract_vector_elt tries to lower:
    define i1 @via_stack_bug(i8 signext %idx) {
      %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
      ret i1 %1
    }
to:
    define i1 @via_stack_bug(i8 signext %idx) {
      %base = alloca <2 x i1>
      store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base
      %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx
      %3 = load i1, i1* %2
      ret i1 %3
    }
However, the elements of <2 x i1> are not byte-addressible. The result of this
is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies
to '%base + %idx * 0', and then simply '%base' causing all values of %idx to
extract element zero.

This commit fixes this by promoting the vector elements of <8-bits to i8 before
splitting the vector.

This fixes a number of test failures in pocl.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247128 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a typo I spotted when hacking on SROA. Somewhat alarming that
Chandler Carruth [Wed, 9 Sep 2015 09:46:16 +0000 (09:46 +0000)]
Fix a typo I spotted when hacking on SROA. Somewhat alarming that
nothing broke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247127 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement CACHEE and PREFE instructions
Zoran Jovanovic [Wed, 9 Sep 2015 09:10:46 +0000 (09:10 +0000)]
[mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247125 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix not encoding src2 of VOP3b instructions
Matt Arsenault [Wed, 9 Sep 2015 08:39:49 +0000 (08:39 +0000)]
AMDGPU: Fix not encoding src2 of VOP3b instructions

Broken by r247074. Should include an assembler test,
but the assembler is currently broken for VOP3b apparently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247123 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.
Sanjoy Das [Wed, 9 Sep 2015 03:47:18 +0000 (03:47 +0000)]
[IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.

IRCE was just using INITIALIZE_PASS(), which is incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247122 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.
Lang Hames [Wed, 9 Sep 2015 03:14:29 +0000 (03:14 +0000)]
[RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247119 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Fix lowering of calls with more than one argument.
Dan Gohman [Wed, 9 Sep 2015 01:52:45 +0000 (01:52 +0000)]
[WebAssembly] Fix lowering of calls with more than one argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247118 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSelectionDAG: Support Expand of f16 extloads
Matt Arsenault [Wed, 9 Sep 2015 01:12:27 +0000 (01:12 +0000)]
SelectionDAG: Support Expand of f16 extloads

Currently this hits an assert that extload should
always be supported, which assumes integer extloads.

This moves a hack out of SI's argument lowering and
is covered by existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247113 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg
Dan Gohman [Wed, 9 Sep 2015 00:52:47 +0000 (00:52 +0000)]
[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247110 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typos / grammar
Matt Arsenault [Wed, 9 Sep 2015 00:38:33 +0000 (00:38 +0000)]
Fix typos / grammar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247109 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"
Duncan P. N. Exon Smith [Wed, 9 Sep 2015 00:37:52 +0000 (00:37 +0000)]
Revert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"

This reverts commit r247107.  Turns out clang calls these functions
directly, and `ArrayRef<T>` doesn't have a working implicit conversion
from `SmallVector<T>`.

http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental_build/14247

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247108 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC
Duncan P. N. Exon Smith [Wed, 9 Sep 2015 00:34:25 +0000 (00:34 +0000)]
Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC

Change `EmitRecordWithAbbrev()` and friends to take an `ArrayRef<T>`
instead of requiring a `SmallVectorImpl<T>`.  No functionality change
intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247107 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-readobj] MachO -- dump LinkerOptions load command.
Davide Italiano [Wed, 9 Sep 2015 00:21:18 +0000 (00:21 +0000)]
[llvm-readobj] MachO -- dump LinkerOptions load command.

Example output:

Linker Options {
  Size: 32
  Count: 2
  Strings [
    Value: -framework
    Value: Cocoa
  ]
}

There were only two tests using this -- so I converted them as part of
this commit rather than separately.

Differential Revision:  http://reviews.llvm.org/D12702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247106 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Avoid creating MBBs for LLVM BBs that cannot contain code
Reid Kleckner [Tue, 8 Sep 2015 23:28:38 +0000 (23:28 +0000)]
[WinEH] Avoid creating MBBs for LLVM BBs that cannot contain code

Typically these are catchpads, which hold data used to decide whether to
catch the exception or continue unwinding. We also shouldn't create MBBs
for catchendpads, cleanupendpads, or terminatepads, since no real code
can live in them.

This fixes a problem where MI passes (like the register allocator) would
try to put code into catchpad blocks, which are not executed by the
runtime. In the new world, blocks ending in invokes now have many
possible successors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247102 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-apply r247080 with order of evaluation fix.
Peter Collingbourne [Tue, 8 Sep 2015 22:49:35 +0000 (22:49 +0000)]
Re-apply r247080 with order of evaluation fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247095 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Emit prologues and epilogues for funclets
Reid Kleckner [Tue, 8 Sep 2015 22:44:41 +0000 (22:44 +0000)]
[WinEH] Emit prologues and epilogues for funclets

Summary:
32-bit funclets have short prologues that allocate enough stack for the
largest call in the whole function. The runtime saves CSRs for the
funclet. It doesn't restore CSRs after we finally transfer control back
to the parent funciton via a CATCHRET, but that's a separate issue.
32-bit funclets also have to adjust the incoming EBP value, which is
what llvm.x86.seh.recoverframe does in the old model.

64-bit funclets need to spill CSRs as normal. For simplicity, this just
spills the same set of CSRs as the parent function, rather than trying
to compute different CSR sets for the parent function and each funclet.
64-bit funclets also allocate enough stack space for the largest
outgoing call frame, like 32-bit.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247092 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r247080, "LowerBitSets: Extend pass to support functions as bitset
Peter Collingbourne [Tue, 8 Sep 2015 22:33:23 +0000 (22:33 +0000)]
Revert r247080, "LowerBitSets: Extend pass to support functions as bitset
members." as it causes test failures on a number of bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247088 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Bitcode] Add compatibility tests for new instructions
Vedant Kumar [Tue, 8 Sep 2015 22:33:23 +0000 (22:33 +0000)]
[Bitcode] Add compatibility tests for new instructions

Adds basic compatibility tests for the following instructions:

  catchpad, catchendpad, cleanuppad, cleanupendpad, terminatepad,
  cleanupret, catchret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247087 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Fix typo in catchret example
Vedant Kumar [Tue, 8 Sep 2015 22:28:38 +0000 (22:28 +0000)]
[docs] Fix typo in catchret example

An example usage of catchret omitted the "to" in "to label" in
ExceptionHandling.rst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the PPC CTR Loop pass to look for calls to the intrinsics that
Eric Christopher [Tue, 8 Sep 2015 22:14:58 +0000 (22:14 +0000)]
Fix the PPC CTR Loop pass to look for calls to the intrinsics that
read CTR and count them as reading the CTR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247083 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerBitSets: Extend pass to support functions as bitset members.
Peter Collingbourne [Tue, 8 Sep 2015 21:57:45 +0000 (21:57 +0000)]
LowerBitSets: Extend pass to support functions as bitset members.

This change extends the bitset lowering pass to support bitsets that may
contain either functions or global variables. A function bitset is lowered to
a jump table that is laid out before one of the functions in the bitset.

Also add support for non-string bitset identifier names. This allows for
distinct metadata nodes to stand in for names with internal linkage,
as done in D11857.

Differential Revision: http://reviews.llvm.org/D11856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247080 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer]Add a test for defeating a hash sum.
Ivan Krasin [Tue, 8 Sep 2015 21:22:52 +0000 (21:22 +0000)]
[libFuzzer]Add a test for defeating a hash sum.

Summary:
Add a test for a data followed by 4-byte hash value.
I use a slightly modified Jenkins hash function,
as described in https://en.wikipedia.org/wiki/Jenkins_hash_function

The modification is to ensure that hash(zeros) != 0.

Reviewers: kcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247076 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix input vcc operand for VOP2b instructions
Matt Arsenault [Tue, 8 Sep 2015 21:15:00 +0000 (21:15 +0000)]
AMDGPU/SI: Fix input vcc operand for VOP2b instructions

Adds vcc to output string input for e32. Allows option
of using e64 encoding with assembler.

Also fixes these instructions not implicitly reading exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247074 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Added run NVVMReflect pass to NVPTX back-end.
Artem Belevich [Tue, 8 Sep 2015 21:04:55 +0000 (21:04 +0000)]
[NVPTX] Added run NVVMReflect pass to NVPTX back-end.

The pass is needed to remove __nvvm_reflect calls when we link in
libdevice bitcode that comes with CUDA.

Differential Revision: http://reviews.llvm.org/D11663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247072 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix comments and RUN line in x86-64 stdarg test leftover from last commit
Derek Schuff [Tue, 8 Sep 2015 20:58:41 +0000 (20:58 +0000)]
Fix comments and RUN line in x86-64 stdarg test leftover from last commit

From http://reviews.llvm.org/D12346

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247070 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes a bug in how struct va_list is initialized in x32
Derek Schuff [Tue, 8 Sep 2015 20:51:31 +0000 (20:51 +0000)]
x32. Fixes a bug in how struct va_list is initialized in x32

Summary: This patch modifies X86TargetLowering::LowerVASTART so that
struct va_list is initialized with 32 bit pointers in x32. It also
includes tests that call @llvm.va_start() for x32.

Patch by João Porto

Subscribers: llvm-commits, hjl.tools
Differential Revision: http://reviews.llvm.org/D12346

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247069 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] remove a piece of stale code
Kostya Serebryany [Tue, 8 Sep 2015 20:40:10 +0000 (20:40 +0000)]
[libFuzzer] remove a piece of stale code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247067 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] be more robust when dealing with files on disk (e.g. don't crash if a...
Kostya Serebryany [Tue, 8 Sep 2015 20:36:33 +0000 (20:36 +0000)]
[libFuzzer] be more robust when dealing with files on disk (e.g. don't crash if a file was there but disappeared)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247066 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Support running without a register allocator in the default CodeGen...
Dan Gohman [Tue, 8 Sep 2015 20:36:33 +0000 (20:36 +0000)]
[WebAssembly] Support running without a register allocator in the default CodeGen passes

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247065 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd const overload of findRegisterUseOperand
Matt Arsenault [Tue, 8 Sep 2015 20:21:29 +0000 (20:21 +0000)]
Add const overload of findRegisterUseOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247063 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Update documentation for the landingpad instruction
Vedant Kumar [Tue, 8 Sep 2015 20:16:35 +0000 (20:16 +0000)]
[docs] Update documentation for the landingpad instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247062 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agorefactor matches for De Morgan's Laws; NFCI
Sanjay Patel [Tue, 8 Sep 2015 20:14:13 +0000 (20:14 +0000)]
refactor matches for De Morgan's Laws; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247061 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Mark s_barrier as a high latency instruction
Matt Arsenault [Tue, 8 Sep 2015 19:54:32 +0000 (19:54 +0000)]
AMDGPU: Mark s_barrier as a high latency instruction

These were marked as WriteSALU, which is low latency.
I'm guessing at the value to use, but it should probably
be considered the highest latency instruction.

I'm not sure this has any actual effect since hasSideEffects
probably is preventing any moving of these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247060 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix s_barrier flags
Matt Arsenault [Tue, 8 Sep 2015 19:54:25 +0000 (19:54 +0000)]
AMDGPU: Fix s_barrier flags

This should be convergent. This is not a
barrier in the isBarrier sense, nor
hasCtrlDep.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247059 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes a bug in i8mem_NOREX declaration.
Derek Schuff [Tue, 8 Sep 2015 19:47:15 +0000 (19:47 +0000)]
x32. Fixes a bug in i8mem_NOREX declaration.

The old implementation assumed LP64 which is broken for x32.  Specifically, the
MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit
physreg copy instruction' error message to be reported.

This patch also enable the h-register*ll tests for x32.

Differential Revision: http://reviews.llvm.org/D12336

Patch by João Porto

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247058 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Handle sub of constant for DS offset folding
Matt Arsenault [Tue, 8 Sep 2015 19:34:22 +0000 (19:34 +0000)]
AMDGPU: Handle sub of constant for DS offset folding

sub C, x - > add (sub 0, x), C for DS offsets.

This is mostly to fix regressions that show up when
SeparateConstOffsetFromGEP is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247054 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix PR 24723 - Handle 0-mass backedges in irreducible loops
Diego Novillo [Tue, 8 Sep 2015 19:22:17 +0000 (19:22 +0000)]
Fix PR 24723 - Handle 0-mass backedges in irreducible loops

This corner case happens when we have an irreducible SCC that is
deeply nested.  As we work down the tree, the backedge masses start
getting smaller and smaller until we reach one that is down to 0.

Since we distribute the incoming mass using the backedge masses as
weight, the distributor does not allow zero weights.  So, we simply
ignore them (which will just use the weights of the non-zero nodes).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247050 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MC/ELF] Accept zero for .align directive
Davide Italiano [Tue, 8 Sep 2015 18:59:47 +0000 (18:59 +0000)]
[MC/ELF] Accept zero for .align directive

.align directive refuses alignment 0 -- a comment in the code hints this is
done for GNU as compatibility, but it seems GNU as accepts .align 0
(and silently rounds up alignment to 1).

Differential Revision:  http://reviews.llvm.org/D12682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247048 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix CPP Backend for GEP API changes for opaque pointer types
David Blaikie [Tue, 8 Sep 2015 18:42:29 +0000 (18:42 +0000)]
Fix CPP Backend for GEP API changes for opaque pointer types

Based on a patch by Jerome Witmann.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247047 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMerge or combine tests and convert to FileCheck.
Benjamin Kramer [Tue, 8 Sep 2015 18:36:56 +0000 (18:36 +0000)]
Merge or combine tests and convert to FileCheck.

- Move tests only exercising instsimplify to instsimplify's apint-or.ll
- Actually test the CHECK lines in instsimplify's apint-or.ll
- Merge the remaining tests in apint-or1.ll and apint-or2.ll, use FileCheck

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247045 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix isDiscardableIfUnused to include available_externally linkage.
Evgeniy Stepanov [Tue, 8 Sep 2015 18:25:20 +0000 (18:25 +0000)]
Fix isDiscardableIfUnused to include available_externally linkage.

AvailableExternally functions are discardable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247044 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoremove function names from comments; NFC
Sanjay Patel [Tue, 8 Sep 2015 18:24:36 +0000 (18:24 +0000)]
remove function names from comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247043 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix for bz24500: Avoid non-deterministic code generation triggered by the x86 call...
Andrew Kaylor [Tue, 8 Sep 2015 18:18:46 +0000 (18:18 +0000)]
Fix for bz24500: Avoid non-deterministic code generation triggered by the x86 call frame optimization

Patch by Dave Kreitzer

Differential Revision: http://reviews.llvm.org/D12620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247042 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoadd tests for De Morgan instcombines based on PR22723
Sanjay Patel [Tue, 8 Sep 2015 18:13:03 +0000 (18:13 +0000)]
add tests for De Morgan instcombines based on PR22723

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247040 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix typos, remove noise; NFCI
Sanjay Patel [Tue, 8 Sep 2015 17:58:22 +0000 (17:58 +0000)]
fix typos, remove noise; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247035 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] better documentatio for -save_minimized_corpus=1
Kostya Serebryany [Tue, 8 Sep 2015 17:43:51 +0000 (17:43 +0000)]
[libFuzzer] better documentatio for -save_minimized_corpus=1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247033 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Bitcode] Add compatibility test for llvm 3.7.0
Vedant Kumar [Tue, 8 Sep 2015 17:39:21 +0000 (17:39 +0000)]
[Bitcode] Add compatibility test for llvm 3.7.0

This patch adds llvm-3.7 IR and generated bitcode for our compatibility
test (in accordance with the developer policy).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247031 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] remove -iterations as redundant (there is also -num_runs)
Kostya Serebryany [Tue, 8 Sep 2015 17:30:35 +0000 (17:30 +0000)]
[libFuzzer] remove -iterations as redundant (there is also -num_runs)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247030 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: NFC rename shr/sar
JF Bastien [Tue, 8 Sep 2015 17:21:21 +0000 (17:21 +0000)]
WebAssembly: NFC rename shr/sar

Renamed from: https://github.com/WebAssembly/design/pull/332

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247028 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] add one more mutator: Mutate_ChangeASCIIInteger
Kostya Serebryany [Tue, 8 Sep 2015 17:19:31 +0000 (17:19 +0000)]
[libFuzzer] add one more mutator: Mutate_ChangeASCIIInteger

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247027 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove white space (test commit)
Jun Bum Lim [Tue, 8 Sep 2015 16:11:22 +0000 (16:11 +0000)]
Remove white space (test commit)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247021 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
Zoran Jovanovic [Tue, 8 Sep 2015 15:02:50 +0000 (15:02 +0000)]
[mips][microMIPS] Implement LLE, LUI, LW and LWE instructions
Differential Revision: http://reviews.llvm.org/D1179

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247017 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Temporarily disable this test, as it depends on additional patches...
Dan Gohman [Tue, 8 Sep 2015 13:21:12 +0000 (13:21 +0000)]
[WebAssembly] Temporarily disable this test, as it depends on additional patches that aren't yet checked in.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247011 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX512: kunpck encoding implementation
Igor Breger [Tue, 8 Sep 2015 13:10:00 +0000 (13:10 +0000)]
AVX512: kunpck encoding implementation
Added tests for encoding.

Differential Revision: http://reviews.llvm.org/D12061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247010 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Enable SSA lowering and other pre-regalloc passes
Dan Gohman [Tue, 8 Sep 2015 12:39:25 +0000 (12:39 +0000)]
[WebAssembly] Enable SSA lowering and other pre-regalloc passes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247008 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemoved an old comment, NFC
Elena Demikhovsky [Tue, 8 Sep 2015 12:22:22 +0000 (12:22 +0000)]
Removed an old comment, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247006 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIRLangRef: Add documentation for the subregister indices.
Alex Lorenz [Tue, 8 Sep 2015 11:39:47 +0000 (11:39 +0000)]
MIRLangRef: Add documentation for the subregister indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247005 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIRLangRef: Add documentation for the global value machine operands.
Alex Lorenz [Tue, 8 Sep 2015 11:38:16 +0000 (11:38 +0000)]
MIRLangRef: Add documentation for the global value machine operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247004 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Zoran Jovanovic [Tue, 8 Sep 2015 10:18:38 +0000 (10:18 +0000)]
[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions
Differential Revision: http://reviews.llvm.org/D11801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246999 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThere is a trunc(lshr (zext A), Cst) optimization in InstCombineCasts that
Jakub Kuderski [Tue, 8 Sep 2015 10:03:17 +0000 (10:03 +0000)]
There is a trunc(lshr (zext A), Cst) optimization in InstCombineCasts that
removes cast by performing the lshr on smaller types. However, currently there
is no trunc(lshr (sext A), Cst) variant.
This patch add such optimization by transforming trunc(lshr (sext A), Cst)
to ashr A, Cst.

Differential Revision: http://reviews.llvm.org/D12520

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246997 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Reserve address spaces 1-255 for software use.
Daniel Sanders [Tue, 8 Sep 2015 09:07:03 +0000 (09:07 +0000)]
[mips] Reserve address spaces 1-255 for software use.

Summary: And define them to have noop casts with address spaces 0-255.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12678

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246990 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16...
Zoran Jovanovic [Tue, 8 Sep 2015 08:25:34 +0000 (08:25 +0000)]
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions
Differential Revision: http://reviews.llvm.org/D10956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246987 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake][CMP0051] Avoid for user of objlib to use llvm_update_compile_flags().
NAKAMURA Takumi [Tue, 8 Sep 2015 07:42:06 +0000 (07:42 +0000)]
[CMake][CMP0051] Avoid for user of objlib to use llvm_update_compile_flags().

$<TARGET_OBJECTS> shouldn't require compile flags. Flags are set in obj.${name}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246984 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agocompilation issue, NFC
Elena Demikhovsky [Tue, 8 Sep 2015 07:34:06 +0000 (07:34 +0000)]
compilation issue, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246983 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofixed compilation issue, NFC.
Elena Demikhovsky [Tue, 8 Sep 2015 07:10:08 +0000 (07:10 +0000)]
fixed compilation issue, NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246982 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: Lowering for 512-bit vector shuffles.
Elena Demikhovsky [Tue, 8 Sep 2015 06:38:21 +0000 (06:38 +0000)]
AVX-512: Lowering for 512-bit vector shuffles.
Vector types: <8 x 64>, <16 x 32>, <32 x 16> float and integer.

Differential Revision: http://reviews.llvm.org/D10683

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-readobj] Shrink code a little bit. No functional change.
Davide Italiano [Mon, 7 Sep 2015 20:47:03 +0000 (20:47 +0000)]
[llvm-readobj] Shrink code a little bit. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246976 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoadd missing regression tests for De Morgan's Law transform in InstCombine
Sanjay Patel [Mon, 7 Sep 2015 19:00:38 +0000 (19:00 +0000)]
add missing regression tests for De Morgan's Law transform in InstCombine

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246973 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W...
Zoran Jovanovic [Mon, 7 Sep 2015 13:01:04 +0000 (13:01 +0000)]
[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions
Differential Revision: http://reviews.llvm.org/D11674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246968 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
Zoran Jovanovic [Mon, 7 Sep 2015 11:56:37 +0000 (11:56 +0000)]
[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions
Differential Revision: http://reviews.llvm.org/D11181

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Get rid of SelectT2ShifterOperandReg, NFC
John Brawn [Mon, 7 Sep 2015 11:45:18 +0000 (11:45 +0000)]
[ARM] Get rid of SelectT2ShifterOperandReg, NFC

SelectT2ShifterOperandReg has identical behaviour to SelectImmShifterOperand,
so get rid of it and use SelectImmShifterOperand instead.

Differential Revision: http://reviews.llvm.org/D12195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246962 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt,...
Zoran Jovanovic [Mon, 7 Sep 2015 10:31:31 +0000 (10:31 +0000)]
[mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions
Differential Revision: http://reviews.llvm.org/D12141

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246960 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCODE_OWNERS.TXT is supposed to be sorted by surname
David Majnemer [Mon, 7 Sep 2015 00:41:40 +0000 (00:41 +0000)]
CODE_OWNERS.TXT is supposed to be sorted by surname

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246954 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPrune utf8 chars in comments.
NAKAMURA Takumi [Mon, 7 Sep 2015 00:26:54 +0000 (00:26 +0000)]
Prune utf8 chars in comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246953 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][MMX] Added missing stack folding tests for MMX/SSSE3 instructions
Simon Pilgrim [Sun, 6 Sep 2015 17:50:15 +0000 (17:50 +0000)]
[X86][MMX] Added missing stack folding tests for MMX/SSSE3 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246949 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][AVX512] Added 512-bit vector shift tests.
Simon Pilgrim [Sun, 6 Sep 2015 13:36:32 +0000 (13:36 +0000)]
[X86][AVX512] Added 512-bit vector shift tests.

Only works for avx512f (dq) targets so far - need to add avx512bw tests once char/short shifts are supported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@246943 91177308-0d34-0410-b5e6-96231b3b80d8