8 years agoSatiate the sanitizer build bot
Jonathan Roelofs [Thu, 21 Aug 2014 20:09:15 +0000 (20:09 +0000)]
Satiate the sanitizer build bot

This fixes a missing initializer from r216182

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216212 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove some logic to populateLTOPassManager.
Rafael Espindola [Thu, 21 Aug 2014 20:03:44 +0000 (20:03 +0000)]
Move some logic to populateLTOPassManager.

This will avoid code duplication in the next commit which calls it directly
from the gold plugin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216211 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Add class to group common template arguments related to vector type
Adam Nemet [Thu, 21 Aug 2014 19:50:07 +0000 (19:50 +0000)]
[AVX512] Add class to group common template arguments related to vector type

We discussed the issue of generality vs. readability of the AVX512 classes
recently.  I proposed this approach to try to hide and centralize the mappings
we commonly perform based on the vector type.  A new class X86VectorVTInfo
captures these.

The idea is to pass an instance of this class to classes/multiclasses instead
of the corresponding ValueType.  Then the class/multiclass can use its field
for things that derive from the type rather than passing all those as separate

I modified avx512_valign to demonstrate this new approach.  As you can see
instead of 7 related template parameters we now have one.  The downside is
that we have to refer to fields for the derived values.  I named the argument
'_' in order to make this as invisible as possible.  Please let me know if you
absolutely hate this.  (Also once we allow local initializations in
multiclasses we can recover the original version by assigning the fields to
local variables.)

Another possible use-case for this class is to directly map things, e.g.:

  RegisterClass KRC = X86VectorVTInfo<32, i16>.KRC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216209 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCoverage Mapping: add function's hash to coverage function records.
Alex Lorenz [Thu, 21 Aug 2014 19:23:25 +0000 (19:23 +0000)]
Coverage Mapping: add function's hash to coverage function records.

The profile data format was recently updated and the new indexing api
requires the code coverage tool to know the function's hash as well
as the function's name to get the execution counts for a function.

Differential Revision: http://reviews.llvm.org/D4994

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216207 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-gcc is dead.
Rafael Espindola [Thu, 21 Aug 2014 19:22:24 +0000 (19:22 +0000)]
llvm-gcc is dead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216206 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LIT] Remove documentation for method since it does not exist
Eric Fiselier [Thu, 21 Aug 2014 18:52:58 +0000 (18:52 +0000)]
[LIT] Remove documentation for  method since it does not exist

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216204 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRespect LibraryInfo in populateLTOPassManager and use it. NFC.
Rafael Espindola [Thu, 21 Aug 2014 18:49:52 +0000 (18:49 +0000)]
Respect LibraryInfo in populateLTOPassManager and use it. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216203 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove dead code. NFC.
Rafael Espindola [Thu, 21 Aug 2014 18:11:21 +0000 (18:11 +0000)]
Remove dead code. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216201 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Run a peephole pass right after AdvSIMD pass.
Quentin Colombet [Thu, 21 Aug 2014 18:10:07 +0000 (18:10 +0000)]
[AArch64] Run a peephole pass right after AdvSIMD pass.
The AdvSIMD pass may produce copies that are not coalescer-friendly. The
peephole optimizer knows how to fix that as demonstrated in the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216200 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Factor out ANDWri instruction generation into a helper function...
Juergen Ributzka [Thu, 21 Aug 2014 18:02:25 +0000 (18:02 +0000)]
[FastISel][AArch64] Factor out ANDWri instruction generation into a helper function. NFCI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216199 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoThumb1 load/store optimizer: Improve code to materialize new base register.
Moritz Roth [Thu, 21 Aug 2014 17:11:03 +0000 (17:11 +0000)]
Thumb1 load/store optimizer: Improve code to materialize new base register.

There are two add-immediate instructions in Thumb1: tADDi8 and tADDi3. Only
the latter supports using different source and destination registers, so
whenever we materialize a new base register (at a certain offset) we'd do
so by moving the base register value to the new register and then adding in
place. This patch changes the code to use a single tADDi3 if the offset is
small enough to fit in 3 bits.

Differential Revision: http://reviews.llvm.org/D5006

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216193 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse returns_nonnull in BumpPtrAllocator and MallocAllocator to avoid null-check in...
Hans Wennborg [Thu, 21 Aug 2014 17:10:00 +0000 (17:10 +0000)]
Use returns_nonnull in BumpPtrAllocator and MallocAllocator to avoid null-check in placement new

In both Clang and LLVM, this is a common pattern:

  Size = sizeof(DeclRefExpr) + SomeExtraStuff;
  void *Mem = Context.Allocate(Size, llvm::alignOf<DeclRefExpr>());
  return new (Mem) DeclRefExpr(...);

The annoying thing is that because the default placement-new operator has a
nothrow specification, the compiler will insert a null check of Mem before
calling the DeclRefExpr constructor. This null check is redundant for us,
because we expect the allocation functions to never return null.

By annotating the allocator functions with returns_nonnull, we can optimize
away these checks. Compiling clang with a recent version of Clang and measuring

  $ perf stat -r20 bin/clang.patch -fsyntax-only -w gcc.c && perf stat -r20 bin/clang.orig -fsyntax-only -w gcc.c

Shows a 2.4% speed-up (+- 0.8%).

The pattern occurs in LLVM too. Measuring with -O3 (and now using bzip2.c
instead, because it's smaller):

  $ perf stat -r20 bin/clang.patch -O3 -w bzip2.c  &&  perf stat -r20 bin/clang.orig -O3 -w bzip2.c

Shows 4.4 % speed-up (+- 1%).

If anyone knows of a similar attribute we can use for MSVC, or some other
technique to get rid off the null check there, please let me know.

Differential Revision: http://reviews.llvm.org/D4989

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216192 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Remove redundant test.
Juergen Ributzka [Thu, 21 Aug 2014 16:40:05 +0000 (16:40 +0000)]
[FastISel][AArch64] Remove redundant test.

These tests and many more are already covered by fast-isel-addressing-modes.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216186 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a thread-model knob for lowering atomics on baremetal & single threaded systems
Jonathan Roelofs [Thu, 21 Aug 2014 14:35:47 +0000 (14:35 +0000)]
Add a thread-model knob for lowering atomics on baremetal & single threaded systems


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216182 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoHandle inlining in populateLTOPassManager like in populateModulePassManager.
Rafael Espindola [Thu, 21 Aug 2014 13:35:30 +0000 (13:35 +0000)]
Handle inlining in populateLTOPassManager like in populateModulePassManager.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216178 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[CLNUP] Remove return after llvm_unreachable. Thanks to Hal Finkel for pointing.
Zinovy Nis [Thu, 21 Aug 2014 13:30:05 +0000 (13:30 +0000)]
[CLNUP] Remove return after llvm_unreachable. Thanks to Hal Finkel for pointing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216176 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many...
Benjamin Kramer [Thu, 21 Aug 2014 13:28:02 +0000 (13:28 +0000)]
DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216175 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove DisableGVNLoadPRE from populateLTOPassManager to PassManagerBuilder.
Rafael Espindola [Thu, 21 Aug 2014 13:13:17 +0000 (13:13 +0000)]
Move DisableGVNLoadPRE from populateLTOPassManager to PassManagerBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216174 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86AsmPrinter MCJIT MSVC bug fix.
Josh Klontz [Thu, 21 Aug 2014 12:55:27 +0000 (12:55 +0000)]
X86AsmPrinter MCJIT MSVC bug fix.

This bug was introduced in r213006 which makes an assumption that MCSection is COFF for Windows MSVC. This assumption is broken for MCJIT users where ELF is used instead [1]. The fix is to change the MCSection cast to a dyn_cast.

[1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2013-December/068407.html.

Reviewers: majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4872

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216173 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Enable DP copy, load and store instructions for FPv4-SP
Oliver Stannard [Thu, 21 Aug 2014 12:50:31 +0000 (12:50 +0000)]
[ARM] Enable DP copy, load and store instructions for FPv4-SP

The FPv4-SP floating-point unit is generally referred to as
single-precision only, but it does have double-precision registers and
load, store and GPR<->DPR move instructions which operate on them.
This patch enables the use of these registers, the main advantage of
which is that we now comply with the AAPCS-VFP calling convention.
This partially reverts r209650, which added some AAPCS-VFP support,
but did not handle return values or alignment of double arguments in

This patch also adds tests for Thumb2 code generation for
floating-point instructions and intrinsics, which previously only
existed for ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216172 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSort declarations.
Rafael Espindola [Thu, 21 Aug 2014 12:39:07 +0000 (12:39 +0000)]
Sort declarations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216171 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMake format_object_base's destructor protected and non-virtual.
Benjamin Kramer [Thu, 21 Aug 2014 11:22:05 +0000 (11:22 +0000)]
Make format_object_base's destructor protected and non-virtual.

It's not meant to be used with operator delete and this avoids emitting virtual
dtors for every derived format object.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216170 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReassociate x + -0.1234 * y into x - 0.1234 * y
Erik Verbruggen [Thu, 21 Aug 2014 10:45:30 +0000 (10:45 +0000)]
Reassociate x + -0.1234 * y into x - 0.1234 * y

This does not require -ffast-math, and it gives CSE/GVN more options to
eliminate duplicate expressions in, e.g.:

  return ((x + 0.1234 * y) * (x - 0.1234 * y));

Differential Revision: http://reviews.llvm.org/D4904

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216169 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: Turn redundant if into an assertion.
Benjamin Kramer [Thu, 21 Aug 2014 10:31:37 +0000 (10:31 +0000)]
X86: Turn redundant if into an assertion.

While there remove noop casts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216168 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Added _addcarry_ and _subborrow_ intrinsics
Robert Khasanov [Thu, 21 Aug 2014 09:43:43 +0000 (09:43 +0000)]
[x86] Added _addcarry_ and _subborrow_ intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216164 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes
Robert Khasanov [Thu, 21 Aug 2014 09:34:12 +0000 (09:34 +0000)]
[x86] SMAP: added HasSMAP attribute for CLAC/STAC, corrected attributes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216163 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.
Robert Khasanov [Thu, 21 Aug 2014 09:27:00 +0000 (09:27 +0000)]
[x86] Broadwell: ADOX/ADCX. Added _addcarryx_u{32|64} intrinsics to LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216162 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Enable Broadwell target.
Robert Khasanov [Thu, 21 Aug 2014 09:16:12 +0000 (09:16 +0000)]
[x86] Enable Broadwell target.
Added FeatureSMAP.

Broadwell ISA includes Haswell ISA + ADX + RDSEED + SMAP

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216161 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[INDVARS] Extend using of widening of induction variables for the cases of "sub nsw...
Zinovy Nis [Thu, 21 Aug 2014 08:25:45 +0000 (08:25 +0000)]
[INDVARS] Extend using of widening of induction variables for the cases of "sub nsw" and "mul nsw" instructions.

Currently only "add nsw" are widened. This patch eliminates tons of "sext" instructions for 64 bit code (and the corresponding target code) in cases like:

int N = 100;
float **A;

void foo(int x0, int x1)
        float * A_cur = &A[0][0];
        float * A_next = &A[1][0];
        for(int x = x0; x < x1; ++x).
          // Currently only [x+N] case is widened. Others 2 cases lead to sext.
          // This patch fixes it, so all 3 cases do not need sext.
          const float div = A_cur[x + N] + A_cur[x - N] + A_cur[x * N];
          A_next[x] = div;
> clang++ test.cpp -march=core-avx2 -Ofast  -fno-unroll-loops -fno-tree-vectorize -S -o -

Differential Revision: http://reviews.llvm.org/D4695

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216160 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIntelJITEventListener updates to fix breaks by recent changes to EngineBuilder and...
Elena Demikhovsky [Thu, 21 Aug 2014 07:01:55 +0000 (07:01 +0000)]
IntelJITEventListener updates to fix breaks by recent changes to EngineBuilder and DIContext.
By Arch Robison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216159 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRepace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to...
Craig Topper [Thu, 21 Aug 2014 05:55:13 +0000 (05:55 +0000)]
Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid needing to mention the size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216158 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInstCombine: Fold ((A | B) & C1) ^ (B & C2) -> (A & C1) ^ B if C1^C2=-1
David Majnemer [Thu, 21 Aug 2014 05:14:48 +0000 (05:14 +0000)]
InstCombine: Fold ((A | B) & C1) ^ (B & C2) -> (A & C1) ^ B if C1^C2=-1

Adapted from a patch by Richard Smith, test-case written by me.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216157 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove custom implementations of max/min in StringRef that was originally added to...
Craig Topper [Thu, 21 Aug 2014 04:31:10 +0000 (04:31 +0000)]
Remove custom implementations of max/min in StringRef that was originally added to work an old gcc bug. I believe its been fixed by now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216156 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoadd self to credits
Eric Fiselier [Thu, 21 Aug 2014 04:27:11 +0000 (04:27 +0000)]
add self to credits

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216155 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix a bug around truncating vector in const prop.
Jiangning Liu [Thu, 21 Aug 2014 02:12:35 +0000 (02:12 +0000)]
Fix a bug around truncating vector in const prop.

In constant folding stage, "TRUNC" can't handle vector data type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216149 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder...
Jiangning Liu [Thu, 21 Aug 2014 01:59:30 +0000 (01:59 +0000)]
Revert r216066, "Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216147 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
Quentin Colombet [Thu, 21 Aug 2014 00:19:16 +0000 (00:19 +0000)]
[PeepholeOptimizer] Take advantage of the isInsertSubreg property in the
advanced copy optimization.

This is the final step patch toward transforming:
udiv    r0, r0, r2
udiv    r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16
bx      lr

udiv    r0, r0, r2
udiv    r1, r1, r3
bx      lr

Indeed, thanks to this patch, this optimization is able to look through
vmov.32 d16[0], r0
vmov.32 d16[1], r1

and is able to rewrite the following sequence:
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov    r0, r1, d16

into simple generic GPR copies that the coalescer managed to remove.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216144 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Mark VSETLNi32 with the InsertSubreg property and implement the related
Quentin Colombet [Thu, 21 Aug 2014 00:10:52 +0000 (00:10 +0000)]
[ARM] Mark VSETLNi32 with the InsertSubreg property and implement the related
target hook.

This patch teaches the compiler that:
dX = VSETLNi32 dY, rZ, imm
is the same as:
dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(imm)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216143 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LoopVectorize] Up the maximum unroll factor to 4 for AArch64
James Molloy [Thu, 21 Aug 2014 00:02:51 +0000 (00:02 +0000)]
[LoopVectorize] Up the maximum unroll factor to 4 for AArch64

Only for Cortex-A57 and Cyclone for now, where it has shown wins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216141 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LoopVectorizer] Limit unroll factor in the presence of nested reductions.
James Molloy [Wed, 20 Aug 2014 23:53:52 +0000 (23:53 +0000)]
[LoopVectorizer] Limit unroll factor in the presence of nested reductions.

If we have a scalar reduction, we can increase the critical path length if the loop we're unrolling is inside another loop. Limit, by default to 2, so the critical path only gets increased by one reduction operation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216140 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd isInsertSubreg property.
Quentin Colombet [Wed, 20 Aug 2014 23:49:36 +0000 (23:49 +0000)]
Add isInsertSubreg property.

This patch adds a new property: isInsertSubreg and the related target hooks:
TargetIntrInfo::getInsertSubregInputs and
TargetInstrInfo::getInsertSubregLikeInputs to specify that a target specific
instruction is a (kind of) INSERT_SUBREG.

The approach is similar to r215394.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216139 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence
Jonathan Roelofs [Wed, 20 Aug 2014 23:38:50 +0000 (23:38 +0000)]
Lower thumbv4t & thumbv5 lo->lo copies through a push-pop sequence

On pre-v6 hardware, 'MOV lo, lo' gives undefined results, so such copies need to
be avoided. This patch trades simplicity for implementation time at the expense
of performance... As they say: correctness first, then performance.

See http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-August/075998.html for a few
ideas on how to make this better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216138 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMention the right target hook in the comment on isExtractSubreg property.
Quentin Colombet [Wed, 20 Aug 2014 23:25:28 +0000 (23:25 +0000)]
Mention the right target hook in the comment on isExtractSubreg property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216137 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
Quentin Colombet [Wed, 20 Aug 2014 23:13:02 +0000 (23:13 +0000)]
[PeepholeOptimizer] Take advantage of the isExtractSubreg property in the
advanced copy optimization.

This patch is a step toward transforming:
udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr

udiv r0, r0, r2
udiv r1, r1, r3
bx lr

Indeed, thanks to this patch, this optimization is able to look through
vmov r0, r1, d16
but it does not understand yet
vmov.32 d16[0], r0
vmov.32 d16[1], r1

Comming patches will fix that and update the related test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216136 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoNew InstCombine pattern: (icmp ult/ule (A + C1), C3) | (icmp ult/ule (A + C2), C3...
Yi Jiang [Wed, 20 Aug 2014 22:55:40 +0000 (22:55 +0000)]
New InstCombine pattern: (icmp ult/ule (A + C1), C3) | (icmp ult/ule (A + C2), C3)  to (icmp ult/ule ((A & ~(C1 ^ C2)) + max(C1, C2)), C3) under certain condition

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216135 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDon't allow MCStreamer::EmitIntValue to output 0-byte integers.
Alexey Samsonov [Wed, 20 Aug 2014 22:46:38 +0000 (22:46 +0000)]
Don't allow MCStreamer::EmitIntValue to output 0-byte integers.
It makes no sense and can hide bugs. In particular, it lead
to left shift by 64 bits, which is an undefined behavior,
properly reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216134 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Mark VMOVRRD with the ExtractSubreg property and implement the related
Quentin Colombet [Wed, 20 Aug 2014 22:16:19 +0000 (22:16 +0000)]
[ARM] Mark VMOVRRD with the ExtractSubreg property and implement the related
target hook.

This patch teaches the compiler that:
is the same as:
rX = EXTRACT_SUBREG dZ, ssub_0
rY = EXTRACT_SUBREG dZ, ssub_1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216132 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix undefined behavior (left shift of negative value) in SystemZ backend.
Alexey Samsonov [Wed, 20 Aug 2014 21:56:43 +0000 (21:56 +0000)]
Fix undefined behavior (left shift of negative value) in SystemZ backend.

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216131 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd isExtractSubreg property.
Quentin Colombet [Wed, 20 Aug 2014 21:51:26 +0000 (21:51 +0000)]
Add isExtractSubreg property.

This patch adds a new property: isExtractSubreg and the related target hooks:
TargetIntrInfo::getExtractSubregInputs and
TargetInstrInfo::getExtractSubregLikeInputs to specify that a target specific
instruction is a (kind of) EXTRACT_SUBREG.

The approach is similar to r215394.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216130 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix null reference creation in SelectionDAG constructor.
Alexey Samsonov [Wed, 20 Aug 2014 21:40:15 +0000 (21:40 +0000)]
Fix null reference creation in SelectionDAG constructor.

Store TargetSelectionDAGInfo as a pointer instead of a reference:
getSelectionDAGInfo() may not be implemented for certain backends
(e.g. it's not currently implemented for R600).

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216129 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix undefined behavior (left shift of negative value) in Hexagon backend.
Alexey Samsonov [Wed, 20 Aug 2014 21:22:03 +0000 (21:22 +0000)]
Fix undefined behavior (left shift of negative value) in Hexagon backend.

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216125 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGIn...
Alexey Samsonov [Wed, 20 Aug 2014 20:57:26 +0000 (20:57 +0000)]
Cleanup: Delete seemingly unused reference to MachineDominatorTree from ScheduleDAGInstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216124 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDon't prevent a vselect of constants from becoming a single load (PR20648).
Sanjay Patel [Wed, 20 Aug 2014 20:34:56 +0000 (20:34 +0000)]
Don't prevent a vselect of constants from becoming a single load (PR20648).

Fix for PR20648 - http://llvm.org/bugs/show_bug.cgi?id=20648

This patch checks the operands of a vselect to see if all values are constants.
If yes, bail out of any further attempts to create a blend or shuffle because
SelectionDAGLegalize knows how to turn this kind of vselect into a single load.

This already happens for machines without SSE4.1, so the added checks just send
more targets down that path.

Differential Revision: http://reviews.llvm.org/D4934

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216121 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: Add missing triples from r216119
Duncan P. N. Exon Smith [Wed, 20 Aug 2014 19:58:59 +0000 (19:58 +0000)]
X86: Add missing triples from r216119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216120 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: Align the stack on word boundaries in LowerFormalArguments()
Duncan P. N. Exon Smith [Wed, 20 Aug 2014 19:40:59 +0000 (19:40 +0000)]
X86: Align the stack on word boundaries in LowerFormalArguments()

The goal of the patch is to implement section 3.2.3 of the AMD64 ABI
correctly.  The controlling sentence is, "The size of each argument gets
rounded up to eightbytes.  Therefore the stack will always be eightbyte
aligned." The equivalent sentence in the i386 ABI page 37 says, "At all
times, the stack pointer should point to a word-aligned area."  For both
architectures, the stack pointer is not being rounded up to the nearest
eightbyte or word between the last normal argument and the first
variadic argument.

Patch by Thomas Jablin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216119 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix null reference creation in ScheduleDAGInstrs constructor call.
Alexey Samsonov [Wed, 20 Aug 2014 19:36:05 +0000 (19:36 +0000)]
Fix null reference creation in ScheduleDAGInstrs constructor call.

Both MachineLoopInfo and MachineDominatorTree may be null in ScheduleDAGMI
constructor call. It is undefined behavior to take references to these values.

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216118 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDo not insert a tail call when returning multiple values on X86
Keno Fischer [Wed, 20 Aug 2014 19:00:37 +0000 (19:00 +0000)]
Do not insert a tail call when returning multiple values on X86

Summary: This fixes http://llvm.org/bugs/show_bug.cgi?id=19530.
The problem is that X86ISelLowering erroneously thought the third call
was eligible for tail call elimination.
It would have been if it's return value was actually the one returned
by the calling function, but here that is not the case and
additional values are being returned.

Test Plan: Test case from the original bug report is included.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D4968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216117 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix undefined behavior (left shift by 64 bits) in ScaledNumber::toString().
Alexey Samsonov [Wed, 20 Aug 2014 18:30:07 +0000 (18:30 +0000)]
Fix undefined behavior (left shift by 64 bits) in ScaledNumber::toString().

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216116 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agocritical-anti-dependency breaker: don't use reg def info from kill insts (PR20308)
Sanjay Patel [Wed, 20 Aug 2014 18:03:00 +0000 (18:03 +0000)]
critical-anti-dependency breaker: don't use reg def info from kill insts (PR20308)

In PR20308 ( http://llvm.org/bugs/show_bug.cgi?id=20308 ), the critical-anti-dependency breaker
caused a miscompile because it broke a WAR hazard using a register that it thinks is available
based on info from a kill inst. Until PR18663 is solved, we shouldn't use any def/use info from
a kill because they are really just nops.

This patch adds guard checks for kills around calls to ScanInstruction() where the DefIndices
array is set. For good measure, add an assert in ScanInstruction() so we don't hit this bug again.

The test case is a reduced version of the code from the bug report.

Differential Revision: http://reviews.llvm.org/D4977

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216114 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
Quentin Colombet [Wed, 20 Aug 2014 17:41:48 +0000 (17:41 +0000)]
[PeepholeOptimizer] Refactor the advanced copy optimization to take advantage of
the isRegSequence property.

This is a follow-up of r215394 and r215404, which respectively introduces the
isRegSequence property and uses it for ARM.

Thanks to the property introduced by the previous commits, this patch is able
to optimize the following sequence:
vmov d0, r2, r3
vmov d1, r0, r1
vmov r0, s0
vmov r1, s2
udiv r0, r1, r0
vmov r1, s1
vmov r2, s3
udiv r1, r2, r1
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr

udiv r0, r0, r2
udiv r1, r1, r3
vmov.32 d16[0], r0
vmov.32 d16[1], r1
vmov r0, r1, d16
bx lr

This patch refactors how the copy optimizations are done in the peephole
optimizer. Prior to this patch, we had one copy-related optimization that
replaced a copy or bitcast by a generic, more suitable (in terms of register
file), copy.

With this patch, the peephole optimizer features two copy-related optimizations:
1. One for rewriting generic copies to generic copies:
2. One for replacing non-generic copies with generic copies:

The goals of these two optimizations are slightly different: one rewrite the
operand of the instruction (#1), the other kills off the non-generic instruction
and replace it by a (sequence of) generic instruction(s).

Both optimizations rely on the ValueTracker introduced in r212100.

The ValueTracker has been refactored to use the information from the
TargetInstrInfo for non-generic instruction. As part of the refactoring, we
switched the tracking from the index of the definition to the actual register
(virtual or physical). This one change is to provide better consistency with
register related APIs and to ease the use of the TargetInstrInfo.

Moreover, this patch introduces a new helper class CopyRewriter used to ease the
rewriting of generic copies (i.e., #1).

Finally, this patch adds a dead code elimination pass right after the peephole
optimizer to get rid of dead code that may appear after rewriting.

This is related to <rdar://problem/12702965>.

Review: http://reviews.llvm.org/D4874

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216088 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTweak CFGPrinter to wrap very long names.
Andrew Trick [Wed, 20 Aug 2014 17:38:12 +0000 (17:38 +0000)]
Tweak CFGPrinter to wrap very long names.

I added wrapping to the CFGPrinter a while back so the -view-cfg
output is actually viewable. I've since enountered very long mangled
names with the same problem, so I'm slightly tweaking this code to
work in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216087 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove unused field.
Rafael Espindola [Wed, 20 Aug 2014 17:33:44 +0000 (17:33 +0000)]
Remove unused field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216086 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
Juergen Ributzka [Wed, 20 Aug 2014 16:34:15 +0000 (16:34 +0000)]
[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.

This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero-
extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both
operands have to be sign-/zero-extended with separate instructions.

Related to <rdar://problem/17913111>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoQuick fix for an use after free.
Rafael Espindola [Wed, 20 Aug 2014 15:19:37 +0000 (15:19 +0000)]
Quick fix for an use after free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216071 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd note to LangRef about how function arguments can be unnamed and
Dan Liew [Wed, 20 Aug 2014 15:06:30 +0000 (15:06 +0000)]
Add note to LangRef about how function arguments can be unnamed and
how this affects the numbering of unnamed temporaries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216070 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSilencing a -Wcast-qual warning. NFC.
Aaron Ballman [Wed, 20 Aug 2014 12:54:13 +0000 (12:54 +0000)]
Silencing a -Wcast-qual warning. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216068 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSilencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted...
Aaron Ballman [Wed, 20 Aug 2014 12:14:35 +0000 (12:14 +0000)]
Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216067 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoOptimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type
Jiangning Liu [Wed, 20 Aug 2014 12:05:15 +0000 (12:05 +0000)]
Optimize ZERO_EXTEND and SIGN_EXTEND in both SelectionDAG Builder and type
legalization stage. With those two optimizations, fewer signed/zero extension
instructions can be inserted, and then we can expose more opportunities to
Machine CSE pass in back-end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216066 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x32] Fix FrameIndex check in SelectLEA64_32Addr
Pavel Chupin [Wed, 20 Aug 2014 11:59:22 +0000 (11:59 +0000)]
[x32] Fix FrameIndex check in SelectLEA64_32Addr

Fixes http://llvm.org/bugs/show_bug.cgi?id=20016 reproducible on new
lea-5.ll case.
Also use RSP/RBP for x32 lea to save 1 byte used for 0x67 prefix in
ESP/EBP case.

Test Plan: lea tests modified to include x32/nacl and new test added

Reviewers: nadav, dschuff, t.p.northover

Subscribers: llvm-commits, zinovy.nis

Differential Revision: http://reviews.llvm.org/D4929

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216065 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: Fix codegen for rbit intrinsic
Yi Kong [Wed, 20 Aug 2014 10:40:20 +0000 (10:40 +0000)]
ARM: Fix codegen for rbit intrinsic

LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.

The bug was originally introduced in r211057.

Differential Revision: http://reviews.llvm.org/D4980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216064 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate projects lists.
Bill Wendling [Wed, 20 Aug 2014 07:32:09 +0000 (07:32 +0000)]
Update projects lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216048 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd libcxxabi to the projects.
Bill Wendling [Wed, 20 Aug 2014 07:30:08 +0000 (07:30 +0000)]
Add libcxxabi to the projects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216047 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInstCombine: Annotate sub with nuw when we prove it's safe
David Majnemer [Wed, 20 Aug 2014 07:17:31 +0000 (07:17 +0000)]
InstCombine: Annotate sub with nuw when we prove it's safe

We can prove that a 'sub' can be a 'sub nuw' if the left-hand side is
negative and the right-hand side is non-negative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216045 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix an off by 1 bug that prevented SmallPtrSet from using all of its 'small' capacity...
Craig Topper [Wed, 20 Aug 2014 04:41:36 +0000 (04:41 +0000)]
Fix an off by 1 bug that prevented SmallPtrSet from using all of its 'small' capacity. Then fix the early return in the move constructor that prevented 'small' moves from clearing the NumElements in the moved from object. The directed test missed this because it was always testing large moves due to the off by 1 bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216044 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoConstants.h: Fix possible typo in r216015. [-Wdocumentation]
NAKAMURA Takumi [Wed, 20 Aug 2014 04:22:47 +0000 (04:22 +0000)]
Constants.h: Fix possible typo in r216015. [-Wdocumentation]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216043 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[dfsan] Treat vararg custom functions like unimplemented functions.
Peter Collingbourne [Wed, 20 Aug 2014 01:40:23 +0000 (01:40 +0000)]
[dfsan] Treat vararg custom functions like unimplemented functions.

Because declarations of these functions can appear in places like autoconf
checks, they have to be handled somehow, even though we do not support
vararg custom functions. We do so by printing a warning and calling the
uninstrumented function, as we do for unimplemented functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216042 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.
Juergen Ributzka [Wed, 20 Aug 2014 01:10:36 +0000 (01:10 +0000)]
[FastISel][AArch64] Use the proper FMOV instruction to materialize a +0.0.

Use FMOVWSr/FMOVXDr instead of FMOVSr/FMOVDr, which have the proper register
class to be used with the zero register. This makes the MachineInstruction
verifier happy again.

This is related to <rdar://problem/18027157>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216040 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoInstCombine: Annotate sub with nsw when we prove it's safe
David Majnemer [Tue, 19 Aug 2014 23:36:30 +0000 (23:36 +0000)]
InstCombine: Annotate sub with nsw when we prove it's safe

We can prove that a 'sub' can be a 'sub nsw' under certain conditions:
- The sign bits of the operands is the same.
- Both operands have more than 1 sign bit.

The subtraction cannot be a signed overflow in either case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216037 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoBumpPtrAllocator: don't accept 0 for the alignment parameter
Hans Wennborg [Tue, 19 Aug 2014 23:35:33 +0000 (23:35 +0000)]
BumpPtrAllocator: don't accept 0 for the alignment parameter

It seems unnecessary to have to use an extra branch to check for this special case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216036 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Factor out ADDS/SUBS instruction emission and add support for...
Juergen Ributzka [Tue, 19 Aug 2014 22:29:55 +0000 (22:29 +0000)]
[FastISel][AArch64] Factor out ADDS/SUBS instruction emission and add support for extensions and shift folding.

Factor out the ADDS/SUBS instruction emission code into helper functions and
make the helper functions more clever to support most of the different ADDS/SUBS
instructions the architecture support. This includes better immedediate support,
shift folding, and sign-/zero-extend folding.

This fixes <rdar://problem/17913111>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216033 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSplit parseAssembly into parseAssembly and parseAssemblyInto.
Rafael Espindola [Tue, 19 Aug 2014 22:05:47 +0000 (22:05 +0000)]
Split parseAssembly into parseAssembly and parseAssemblyInto.

This should restore the functionality of parsing new code into an existing
module without the confusing interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216031 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDelete unused argument in AArch64MCInstLower constructor: it doesn't
Alexey Samsonov [Tue, 19 Aug 2014 21:51:08 +0000 (21:51 +0000)]
Delete unused argument in AArch64MCInstLower constructor: it doesn't
use Mangler, and Mangler is in fact not even created when AArch64MCInstLower
is constructed.

This bug is reported by UBSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216030 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLangRef: Move example of function-scope uselistorder to a function
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:48:04 +0000 (21:48 +0000)]
LangRef: Move example of function-scope uselistorder to a function

Should make the example added in r216025 a little more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216027 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Implement uselistorder assembly directives
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:30:15 +0000 (21:30 +0000)]
IR: Implement uselistorder assembly directives

Implement `uselistorder` and `uselistorder_bb` assembly directives,
which allow the use-list order to be recovered when round-tripping to

This is the bulk of PR20515.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216025 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Add an i386 RuntimeDyldMachO test case.
Lang Hames [Tue, 19 Aug 2014 21:26:36 +0000 (21:26 +0000)]
[MCJIT] Add an i386 RuntimeDyldMachO test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216024 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Fix a missed case when threading OnlyIfReduced through ConstantExpr
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:18:21 +0000 (21:18 +0000)]
IR: Fix a missed case when threading OnlyIfReduced through ConstantExpr

In r216015 I missed propagating `OnlyIfReduced` through the inline
versions of `getGetElementPtr()` (I was relying on compile failures on
mismatches between the header and source signatures to get them all).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216023 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoverify-uselistorder: Force -preserve-bc-use-list-order
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 21:08:27 +0000 (21:08 +0000)]
verify-uselistorder: Force -preserve-bc-use-list-order

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216022 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Extend floating-point materialization test.
Juergen Ributzka [Tue, 19 Aug 2014 20:35:07 +0000 (20:35 +0000)]
[FastISel][AArch64] Extend floating-point materialization test.

This adds the missing test that I promised for r215753 to test the
materialization of the floating-point value +0.0.

Related to <rdar://problem/18027157>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216019 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofix the gcc build
Rafael Espindola [Tue, 19 Aug 2014 20:06:25 +0000 (20:06 +0000)]
fix the gcc build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216018 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MCJIT] Allow '$' characters in symbol names in RuntimeDyldChecker.
Lang Hames [Tue, 19 Aug 2014 20:04:45 +0000 (20:04 +0000)]
[MCJIT] Allow '$' characters in symbol names in RuntimeDyldChecker.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216017 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Fix ConstantExpr::replaceUsesOfWithOnConstant()
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 20:03:35 +0000 (20:03 +0000)]
IR: Fix ConstantExpr::replaceUsesOfWithOnConstant()

Change `ConstantExpr` to follow the model the other constants are using:
only malloc a replacement if it's going to be used.  This fixes a subtle
bug where if an API user had used `ConstantExpr::get()` already to
create the replacement but hadn't given it any users, we'd delete the

This relies on r216015 to thread `OnlyIfReduced` through

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216016 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Thread OnlyIfReduced through ConstantExpr::getWithOperands()
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:45:37 +0000 (19:45 +0000)]
IR: Thread OnlyIfReduced through ConstantExpr::getWithOperands()

In order to change `ConstantExpr::replaceUsesOfWithOnConstant()` to work
like other constants (e.g., using `ConstantArray::getImpl()`), thread
`OnlyIfReduced` through as necessary.  When `OnlyIfReduced` is false,
there's no functionality change.  When it's true, if there's no constant
folding or type changes `nullptr` is returned instead of the new

`ConstantExpr::replaceUsesOfWithOnConstant()` will be updated to use the
"true" version in a follow-up commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216015 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix the MSVC build.
Rafael Espindola [Tue, 19 Aug 2014 19:45:15 +0000 (19:45 +0000)]
Fix the MSVC build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216014 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply [FastISel][AArch64] Add support for more addressing modes (r215597).
Juergen Ributzka [Tue, 19 Aug 2014 19:44:17 +0000 (19:44 +0000)]
Reapply [FastISel][AArch64] Add support for more addressing modes (r215597).

Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
FastISel didn't take much advantage of the different addressing modes available
to it on AArch64. This commit allows the ComputeAddress method to recognize more
addressing modes that allows shifts and sign-/zero-extensions to be folded into
the memory operation itself.

For Example:
  lsl x1, x1, #3     --> ldr x0, [x0, x1, lsl #3]
  ldr x0, [x0, x1]

  sxtw x1, w1
  lsl x1, x1, #3     --> ldr x0, [x0, x1, sxtw #3]
  ldr x0, [x0, x1]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216013 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply [FastISel][X86] Add large code model support for materializing floating-point...
Juergen Ributzka [Tue, 19 Aug 2014 19:44:13 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Add large code model support for materializing floating-point constants (r215595).

Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
In the large code model for X86 floating-point constants are placed in the
constant pool and materialized by loading from it. Since the constant pool
could be far away, a PC relative load might not work. Therefore we first
materialize the address of the constant pool with a movabsq and then load
from there the floating-point value.

Fixes <rdar://problem/17674628>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216012 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply [FastISel][X86] Use XOR to materialize the "0" value (r215594).
Juergen Ributzka [Tue, 19 Aug 2014 19:44:10 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Use XOR to materialize the "0" value (r215594).

Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216011 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply [FastISel][X86] Emit more efficient instructions for integer constant materia...
Juergen Ributzka [Tue, 19 Aug 2014 19:44:06 +0000 (19:44 +0000)]
Reapply [FastISel][X86] Emit more efficient instructions for integer constant materialization (r215593).

Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
This mostly affects the i64 value type, which always resulted in an 15byte
mobavsq instruction to materialize any constant. The custom code checks the
value of the immediate and tries to use a different and smaller mov
instruction when possible.

This fixes <rdar://problem/17420988>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216010 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply [FastISel][AArch64] Make use of the zero register when possible (r215591).
Juergen Ributzka [Tue, 19 Aug 2014 19:44:02 +0000 (19:44 +0000)]
Reapply [FastISel][AArch64] Make use of the zero register when possible (r215591).

Note: This was originally reverted to track down a buildbot error. Reapply
without any modifications.

Original commit message:
This change materializes now the value "0" from the zero register.
The zero register can be folded by several instruction, so no
materialization is need at all.

Fixes <rdar://problem/17924413>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216009 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoADT: Unit test for ArrayRef::equals change in r215986
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:18:46 +0000 (19:18 +0000)]
ADT: Unit test for ArrayRef::equals change in r215986

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216008 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: De-duplicate code for replacing operands in place
Duncan P. N. Exon Smith [Tue, 19 Aug 2014 19:13:30 +0000 (19:13 +0000)]
IR: De-duplicate code for replacing operands in place

This is non-trivial and sits in three places.  Move it to

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216007 91177308-0d34-0410-b5e6-96231b3b80d8