oota-llvm.git
7 years agoRevert r245635, "[InstCombine] Transform A & (L - 1) u< L --> L != 0"
NAKAMURA Takumi [Fri, 21 Aug 2015 07:46:07 +0000 (07:46 +0000)]
Revert r245635, "[InstCombine] Transform A & (L - 1) u< L --> L != 0"

It caused miscompilation in clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245678 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTest Commit: Reformats 2 lines in LangRef.rst
Mohammad Shahid [Fri, 21 Aug 2015 05:31:07 +0000 (05:31 +0000)]
Test Commit: Reformats 2 lines in LangRef.rst

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245673 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLinker: Remove empty destructor.
Peter Collingbourne [Fri, 21 Aug 2015 04:51:24 +0000 (04:51 +0000)]
Linker: Remove empty destructor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245672 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLTO: Simplify ownership of LTOCodeGenerator::TargetMach.
Peter Collingbourne [Fri, 21 Aug 2015 04:45:57 +0000 (04:45 +0000)]
LTO: Simplify ownership of LTOCodeGenerator::TargetMach.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245671 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLTO: Simplify ownership of LTOCodeGenerator::CodegenOptions.
Peter Collingbourne [Fri, 21 Aug 2015 04:45:55 +0000 (04:45 +0000)]
LTO: Simplify ownership of LTOCodeGenerator::CodegenOptions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245670 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc] Support user-specified stack object overalignment.
James Y Knight [Fri, 21 Aug 2015 04:17:56 +0000 (04:17 +0000)]
[Sparc] Support user-specified stack object overalignment.

Note: I do not implement a base pointer, so it's still impossible to
have dynamic realignment AND dynamic alloca in the same function.

This also moves the code for determining the frame index reference
into getFrameIndexReference, where it belongs, instead of inline in
eliminateFrameIndex.

[Begin long-winded screed]

Now, stack realignment for Sparc is actually a silly thing to support,
because the Sparc ABI has no need for it -- unlike the situation on
x86, the stack is ALWAYS aligned to the required alignment for the CPU
instructions: 8 bytes on sparcv8, and 16 bytes on sparcv9.

However, LLVM unfortunately implements user-specified overalignment
using stack realignment support, so for now, I'm going to go along
with that tradition. GCC instead treats objects which have alignment
specification greater than the maximum CPU-required alignment for the
target as a separate block of stack memory, with their own virtual
base pointer (which gets aligned). Doing it that way avoids needing to
implement per-target support for stack realignment, except for the
targets which *actually* have an ABI-specified stack alignment which
is too small for the CPU's requirements.

Further unfortunately in LLVM, the default canRealignStack for all
targets effectively returns true, despite that implementing that is
something a target needs to do specifically. So, the previous behavior
on Sparc was to silently ignore the user's specified stack
alignment. Ugh.

Yet MORE unfortunate, if a target actually does return false from
canRealignStack, that also causes the user-specified alignment to be
*silently ignored*, rather than emitting an error.

(I started looking into fixing that last, but it broke a bunch of
tests, because LLVM actually *depends* on having it silently ignored:
some architectures (e.g. non-linux i386) have smaller stack alignment
than spilled-register alignment. But, the fact that a register needs
spilling is not known until within the register allocator. And by that
point, the decision to not reserve the frame pointer has been frozen
in place. And without a frame pointer, stack realignment is not
possible. So, canRealignStack() returns false, and
needsStackRealignment() then returns false, assuming everyone can just
go on their merry way assuming the alignment requirements were
probably just suggestions after-all. Sigh...)

Differential Revision: http://reviews.llvm.org/D12208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245668 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTransformUtils: Introduce module splitter.
Peter Collingbourne [Fri, 21 Aug 2015 02:48:20 +0000 (02:48 +0000)]
TransformUtils: Introduce module splitter.

The module splitter splits a module into linkable partitions. It will
be used to implement parallel LTO code generation.

This initial version of the splitter does not attempt to deal with the
somewhat subtle symbol visibility issues around module splitting. These
will be dealt with in a future change.

Differential Revision: http://reviews.llvm.org/D12132

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245662 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSparcAsmParser.cpp: Appease msc x86.
NAKAMURA Takumi [Fri, 21 Aug 2015 01:12:19 +0000 (01:12 +0000)]
SparcAsmParser.cpp: Appease msc x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245661 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: Fix testcase of r245640
Matthias Braun [Fri, 21 Aug 2015 00:23:19 +0000 (00:23 +0000)]
AArch64: Fix testcase of r245640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245647 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLP] Add one more test case for propagating 'nontemporal' attributes.
Michael Zolotukhin [Fri, 21 Aug 2015 00:08:39 +0000 (00:08 +0000)]
[SLP] Add one more test case for propagating 'nontemporal' attributes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245644 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodelete more dead code from this testcase.
Adrian Prantl [Fri, 21 Aug 2015 00:02:04 +0000 (00:02 +0000)]
delete more dead code from this testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245643 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFurther reduce the IR in this testcase based on a further reduction
Adrian Prantl [Thu, 20 Aug 2015 23:59:39 +0000 (23:59 +0000)]
Further reduce the IR in this testcase based on a further reduction
of the original source by David Blaikie (thanks!).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245642 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: Fix cmp;ccmp ordering
Matthias Braun [Thu, 20 Aug 2015 23:33:34 +0000 (23:33 +0000)]
AArch64: Fix cmp;ccmp ordering

When producing conditional compare sequences for or operations we need
to negate the operands and the finally tested flags. The thing is if we negate
the finally tested flags this equals a logical negation of all previously
emitted expressions. There was a case missing where we have to order OR
expressions so they get emitted first.

This fixes http://llvm.org/PR24459

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245641 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: Do not create CCMP on multiple users.
Matthias Braun [Thu, 20 Aug 2015 23:33:31 +0000 (23:33 +0000)]
AArch64: Do not create CCMP on multiple users.

Create CMP;CCMP sequences from and/or trees does not gain us anything if
the and/or tree is materialized to a GP register anyway. While most of
the code already checked for hasOneUse() there was one important case
missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245640 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstSimplify] add nuw %x, C2 must be at least C2
David Majnemer [Thu, 20 Aug 2015 23:01:41 +0000 (23:01 +0000)]
[InstSimplify] add nuw %x, C2 must be at least C2

Use the fact that add nuw always creates a larger bit pattern when
trying to simplify comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245638 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Mark more operators as Expand.
Dan Gohman [Thu, 20 Aug 2015 22:57:13 +0000 (22:57 +0000)]
[WebAssembly] Mark more operators as Expand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245636 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Transform A & (L - 1) u< L --> L != 0
Sanjoy Das [Thu, 20 Aug 2015 22:31:55 +0000 (22:31 +0000)]
[InstCombine] Transform A & (L - 1) u< L --> L != 0

Summary:
This transform is never a pessimization at the IR level (since it
replaces an `icmp` with another), and has potentiall payoffs:

 1. It may make the `icmp` fold away or become loop invariant.
 2. It may make the `A & (L - 1)` computation dead.

This shows up in Java, in range checks generated by array accesses of
the form `a[i & (a.length - 1)]`.

Reviewers: reames, majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12210

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245635 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLP] Propagate 'nontemporal' attribute into vectorized instructions.
Michael Zolotukhin [Thu, 20 Aug 2015 22:28:15 +0000 (22:28 +0000)]
[SLP] Propagate 'nontemporal' attribute into vectorized instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245633 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVectorize] Propagate 'nontemporal' attribute into vectorized instructions.
Michael Zolotukhin [Thu, 20 Aug 2015 22:27:38 +0000 (22:27 +0000)]
[LoopVectorize] Propagate 'nontemporal' attribute into vectorized instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245632 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename Instruction::dropUnknownMetadata() to dropUnknownNonDebugMetadata()
Adrian Prantl [Thu, 20 Aug 2015 22:00:30 +0000 (22:00 +0000)]
Rename Instruction::dropUnknownMetadata() to dropUnknownNonDebugMetadata()
and make it always preserve debug locations, since all callers wanted this
behavior anyway.

This is addressing a post-commit review feedback for r245589.

NFC (inside the LLVM tree).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245622 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Look for scalar through one bitcast when lowering to VBROADCAST.
Ahmed Bougacha [Thu, 20 Aug 2015 21:02:39 +0000 (21:02 +0000)]
[X86] Look for scalar through one bitcast when lowering to VBROADCAST.

Fixes PR23464: one way to use the broadcast intrinsics is:

  _mm256_broadcastw_epi16(_mm_cvtsi32_si128(*(int*)src));

We don't currently fold this, but now that we use native IR for
the intrinsics (r245605), we can look through one bitcast to find
the broadcast scalar.

Differential Revision: http://reviews.llvm.org/D10557

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245613 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add some broadcast-from-memory tests.
Ahmed Bougacha [Thu, 20 Aug 2015 20:59:41 +0000 (20:59 +0000)]
[X86] Add some broadcast-from-memory tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245612 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] truncating 64-bit to 32-bit is free
Jingyue Wu [Thu, 20 Aug 2015 20:59:02 +0000 (20:59 +0000)]
[NVPTX] truncating 64-bit to 32-bit is free

Summary:
Add an LSR test that exercises isTruncateFree. Without this change, LSR creates
another indvar representing the truncated value.

Reviewers: jholewinski, eliben

Subscribers: jholewinski, llvm-commits

Differential Revision: http://reviews.llvm.org/D12058

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245611 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Replace avx2 broadcast intrinsics with native IR.
Ahmed Bougacha [Thu, 20 Aug 2015 20:36:19 +0000 (20:36 +0000)]
[X86] Replace avx2 broadcast intrinsics with native IR.

Since r245605, the clang headers don't use these anymore.
r245165 updated some of the tests already; update the others, add
an autoupgrade, remove the intrinsics, and cleanup the definitions.

Differential Revision: http://reviews.llvm.org/D10555

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245606 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[asan] Add ASAN support for AArch64 42-bit VMA
Adhemerval Zanella [Thu, 20 Aug 2015 18:30:40 +0000 (18:30 +0000)]
[asan] Add ASAN support for AArch64 42-bit VMA

This patch adds support for asan on aarch64-linux with 42-bit VMA
(current default config for 64K pagesize kernels).  The support is
enabled by defining the SANITIZER_AARCH64_VMA to 42 at build time
for both clang/llvm and compiler-rt.  The default VMA is 39 bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245594 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ValueTracking] computeOverflowForSignedAdd and isKnownNonNegative
Jingyue Wu [Thu, 20 Aug 2015 18:27:04 +0000 (18:27 +0000)]
[ValueTracking] computeOverflowForSignedAdd and isKnownNonNegative

Summary:
Refactor, NFC

Extracts computeOverflowForSignedAdd and isKnownNonNegative from NaryReassociate to ValueTracking in case
others need it.

Reviewers: reames

Subscribers: majnemer, llvm-commits

Differential Revision: http://reviews.llvm.org/D11313

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245591 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LVI] Avoid iterator invalidation in LazyValueInfoCache::threadEdge
Bruno Cardoso Lopes [Thu, 20 Aug 2015 18:24:54 +0000 (18:24 +0000)]
[LVI] Avoid iterator invalidation in LazyValueInfoCache::threadEdge

Do that by copying out the elements to another SmallPtrSet.
Follow up from r245309.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245590 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a bug that caused SimplifyCFG to drop DebugLocs.
Adrian Prantl [Thu, 20 Aug 2015 18:24:02 +0000 (18:24 +0000)]
Fix a bug that caused SimplifyCFG to drop DebugLocs.

Instruction::dropUnknownMetadata(KnownSet) is supposed to preserve all
metadata in KnownSet, but the condition for DebugLocs was inverted.

Most users of dropUnknownMetadata() actually worked around this by not
adding LLVMContext::MD_dbg to their list of KnowIDs.
This is now made explicit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245589 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a debug location handling bug in GVN.
Adrian Prantl [Thu, 20 Aug 2015 18:23:56 +0000 (18:23 +0000)]
Fix a debug location handling bug in GVN.
Caught by the famous "DebugLoc describes the currect SubProgram" assertion.

When GVN is removing a nonlocal load it updates the debug location of the
SSA value it replaced the load with with the one of the load. In the
testcase this actually overwrites a valid debug location with an empty one.

In reality GVN has to make an arbitrary choice between two equally valid
debug locations. This patch changes to behavior to only update the
location if the value doesn't already have a debug location.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245588 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LVer] Fix FIXME: hide addPHINodes, NFC
Adam Nemet [Thu, 20 Aug 2015 17:22:29 +0000 (17:22 +0000)]
[LVer] Fix FIXME: hide addPHINodes, NFC

Since Ashutosh made findDefsUsedOutsideOfLoop public, we can clean this
up.

Now clients that don't compute DefsUsedOutsideOfLoop can just call
versionLoop() and computing DefsUsedOutsideOfLoop will happen
implicitly.  With that there is no reason to expose addPHINodes anymore.

Ashutosh, you can now drop the calls to findDefsUsedOutsideOfLoop and
addPHINodes in LVerLICM and things should just work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245579 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Don't try and custom lower a vNi64 SETCC.
James Molloy [Thu, 20 Aug 2015 16:33:44 +0000 (16:33 +0000)]
[ARM] Don't try and custom lower a vNi64 SETCC.

It won't go well. We've already marked 64-bit SETCCs as non-Custom, but it's just possible that a SETCC has a legal result type but an illegal operand type. If this happens, bail out before we create unselectable nodes.

Fixes PR24292. I tried to create a testcase but in 99% of cases we can't trigger this - not surprising that this bug has been latent since 2009.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245577 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix symbol value computation when part of the expression is weak.
Rafael Espindola [Thu, 20 Aug 2015 16:18:30 +0000 (16:18 +0000)]
Fix symbol value computation when part of the expression is weak.

This matches the behaviour of the gnu assembler and is part of
fixing pr24486.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245576 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc]: correct the 'set' synthetic instruction
Douglas Katzman [Thu, 20 Aug 2015 16:16:16 +0000 (16:16 +0000)]
[Sparc]: correct the 'set' synthetic instruction

Differential Revision: http://reviews.llvm.org/D12194

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245575 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoOptimize bitwise even/odd test (-x&1 -> x&1) to not use negation.
Balaram Makam [Thu, 20 Aug 2015 15:35:00 +0000 (15:35 +0000)]
Optimize bitwise even/odd test (-x&1 -> x&1) to not use negation.

Summary: We know that -x & 1 is equivalent to x & 1, avoid using negation for testing if a negative integer is even or odd.

Reviewers: majnemer

Subscribers: junbuml, mssimpso, gberry, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D12156

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245569 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIU...
Zoran Jovanovic [Thu, 20 Aug 2015 11:51:49 +0000 (11:51 +0000)]
[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions
Differential Revision: http://reviews.llvm.org/D10955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245554 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fix FBLD and FBSTP
Marina Yatsina [Thu, 20 Aug 2015 11:51:24 +0000 (11:51 +0000)]
[X86] Fix FBLD and FBSTP

FBLD and FBSTP should receive TBYTE because it is defined as
FBLD m80
FBSTP m80

Differential Revision: http://reviews.llvm.org/D11748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245553 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fix bug in COMISD and COMISS definition in td files
Marina Yatsina [Thu, 20 Aug 2015 11:21:36 +0000 (11:21 +0000)]
[X86] Fix bug in COMISD and COMISS definition in td files

COMISD should receive QWORD because it is defined as
 (V)COMISD xmm1, xmm2/m64

COMISS should receive DWORD because it is defined as
 (V)COMISS xmm1, xmm2/m32

Differential Revision: http://reviews.llvm.org/D11712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245551 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake helper functions static. NFC.
Benjamin Kramer [Thu, 20 Aug 2015 09:57:22 +0000 (09:57 +0000)]
Make helper functions static. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245549 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fix the (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) fold
David Majnemer [Thu, 20 Aug 2015 09:00:56 +0000 (09:00 +0000)]
[X86] Fix the (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) fold

We didn't check for the necessary preconditions before folding a
mask/shift into a single mask.

This fixes PR24516.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245544 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[DSE] Enable removal of lifetime intrinsics in terminating blocks"
Bjorn Steinbrink [Thu, 20 Aug 2015 08:58:47 +0000 (08:58 +0000)]
Revert "[DSE] Enable removal of lifetime intrinsics in terminating blocks"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245543 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DSE] Enable removal of lifetime intrinsics in terminating blocks
Bjorn Steinbrink [Thu, 20 Aug 2015 08:25:28 +0000 (08:25 +0000)]
[DSE] Enable removal of lifetime intrinsics in terminating blocks

Usually DSE is not supposed to remove lifetime intrinsics, but it's
actually ok to remove them for dead objects in terminating blocks,
because they convey no extra information there. Until we hit a lifetime
start that cannot be removed, that is. Because from that point on the
lifetime intrinsics become interesting again, e.g. for stack coloring.

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11710

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245542 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARC] Pull the ObjC ARC components that really serve the role of
Chandler Carruth [Thu, 20 Aug 2015 08:06:03 +0000 (08:06 +0000)]
[ARC] Pull the ObjC ARC components that really serve the role of
analyses into LLVM's Analysis library rather than having them in
a Transforms library.

This is motivated by the need to have the core AliasAnalysis
infrastructure be aware of the ObjCARCAliasAnalysis. However, it also
seems like a nice and clean separation. Everything was very easy to move
and this doesn't create much clutter in the analysis library IMO.

Differential Revision: http://reviews.llvm.org/D12133

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245541 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Fix value type on XVCMPEQDP for v2f64 comparisons
Hal Finkel [Thu, 20 Aug 2015 03:02:02 +0000 (03:02 +0000)]
[PowerPC] Fix value type on XVCMPEQDP for v2f64 comparisons

XVCMPEQDP is used for VSX v2f64 equality comparisons, but the value type needs
to be v2i64 (as that's the corresponding SETCC type).

Fixes PR24225.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245535 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Fix the int2fp(fp2int(x)) DAGCombine to ignore ppc_fp128
Hal Finkel [Thu, 20 Aug 2015 01:18:20 +0000 (01:18 +0000)]
[PowerPC] Fix the int2fp(fp2int(x)) DAGCombine to ignore ppc_fp128

This DAGCombine was creating custom SDAG nodes with an illegal ppc_fp128
operand type because it was triggering on f64/f32 int2fp(fp2int(ppc_fp128 x)),
but shouldn't (it should only apply to f32/f64 types). The result was a crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245530 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Use the global value syntax for global value memory operands.
Alex Lorenz [Thu, 20 Aug 2015 00:20:03 +0000 (00:20 +0000)]
MIR Serialization: Use the global value syntax for global value memory operands.

This commit modifies the serialization syntax so that the global IR values in
machine memory operands use the global value '@<name>' syntax instead of the
current '%ir.<name>' syntax.

The unnamed global IR values are handled by this commit as well, as the
existing global value parsing method can parse the unnamed globals already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245527 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Change syntax for the call entry pseudo source values.
Alex Lorenz [Thu, 20 Aug 2015 00:12:57 +0000 (00:12 +0000)]
MIR Serialization: Change syntax for the call entry pseudo source values.

The global IR values in machine memory operands should use the global value
'@<name>' syntax instead of the current '%ir.<name>' syntax.

However, the global value call entry pseudo source values use the global value
syntax already. Therefore, the syntax for the call entry pseudo source values
has to be changed so that the global values and call entry global value PSVs
can be parsed without ambiguities.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245526 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix test failure introduced by r245521.
Alex Lorenz [Wed, 19 Aug 2015 23:56:37 +0000 (23:56 +0000)]
Fix test failure introduced by r245521.

Machine memory operands can contain pointer values that are constants, and
the 'getLocalSlot' method requires non-constant values.

The constant pointer values will have to be serialized in a different patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245523 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize unnamed local IR values in memory operands.
Alex Lorenz [Wed, 19 Aug 2015 23:31:05 +0000 (23:31 +0000)]
MIR Serialization: Serialize unnamed local IR values in memory operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245521 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: parseIRValue should take in a constant pointer. NFC.
Alex Lorenz [Wed, 19 Aug 2015 23:27:07 +0000 (23:27 +0000)]
MIR Parser: parseIRValue should take in a constant pointer. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245520 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Printer: Extract the code that prints IR slots to a separate function. NFC.
Alex Lorenz [Wed, 19 Aug 2015 23:24:37 +0000 (23:24 +0000)]
MIR Printer: Extract the code that prints IR slots to a separate function. NFC.

This code can be reused when printing references to unnamed local IR values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245519 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAllow Optionals to be compared to None
David Blaikie [Wed, 19 Aug 2015 23:07:27 +0000 (23:07 +0000)]
Allow Optionals to be compared to None

This is something like nullopt in std::experimental::optional. Optional
could already be constructed from None, so this seems like an obvious
extension from there.

I have a use in a future patch for Clang, though it may not go that
way/end up used - so this seemed worth committing now regardless.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245518 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Kaleidoscope-Ch2: Don't pass -Wno-unused-private-field unconditionally.
NAKAMURA Takumi [Wed, 19 Aug 2015 22:55:16 +0000 (22:55 +0000)]
[CMake] Kaleidoscope-Ch2: Don't pass -Wno-unused-private-field unconditionally.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245516 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] enable machine combiner reassociations for scalar double-precision min/max
Sanjay Patel [Wed, 19 Aug 2015 21:27:27 +0000 (21:27 +0000)]
[x86] enable machine combiner reassociations for scalar double-precision min/max

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245506 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] enable machine combiner reassociations for scalar single-precision maximums
Sanjay Patel [Wed, 19 Aug 2015 21:18:46 +0000 (21:18 +0000)]
[x86] enable machine combiner reassociations for scalar single-precision maximums

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245504 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding
Simon Pilgrim [Wed, 19 Aug 2015 21:11:58 +0000 (21:11 +0000)]
[DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding

We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes

I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding

Differential Revision: http://reviews.llvm.org/D12118

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245503 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64][FastISel] Don't fold shifts with UB.
Juergen Ributzka [Wed, 19 Aug 2015 20:52:55 +0000 (20:52 +0000)]
[AArch64][FastISel] Don't fold shifts with UB.

We are already falling back to SelectionDAG when encountering an shift with UB.
This adds the same checks for shifts with UB that get folded into arithmetic or
logical operations.

This fixes rdar://problem/22345295.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245499 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Emit more efficient >= comparisons against 0
David Majnemer [Wed, 19 Aug 2015 20:51:40 +0000 (20:51 +0000)]
[X86] Emit more efficient >= comparisons against 0

We don't do a great job with >= 0 comparisons against zero when the
result is used as an i8.

Given something like:
  void f(long long LL, bool *B) {
    *B = LL >= 0;
  }

We used to generate:
  shrq    $63, %rdi
  xorb    $1, %dil
  movb    %dil, (%rsi)

Now we generate:
  testq   %rdi, %rdi
  setns   (%rsi)

Differential Revision: http://reviews.llvm.org/D12136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245498 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Use the default alignment for SIMD types.
Dan Gohman [Wed, 19 Aug 2015 20:30:20 +0000 (20:30 +0000)]
[WebAssembly] Use the default alignment for SIMD types.

Previously WebAssembly's datalayout string had -v128:8:128. This had been an
attempt to declare a certain level of support for unaligned SIMD accesses.
However, clang makes its own determinations for SIMD alignment that are
independent of the datalayout string, so this wasn't actually meaningful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245494 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE.
Simon Pilgrim [Wed, 19 Aug 2015 20:09:50 +0000 (20:09 +0000)]
[DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE.

Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle.

Differential Revision: http://reviews.llvm.org/D12125

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245490 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReplace some calls to isa<LandingPadInst> with isEHPad()
David Majnemer [Wed, 19 Aug 2015 19:54:02 +0000 (19:54 +0000)]
Replace some calls to isa<LandingPadInst> with isEHPad()

No functionality change is intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245487 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMinor tidying of regex in a test
Paul Robinson [Wed, 19 Aug 2015 19:36:35 +0000 (19:36 +0000)]
Minor tidying of regex in a test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245486 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc]: asm-only support for the ldstub instruction.
Douglas Katzman [Wed, 19 Aug 2015 19:30:57 +0000 (19:30 +0000)]
[Sparc]: asm-only support for the ldstub instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245485 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.
Alex Lorenz [Wed, 19 Aug 2015 19:19:16 +0000 (19:19 +0000)]
MIR Parser: Rename 'MachineOperandWithLocation' to 'ParsedMachineOperand'. NFC.

Besides storing the operand's source range, this structure now stores other
attributes as well, so the name should reflect this fact.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245483 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize instruction's register ties.
Alex Lorenz [Wed, 19 Aug 2015 19:05:34 +0000 (19:05 +0000)]
MIR Serialization: Serialize instruction's register ties.

This commit serializes the machine instruction's register operand ties.
The ties are printed out only when the instructon has register ties that are
different from the ties that are specified in the instruction's description.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245482 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTemporary fix for the self-host failures introduced by rL244921.
Nemanja Ivanovic [Wed, 19 Aug 2015 19:04:47 +0000 (19:04 +0000)]
Temporary fix for the self-host failures introduced by rL244921.

This revision has introduced an issue that only affects bootstrapped compiler
when it is printing the ASM. I am working on resolving the issue, but in the
meantime, I'm disabling the legalization of scalar_to_vector operation for v2i64
and the associated testing until I can get this fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245481 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize defined registers that require 'def' register flag.
Alex Lorenz [Wed, 19 Aug 2015 18:55:47 +0000 (18:55 +0000)]
MIR Serialization: Serialize defined registers that require 'def' register flag.

The defined registers are already serialized - they are represented by placing
them before the '=' in a machine instruction. However, certain instructions like
INLINEASM can have defined register operands after the '=', so this commit
introduces the 'def' register flag for such operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245480 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PeepholeOptimizer] Look through PHIs to find additional register sources
Bruno Cardoso Lopes [Wed, 19 Aug 2015 18:53:36 +0000 (18:53 +0000)]
[PeepholeOptimizer] Look through PHIs to find additional register sources

Reintroduce r245442. Remove an overly conservative assertion introduced
in r245442. We could replace the assertion to use `shareSameRegisterFile`
instead, but in that point in `insertPHI` we already lost the original
Def subreg to check against. So drop the assertion completely.

Original commit message:

- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245479 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SPARC] Enable writing to floating-point-state register.
Douglas Katzman [Wed, 19 Aug 2015 18:34:48 +0000 (18:34 +0000)]
[SPARC] Enable writing to floating-point-state register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245475 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Kaleidoscope] More inter-chapter diff reduction.
Lang Hames [Wed, 19 Aug 2015 18:32:58 +0000 (18:32 +0000)]
[Kaleidoscope] More inter-chapter diff reduction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245474 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Fix minor typo in CodingStandards.rst
Vedant Kumar [Wed, 19 Aug 2015 18:19:12 +0000 (18:19 +0000)]
[docs] Fix minor typo in CodingStandards.rst

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245473 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Kaleidoscope] Clang-format the Kaleidoscope tutorials.
Lang Hames [Wed, 19 Aug 2015 18:15:58 +0000 (18:15 +0000)]
[Kaleidoscope] Clang-format the Kaleidoscope tutorials.

Also reduces changes between tutorial chapters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245472 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Improve short-form diags on long-form Match_InvalidOperand.
Ahmed Bougacha [Wed, 19 Aug 2015 17:40:19 +0000 (17:40 +0000)]
[AArch64] Improve short-form diags on long-form Match_InvalidOperand.

Since r244955, we try to use the short-form ErrorInfo when both
tries failed, and the long-form match failed on a suffix operand.
However, this means we sometimes mix ErrorInfo and MatchResult
(one manifestation of this being PR24498). Instead, restore both.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245469 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Fix GCC 4.8.0 ICE in lambda function
Hal Finkel [Wed, 19 Aug 2015 17:26:07 +0000 (17:26 +0000)]
[SCEV] Fix GCC 4.8.0 ICE in lambda function

Rewrite some code to not use a lambda function. The non-lambda code is just
about as clean as the original, and not any longer. The lambda function causes
an internal compiler error in GCC 4.8.0, and it is not worth breaking support
for that compiler over this. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245466 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LAA] Comment how memchecks are codegened
Adam Nemet [Wed, 19 Aug 2015 17:24:36 +0000 (17:24 +0000)]
[LAA] Comment how memchecks are codegened

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245465 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[AArch64] Simplify/refactor code to ease code review. NFC."
Renato Golin [Wed, 19 Aug 2015 16:29:53 +0000 (16:29 +0000)]
Revert "[AArch64] Simplify/refactor code to ease code review. NFC."

This reverts commit r245443, as it broke AArch64 test-suite tramp3d
with an assert "Reg && "Null register has no regunits".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245455 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes a bug in x32 exception handling.
Derek Schuff [Wed, 19 Aug 2015 16:28:21 +0000 (16:28 +0000)]
x32. Fixes a bug in x32 exception handling.

This patch updates the X86 lowering so that the Exception Pointer and Selector
are 64-bit wide only if Subtarget.isTarget64BitLP64.

Patch by João Porto

Reviewers: dschuff, rnk
Differential Revision: http://reviews.llvm.org/D12111

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245454 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes jmp %reg in x32
JF Bastien [Wed, 19 Aug 2015 16:17:08 +0000 (16:17 +0000)]
x32. Fixes jmp %reg in x32

x32 has 32-bit pointers; x86-64 can't jmp %r32. This patch addresses this issue by explicitly zero-extending brind's target to 64-bits.

Author: jpp

Reviewers: jfb, dschuff, pavel.v.chupin

Subscribers: llvm-commits

Differential revision: http://reviews.llvm.org/D12112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245452 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended.
James Y Knight [Wed, 19 Aug 2015 15:59:49 +0000 (15:59 +0000)]
[Sparc] Rename LoadASR and StoreASR from r245360 to *ASI, as was intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245450 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[PeepholeOptimizer] Look through PHIs to find additional register sources"
Bruno Cardoso Lopes [Wed, 19 Aug 2015 15:10:32 +0000 (15:10 +0000)]
Revert "[PeepholeOptimizer] Look through PHIs to find additional register sources"

Revert r245442 while investigating a fix. An assertion hit in
http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_build/11380

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245446 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SPARC] Fix BooleanContents, so that select of a trunc doesn't
James Y Knight [Wed, 19 Aug 2015 14:47:04 +0000 (14:47 +0000)]
[SPARC] Fix BooleanContents, so that select of a trunc doesn't
eliminate the trunc.

Differential Revision: http://reviews.llvm.org/D10442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245444 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Simplify/refactor code to ease code review. NFC.
Chad Rosier [Wed, 19 Aug 2015 14:34:54 +0000 (14:34 +0000)]
[AArch64] Simplify/refactor code to ease code review. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245443 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PeepholeOptimizer] Look through PHIs to find additional register sources
Bruno Cardoso Lopes [Wed, 19 Aug 2015 14:34:41 +0000 (14:34 +0000)]
[PeepholeOptimizer] Look through PHIs to find additional register sources

Reapply r243486.

- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197
rdar://problem/20404526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245442 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Add instruction selection patterns for vmin/vmax
Silviu Baranga [Wed, 19 Aug 2015 14:11:27 +0000 (14:11 +0000)]
[ARM] Add instruction selection patterns for vmin/vmax

Summary:
The mid-end was generating vector smin/smax/umin/umax nodes, but
we were using vbsl to generatate the code. This adds the vmin/vmax
patterns and a test to check that we are now generating vmin/vmax
instructions.

Reviewers: rengolin, jmolloy

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D12105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245439 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMap %fprs to %asr6 in the Sparc assembler parser.
Joerg Sonnenberger [Wed, 19 Aug 2015 13:55:14 +0000 (13:55 +0000)]
Map %fprs to %asr6 in the Sparc assembler parser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245437 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEmit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.
Daniel Sanders [Wed, 19 Aug 2015 12:03:04 +0000 (12:03 +0000)]
Emit <regmask R1 R2 R3 ...> instead of just <regmask> in IR dumps.

Reviewers: qcolombet

Subscribers: kparzysz, qcolombet, llvm-commits

Differential Revision: http://reviews.llvm.org/D11644

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245433 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[X86] Widen the 'AND' mask if doing so shrinks the encoding size"
Tobias Grosser [Wed, 19 Aug 2015 11:35:10 +0000 (11:35 +0000)]
Revert "[X86] Widen the 'AND' mask if doing so shrinks the encoding size"

This reverts commit 245169 which miscompiles MultiSource/Applications/siod
from LNT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245432 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for...
Michael Kuperstein [Wed, 19 Aug 2015 11:21:43 +0000 (11:21 +0000)]
[X86] Do not lower scalar sdiv/udiv to a shifts + mul sequence when optimizing for minsize

There are some cases where the mul sequence is smaller, but for the most part,
using a div is preferable. This does not apply to vectors, since x86 doesn't
have vector idiv, and a vector mul/shifts sequence ought to be smaller than a
scalarized division.

Differential Revision: http://reviews.llvm.org/D12082

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245431 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TLI] Refactor "is integer division cheap" queries.
Michael Kuperstein [Wed, 19 Aug 2015 11:17:59 +0000 (11:17 +0000)]
[TLI] Refactor "is integer division cheap" queries.

This removes the isPow2SDivCheap() query, as it is not currently used in
any meaningful way. isIntDivCheap() no longer relies on a state variable
(as all in-tree target set it to false), but the interface allows querying
based on the type optimization level.

NFC.

Differential Revision: http://reviews.llvm.org/D12082

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245430 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove an empty directory left after r245318.
Alexander Kornienko [Wed, 19 Aug 2015 09:00:21 +0000 (09:00 +0000)]
Remove an empty directory left after r245318.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245426 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMore clean up, still NFC. Remove dead variables now that the casts are gone.
Nick Lewycky [Wed, 19 Aug 2015 06:25:30 +0000 (06:25 +0000)]
More clean up, still NFC. Remove dead variables now that the casts are gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245420 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoClean up this file a little. Remove dead casts, casting Values to Values. Adjust...
Nick Lewycky [Wed, 19 Aug 2015 06:22:33 +0000 (06:22 +0000)]
Clean up this file a little. Remove dead casts, casting Values to Values. Adjust some comments for typos and whitespace. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245419 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoExposed findDefsUsedOutsideOfLoop as a loop utility function
Ashutosh Nema [Wed, 19 Aug 2015 05:40:42 +0000 (05:40 +0000)]
Exposed findDefsUsedOutsideOfLoop as a loop utility function

Exposed findDefsUsedOutsideOfLoop as a loop utility function by moving
it from LoopDistribute to LoopUtils.

Reviewed By: anemet

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245416 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LPM] Teach the legacy pass manager to support *using* an analysis
Chandler Carruth [Wed, 19 Aug 2015 03:02:12 +0000 (03:02 +0000)]
[LPM] Teach the legacy pass manager to support *using* an analysis
without *requiring* it.

This allows a pass indicate that it will use an analysis if available
(through getAnalysisIfAvailable). When the pass manager knows this, it
will refrain from deleting that analysis if it can. Naturally, it will
still get invalidated at the correct time. These passes are not
considered when scheduling the pass pipeline, so typically they will
require manual scheduling, but this may also allow passes with
getAnalysisIfAvailable to find the analysis more often if nothing after
them requires that analysis and it wasn't invalidated.

I don't have a particular use case with the current passes, but with my
new structure for alias analyses, this will be very useful. We want to
allow people to customize the set of AAs available by scheduling
additional passes. These's aren't ever *required* for obvious reasons.
So we need some way to mark in the legacy pass manager that they will
still be used if available.

This is essentially how analysis groups already work. But this makes the
feature generally available and more explicit. It should allow the AA
change to not impact how people trigger a custom alias analysis being
available at a certain point in compilation.

Differential Revision: http://reviews.llvm.org/D12114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245409 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix how DependenceAnalysis calls delinearization
Hal Finkel [Wed, 19 Aug 2015 02:56:36 +0000 (02:56 +0000)]
Fix how DependenceAnalysis calls delinearization

Fix how DependenceAnalysis calls delinearization, mirroring what is done in
Delinearization.cpp (mostly by making sure to call getSCEVAtScope before
delinearizing, and by removing the unnecessary 'Pairs == 1' check).

Patch by Vaivaswatha Nagaraj!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245408 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Fix PR24469 resulting from r245025 and re-enable dead store elimination acros...
Eric Christopher [Wed, 19 Aug 2015 02:15:13 +0000 (02:15 +0000)]
Revert "Fix PR24469 resulting from r245025 and re-enable dead store elimination across basicblocks."

This is causing bootstrap problems, e.g.: http://bb.pgr.jp/builders/clang-3stage-i686-linux/builds/2960

This reverts r245195.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245402 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake ScalarEvolution::isKnownPredicate a little smarter
Hal Finkel [Wed, 19 Aug 2015 01:51:51 +0000 (01:51 +0000)]
Make ScalarEvolution::isKnownPredicate a little smarter

Here we make ScalarEvolution::isKnownPredicate, indirectly, a little smarter.
Given some relational comparison operator OP, and two AddRec SCEVs, {I,+,S} OP
{J,+,T}, we can reduce this to the comparison I OP J when S == T, both AddRecs
are for the same loop, and both are known not to wrap.

As it turns out, because of the way that backedge-guard expressions can be
leveraged when computing known predicates, this allows indvars to simplify the
if-statement comparison in this loop:

  void foo (int *a, int *b, int n) {
    for (int i = 0; i < n; ++i) {
      if (i > n)
        a[i] = b[i] + 1;
    }
  }

which, somewhat surprisingly, we were not previously optimizing away.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245400 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSplit ARM and AArch64 emutls.ll test
Chih-Hung Hsieh [Wed, 19 Aug 2015 01:44:51 +0000 (01:44 +0000)]
Split ARM and AArch64 emutls.ll test

Differential Revision: http://reviews.llvm.org/D12127

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245399 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize MMI's variable debug information.
Alex Lorenz [Wed, 19 Aug 2015 00:13:25 +0000 (00:13 +0000)]
MIR Serialization: Serialize MMI's variable debug information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245396 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[BasicAA] Add a test for PR24468 to be sure we won't regress
Quentin Colombet [Wed, 19 Aug 2015 00:08:26 +0000 (00:08 +0000)]
[BasicAA] Add a test for PR24468 to be sure we won't regress
when we finally get the GEP aliasing right.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245395 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[BasicAA] Revert r221876 because it can produce incorrect aliasing
Quentin Colombet [Wed, 19 Aug 2015 00:07:20 +0000 (00:07 +0000)]
[BasicAA] Revert r221876 because it can produce incorrect aliasing
information: see PR24468.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@245394 91177308-0d34-0410-b5e6-96231b3b80d8