oota-llvm.git
7 years agollvm/examples/BrainF: Give an explicit pointee type to ConstantExpr::getGetElementPtr...
NAKAMURA Takumi [Thu, 2 Apr 2015 22:44:00 +0000 (22:44 +0000)]
llvm/examples/BrainF: Give an explicit pointee type to ConstantExpr::getGetElementPtr(ty...), according to r233938.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233983 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ASan] Don't use stack malloc for 32-bit functions using inline asm
Reid Kleckner [Thu, 2 Apr 2015 21:44:55 +0000 (21:44 +0000)]
[ASan] Don't use stack malloc for 32-bit functions using inline asm

This prevents us from running out of registers in the backend.

Introducing stack malloc calls prevents the backend from recognizing the
inline asm operands as stack objects. When the backend recognizes a
stack object, it doesn't need to materialize the address of the memory
in a physical register. Instead it generates a simple SP-based memory
operand. Introducing a stack malloc forces the backend to find a free
register for every memory operand. 32-bit x86 simply doesn't have enough
registers for this to succeed in most cases.

Reviewers: kcc, samsonov

Differential Revision: http://reviews.llvm.org/D8790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233979 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix unused variable in NDEBUG builds
Reid Kleckner [Thu, 2 Apr 2015 21:43:22 +0000 (21:43 +0000)]
Fix unused variable in NDEBUG builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233978 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SLSR] handles off bounds GEPs
Jingyue Wu [Thu, 2 Apr 2015 21:18:32 +0000 (21:18 +0000)]
[SLSR] handles off bounds GEPs

Summary:
The old requirement on GEP candidates being in bounds is unnecessary.
For off-bound GEPs, we still have

  &B[i * S] = B + (i * S) * e = B + (i * e) * S

Test Plan: slsr_offbound_gep in slsr-gep.ll

Reviewers: meheff

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8809

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233949 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Make llvm.eh.actions use frameescape indices for catch params
Reid Kleckner [Thu, 2 Apr 2015 21:13:31 +0000 (21:13 +0000)]
[WinEH] Make llvm.eh.actions use frameescape indices for catch params

This makes it possible to use the same representation of llvm.eh.actions
in outlined handlers as we use in the parent function because i32's are
just constants that can be copied freely between functions.

I had to add a sentinel alloca to the list of child allocas so that we
don't try to sink the catch object into the handler. Normally, one would
use nullptr for this kind of thing, but TinyPtrVector doesn't support
null elements. More than that, it's elements have to have a suitable
alignment. Therefore, I settled on this for my sentinel:

  AllocaInst *getCatchObjectSentinel() {
    return static_cast<AllocaInst *>(nullptr) + 1;
  }

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233947 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vector
Sanjay Patel [Thu, 2 Apr 2015 20:21:52 +0000 (20:21 +0000)]
[AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vector

Without this patch, we split the 256-bit vector into halves and produced something like:
movzwl (%rdi), %eax
vmovd %eax, %xmm0
vxorps %xmm1, %xmm1, %xmm1
vblendps $15, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]

Now, we eliminate the xor and blend because those zeros are free with the vmovd:
        movzwl  (%rdi), %eax
        vmovd   %eax, %xmm0

This should be the final fix needed to resolve PR22685:
https://llvm.org/bugs/show_bug.cgi?id=22685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233941 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[opaque pointer type] API migration for GEP constant factories
David Blaikie [Thu, 2 Apr 2015 18:55:32 +0000 (18:55 +0000)]
[opaque pointer type] API migration for GEP constant factories

Require the pointee type to be passed explicitly and assert that it is
correct. For now it's possible to pass nullptr here (and I've done so in
a few places in this patch) but eventually that will be disallowed once
all clients have been updated or removed. It'll be a long road to get
all the way there... but if you have the cahnce to update your callers
to pass the type explicitly without depending on a pointer's element
type, that would be a good thing to do soon and a necessary thing to do
eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233938 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add a comment to make it explicit why we increased the complexity.
Quentin Colombet [Thu, 2 Apr 2015 18:54:23 +0000 (18:54 +0000)]
[AArch64] Add a comment to make it explicit why we increased the complexity.
Follow-up of r233653.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233936 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86, AVX] adjust tablegen patterns to generate better code for scalar insertion...
Sanjay Patel [Thu, 2 Apr 2015 17:56:17 +0000 (17:56 +0000)]
[X86, AVX] adjust tablegen patterns to generate better code for scalar insertion into zero vector (PR23073)

For code like this:

define <8 x i32> @load_v8i32() {
  ret <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
}

We produce this AVX code:

_load_v8i32:                            ## @load_v8i32
  movl $7, %eax
  vmovd %eax, %xmm0
  vxorps %ymm1, %ymm1, %ymm1
  vblendps $1, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
  retq

There are at least 2 bugs in play here:

    We're generating a blend when a move scalar does the same job using 2 less instruction bytes (see FIXMEs).
    We're not matching an existing pattern that would eliminate the xor and blend entirely. The zero bytes are free with vmovd.

The 2nd fix involves an adjustment of "AddedComplexity" [1] and mostly masks the 1st problem.

[1] AddedComplexity has close to no documentation in the source.
The best we have is this comment: "roughly corresponds to the number of nodes that are covered".
It appears that x86 has bastardized this definition by inflating its values for some other
undocumented reason. For example, we have a pattern with "AddedComplexity = 400" (!).

I searched my way to this page:
https://groups.google.com/forum/#!topic/llvm-dev/5UX-Og9M0xQ

Differential Revision: http://reviews.llvm.org/D8794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233931 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopAccesses] Handle case when no memchecks are needed after partitioning
Adam Nemet [Thu, 2 Apr 2015 17:51:57 +0000 (17:51 +0000)]
[LoopAccesses] Handle case when no memchecks are needed after partitioning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233930 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd an LLVM_PTR_SIZE macro to make LLVM_ALIGNAS more useful
Reid Kleckner [Thu, 2 Apr 2015 17:43:35 +0000 (17:43 +0000)]
Add an LLVM_PTR_SIZE macro to make LLVM_ALIGNAS more useful

MSVC 2013 requires the argument to __declspec(align()) to be an integer
constant expression that doesn't involve any identifiers like sizeof.

For GCC and Clang, LLVM_PTR_SIZE is equivalent to __SIZEOF_POINTER__,
which dates back to GCC 4.6 and Clang 2010. If that's not available, we
get sizeof(void*), which works with alignas() and
__attribute__((aligned())).

For MSVC, LLVM_PTR_SIZE is 4 or 8 depending on _WIN64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233929 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo and reword in LangRef
Eli Bendersky [Thu, 2 Apr 2015 15:20:04 +0000 (15:20 +0000)]
Fix typo and reword in LangRef

Patch by Douglas Katzman

Differential Revision: http://reviews.llvm.org/D8785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233920 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[alignof] Put back the hack for old versions of GCC.
Benjamin Kramer [Thu, 2 Apr 2015 13:31:50 +0000 (13:31 +0000)]
[alignof] Put back the hack for old versions of GCC.

This works around a bug (PR56859) that is fixed in all versions of GCC I tested
with but was present in 4.8.0. Using 4.8.0 is of course a terrible idea, but looks
like we can't drop it just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233916 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[support] Add a macro wrapper for alignas and simplify some code.
Benjamin Kramer [Thu, 2 Apr 2015 11:32:48 +0000 (11:32 +0000)]
[support] Add a macro wrapper for alignas and simplify some code.

We wrap __attribute((aligned)) for GCC 4.7 and __declspec(align) for
MSVC. The latter behaves weird in some contexts so this should be used
carefully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233910 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.
Vasileios Kalintiris [Thu, 2 Apr 2015 11:09:40 +0000 (11:09 +0000)]
[mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.

Summary:
Avoid duplicate code in Mips16FrameLowering and MipsSEFrameLowering by
providing an implementation of the eliminateCallFramePseudoInstr()
function from their base class.

Depends on D8640.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233909 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
Elena Demikhovsky [Thu, 2 Apr 2015 10:51:40 +0000 (10:51 +0000)]
AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
by Asaf Badouh (asaf.badouh@intel.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233906 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.
Vasileios Kalintiris [Thu, 2 Apr 2015 10:42:44 +0000 (10:42 +0000)]
[mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.

Summary:
adjustStackPtr() is implemented from both MipsSEInstrInfo and
Mips16InstrInfo. It makes sense to expose this function from
MipsInstrInfo and avoid explicit casting in some cases.

Depends on D8638.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233905 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Make sure that we don't adjust the stack pointer by zero amount.
Vasileios Kalintiris [Thu, 2 Apr 2015 10:14:54 +0000 (10:14 +0000)]
[mips] Make sure that we don't adjust the stack pointer by zero amount.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233904 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Rename v8.1a from "extension" to "architecture": follow-up
Vladimir Sukharev [Thu, 2 Apr 2015 09:32:14 +0000 (09:32 +0000)]
[ARM] Rename v8.1a from "extension" to "architecture": follow-up

Corrected forgotten change to remove excess "generic-armv8.1-a" cpu

Subscribers: llvm-commits

Completion of http://reviews.llvm.org/rL233811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233903 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r233595, "MC: For variable symbols, maintain MCSymbol::Section as a cache."
Peter Collingbourne [Thu, 2 Apr 2015 07:02:51 +0000 (07:02 +0000)]
Revert r233595, "MC: For variable symbols, maintain MCSymbol::Section as a cache."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233898 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Fix local-linkage handling in the CompileOnDemand layer.
Lang Hames [Thu, 2 Apr 2015 05:28:10 +0000 (05:28 +0000)]
[Orc] Fix local-linkage handling in the CompileOnDemand layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233895 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[gcroot] Remove unused items from an enum
Philip Reames [Thu, 2 Apr 2015 05:02:16 +0000 (05:02 +0000)]
[gcroot] Remove unused items from an enum

These two were never implemented for gcroot, so there's no point in keeping them around now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233892 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTeach gcroot how to handle dynamically realigned frames
Philip Reames [Thu, 2 Apr 2015 05:00:40 +0000 (05:00 +0000)]
Teach gcroot how to handle dynamically realigned frames

I'm playing with supporting custom stack map formats with statepoints.  While
doing so, I noticed that the existing implementation didn't indicate inherently
unsized frames.  This change essentially just ports the functionality that already
exists for the default StackMaps section to custom stackmaps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233891 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Increment epoch from DenseMap::swap.
Sanjoy Das [Thu, 2 Apr 2015 04:58:12 +0000 (04:58 +0000)]
[ADT] Increment epoch from DenseMap::swap.

Swapping DenseMap A with DenseMap B invalidates iterators pointing into
both A and B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233890 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Remove dead code.
Sanjoy Das [Thu, 2 Apr 2015 04:58:08 +0000 (04:58 +0000)]
[ADT] Remove dead code.

Nothing is using DenseMapBase::swap.  Besides it does not compile in its
current form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233889 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopAccesses] Remove unused global variables in tests
Adam Nemet [Thu, 2 Apr 2015 04:42:51 +0000 (04:42 +0000)]
[LoopAccesses] Remove unused global variables in tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233887 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Add support classes for inspecting and running C++ static ctor/dtors, and
Lang Hames [Thu, 2 Apr 2015 04:34:45 +0000 (04:34 +0000)]
[Orc] Add support classes for inspecting and running C++ static ctor/dtors, and
use these to add support for C++ static ctors/dtors to the Orc-lazy JIT in LLI.

Replace the trivial_retval_1 regression test - the new 'hello' test is covering
strictly more code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233885 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't print an error message when looking up the scheduling model if user specified...
Craig Topper [Thu, 2 Apr 2015 04:27:50 +0000 (04:27 +0000)]
Don't print an error message when looking up the scheduling model if user specified -mcpu=help.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233884 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a bug indicated by -fsanitize=shift-exponent.
Alexey Samsonov [Thu, 2 Apr 2015 01:30:10 +0000 (01:30 +0000)]
Fix a bug indicated by -fsanitize=shift-exponent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233881 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMark this inline properly
Daniel Berlin [Thu, 2 Apr 2015 00:03:15 +0000 (00:03 +0000)]
Mark this inline properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233870 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReturn iterator from Instruction::eraseFromParent.
Daniel Berlin [Thu, 2 Apr 2015 00:03:07 +0000 (00:03 +0000)]
Return iterator from Instruction::eraseFromParent.

Summary:
This is necessary in order to make removal while using reverse iterators work.

(See http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/084122.html)

Updates to other eraseFromParent's to come in later patches.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233869 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTableGen: Generate more const goodness
Matthias Braun [Wed, 1 Apr 2015 22:09:55 +0000 (22:09 +0000)]
TableGen: Generate more const goodness

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233857 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix sanitizer-x86_64-linux-fast failure that was not deleting the bindtable.
Kevin Enderby [Wed, 1 Apr 2015 21:50:45 +0000 (21:50 +0000)]
Fix sanitizer-x86_64-linux-fast failure that was not deleting the bindtable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233856 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] document the -tokens flag. Also change the diagnostic output
Kostya Serebryany [Wed, 1 Apr 2015 21:33:20 +0000 (21:33 +0000)]
[fuzzer] document the -tokens flag. Also change the diagnostic output

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233842 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove declarations for nonexistent methods
Matthias Braun [Wed, 1 Apr 2015 21:16:02 +0000 (21:16 +0000)]
Remove declarations for nonexistent methods

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233841 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd the option -objc-meta-data to llvm-objdump used with -macho to
Kevin Enderby [Wed, 1 Apr 2015 20:57:01 +0000 (20:57 +0000)]
Add the option -objc-meta-data to llvm-objdump used with -macho to
print the Objective-C runtime meta data for Mach-O files.

There are three types of Objective-C runtime meta data, Objc2 64-bit,
Objc2 32-bit and Objc1 32-bit.  This prints the first of these types. The
changes to print the others will follow next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233840 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Don't accidentally select shll $1, %eax when shrinking an immediate.
Benjamin Kramer [Wed, 1 Apr 2015 19:01:09 +0000 (19:01 +0000)]
[X86] Don't accidentally select shll $1, %eax when shrinking an immediate.

addl has higher throughput and this was needlessly picking a suboptimal
encoding causing PR23098.

I wish there was a way of doing this without further duplicating tbl-
generated patterns, but so far I haven't found one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233832 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Look at backedge dominating conditions (re-land r233447).
Sanjoy Das [Wed, 1 Apr 2015 18:24:06 +0000 (18:24 +0000)]
[SCEV] Look at backedge dominating conditions (re-land r233447).

Summary:
This change teaches ScalarEvolution::isLoopBackedgeGuardedByCond to look
at edges within the loop body that dominate the latch.  We don't do an
exhaustive search for all possible edges, but only a quick walk up the
dom tree.

This re-lands r233447.  r233447 was reverted because it caused massive
compile-time regressions.  This change has a fix for the same issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233829 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove 4,096 loop scale limitation.
Diego Novillo [Wed, 1 Apr 2015 17:42:27 +0000 (17:42 +0000)]
Remove 4,096 loop scale limitation.

Summary:
This is part 1 of fixes to address the problems described in
https://llvm.org/bugs/show_bug.cgi?id=22719.

The restriction to limit loop scales to 4,096 does not really prevent
overflows anymore, as the underlying algorithm has changed and does
not seem to suffer from this problem.

Additionally, artificially restricting loop scales to such a low number
skews frequency information, making loops of equal hotness appear to
have very different hotness properties.

The only loops that are artificially restricted to a scale of 4096 are
infinite loops (those loops with an exit mass of 0). This prevents
infinite loops from skewing the frequencies of other regions in the CFG.

At the end of propagation, frequencies are scaled to values that take no
more than 64 bits to represent. When the range of frequencies to be
represented fits within 61 bits, it pushes up the scaling factor to a
minimum of 8 to better distinguish small frequency values. Otherwise,
small frequency values are all saturated down at 1.

Tested on x86_64.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8718

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233826 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix WinEHPrepare bug with multiple catch handlers
Andrew Kaylor [Wed, 1 Apr 2015 17:21:25 +0000 (17:21 +0000)]
Fix WinEHPrepare bug with multiple catch handlers

Differential Revision: http://reviews.llvm.org/D8682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233824 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Rename v8.1a from "extension" to "architecture"
Vladimir Sukharev [Wed, 1 Apr 2015 14:54:56 +0000 (14:54 +0000)]
[ARM] Rename v8.1a from "extension" to "architecture"

v8.1a is renamed to architecture, following current entity naming approach.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233811 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Rename v8.1a from "extension" to "architecture"
Vladimir Sukharev [Wed, 1 Apr 2015 14:49:29 +0000 (14:49 +0000)]
[AArch64] Rename v8.1a from "extension" to "architecture"

v8.1a is renamed to architecture, accordingly to approaches in ARM backend.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233810 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agogit-clang-format r233603.
Rafael Espindola [Wed, 1 Apr 2015 14:44:59 +0000 (14:44 +0000)]
git-clang-format r233603.

Thanks to Meador Inge for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233808 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Support transactional execution on zEC12
Ulrich Weigand [Wed, 1 Apr 2015 12:51:43 +0000 (12:51 +0000)]
[SystemZ] Support transactional execution on zEC12

The zEC12 provides the transactional-execution facility.  This is exposed
to users via a set of builtin routines on other compilers.  This patch
adds LLVM support to enable those builtins.  In partciular, the patch:

- adds the transactional-execution and processor-assist facilities
- adds MC support for all instructions provided by those facilities
- adds LLVM intrinsics for those instructions and hooks them up for CodeGen
- adds CodeGen support to optimize CC return value checking

Since this is first use of target-specific intrinsics on the platform,
the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and
hooks it up in Intrinsics.td.  I've also changed Triple::getArchTypePrefix
to return "s390" instead of "systemz", since the naming convention for
GCC intrinsics uses "s390" on the platform, and it neemed more straight-
forward to use the same convention for LLVM IR intrinsics.

An associated clang patch makes the intrinsics (and command line switches)
available at the source-language level.

For reference, the transactional-execution instructions are documented
in the z/Architecture Principles of Operation for the zEC12:
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf
The associated builtins are documented in the GCC manual:
http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html

Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td
+++ llvm-head/lib/Target/SystemZ/SystemZOperators.td
@@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic       : SDTypeProf
 def SDT_ZPrefetch           : SDTypeProfile<0, 2,
                                             [SDTCisVT<0, i32>,
                                              SDTCisPtrTy<1>]>;
+def SDT_ZTBegin             : SDTypeProfile<0, 2,
+                                            [SDTCisPtrTy<0>,
+                                             SDTCisVT<1, i32>]>;

 //===----------------------------------------------------------------------===//
 // Node definitions
@@ -180,6 +183,15 @@ def z_prefetch          : SDNode<"System
                                  [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
                                   SDNPMemOperand]>;

+def z_tbegin            : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tbegin_nofloat    : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tend              : SDNode<"SystemZISD::TEND", SDTNone,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
+
 //===----------------------------------------------------------------------===//
 // Pattern fragments
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i
   let Inst{15-0}  = BD2;
 }

+class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<4, outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  field bits<32> SoftFail = 0;
+
+  bits<16> BD2;
+
+  let Inst{31-16} = op;
+  let Inst{15-0}  = BD2;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1362,6 +1362,60 @@ let Defs = [CC] in {
 }

 //===----------------------------------------------------------------------===//
+// Transactional execution
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureTransactionalExecution] in {
+  // Transaction Begin
+  let hasSideEffects = 1, mayStore = 1,
+      usesCustomInserter = 1, Defs = [CC] in {
+    def TBEGIN : InstSIL<0xE560,
+                         (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                         "tbegin\t$BD1, $I2",
+                         [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
+    def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                                [(z_tbegin_nofloat bdaddr12only:$BD1,
+                                                   imm32zx16:$I2)]>;
+    def TBEGINC : InstSIL<0xE561,
+                          (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                          "tbeginc\t$BD1, $I2",
+                          [(int_s390_tbeginc bdaddr12only:$BD1,
+                                             imm32zx16:$I2)]>;
+  }
+
+  // Transaction End
+  let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
+    def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
+
+  // Transaction Abort
+  let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
+    def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
+                       "tabort\t$BD2",
+                       [(int_s390_tabort bdaddr12only:$BD2)]>;
+
+  // Nontransactional Store
+  let hasSideEffects = 1 in
+    def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
+
+  // Extract Transaction Nesting Depth
+  let hasSideEffects = 1 in
+    def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor assist
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureProcessorAssist] in {
+  let hasSideEffects = 1, R4 = 0 in
+    def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
+                      "ppa\t$R1, $R2, $R3", []>;
+  def : Pat<(int_s390_ppa_txassist GR32:$src),
+            (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
+                 0, 1)>;
+}
+
+//===----------------------------------------------------------------------===//
 // Miscellaneous Instructions.
 //===----------------------------------------------------------------------===//

Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td
+++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td
@@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys
   "Assume that the miscellaneous-extensions facility is installed"
 >;

+def FeatureTransactionalExecution : SystemZFeature<
+  "transactional-execution", "TransactionalExecution",
+  "Assume that the transactional-execution facility is installed"
+>;
+
+def FeatureProcessorAssist : SystemZFeature<
+  "processor-assist", "ProcessorAssist",
+  "Assume that the processor-assist facility is installed"
+>;
+
 def : Processor<"generic", NoItineraries, []>;
 def : Processor<"z10", NoItineraries, []>;
 def : Processor<"z196", NoItineraries,
@@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1,
-                 FeatureMiscellaneousExtensions]>;
+                 FeatureMiscellaneousExtensions,
+                 FeatureTransactionalExecution, FeatureProcessorAssist]>;
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
+      HasTransactionalExecution(false), HasProcessorAssist(false),
       TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}

Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
@@ -42,6 +42,8 @@ protected:
   bool HasFastSerialization;
   bool HasInterlockedAccess1;
   bool HasMiscellaneousExtensions;
+  bool HasTransactionalExecution;
+  bool HasProcessorAssist;

 private:
   Triple TargetTriple;
@@ -102,6 +104,12 @@ public:
     return HasMiscellaneousExtensions;
   }

+  // Return true if the target has the transactional-execution facility.
+  bool hasTransactionalExecution() const { return HasTransactionalExecution; }
+
+  // Return true if the target has the processor-assist facility.
+  bool hasProcessorAssist() const { return HasProcessorAssist; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Index: llvm-head/lib/Support/Triple.cpp
===================================================================
--- llvm-head.orig/lib/Support/Triple.cpp
+++ llvm-head/lib/Support/Triple.cpp
@@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar
   case sparcv9:
   case sparc:       return "sparc";

-  case systemz:     return "systemz";
+  case systemz:     return "s390";

   case x86:
   case x86_64:      return "x86";
Index: llvm-head/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm-head.orig/include/llvm/IR/Intrinsics.td
+++ llvm-head/include/llvm/IR/Intrinsics.td
@@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsR600.td"
 include "llvm/IR/IntrinsicsBPF.td"
+include "llvm/IR/IntrinsicsSystemZ.td"
Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
===================================================================
--- /dev/null
+++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
@@ -0,0 +1,46 @@
+//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the SystemZ-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Transactional-execution intrinsics
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "s390" in {
+  def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+                                  [IntrNoDuplicate]>;
+
+  def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
+                                          [llvm_ptr_ty, llvm_i32_ty],
+                                          [IntrNoDuplicate]>;
+
+  def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+                                   [IntrNoDuplicate]>;
+
+  def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
+                                  [IntrNoReturn, Throws]>;
+
+  def int_s390_tend : GCCBuiltin<"__builtin_tend">,
+                      Intrinsic<[llvm_i32_ty], []>;
+
+  def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
+                      Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+
+  def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
+                                 [IntrReadWriteArgMem]>;
+
+  def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
+                              Intrinsic<[], [llvm_i32_ty]>;
+}
+
Index: llvm-head/lib/Target/SystemZ/SystemZ.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZ.h
+++ llvm-head/lib/Target/SystemZ/SystemZ.h
@@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0       = C
 const unsigned CCMASK_TM_MSB_1       = CCMASK_2 | CCMASK_3;
 const unsigned CCMASK_TM             = CCMASK_ANY;

+// Condition-code mask assignments for TRANSACTION_BEGIN.
+const unsigned CCMASK_TBEGIN_STARTED       = CCMASK_0;
+const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
+const unsigned CCMASK_TBEGIN_TRANSIENT     = CCMASK_2;
+const unsigned CCMASK_TBEGIN_PERSISTENT    = CCMASK_3;
+const unsigned CCMASK_TBEGIN               = CCMASK_ANY;
+
+// Condition-code mask assignments for TRANSACTION_END.
+const unsigned CCMASK_TEND_TX   = CCMASK_0;
+const unsigned CCMASK_TEND_NOTX = CCMASK_2;
+const unsigned CCMASK_TEND      = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
+
 // The position of the low CC bit in an IPM result.
 const unsigned IPM_CC = 28;

Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
@@ -146,6 +146,15 @@ enum {
   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
   SERIALIZE,

+  // Transaction begin.  The first operand is the chain, the second
+  // the TDB pointer, and the third the immediate control field.
+  // Returns chain and glue.
+  TBEGIN,
+  TBEGIN_NOFLOAT,
+
+  // Transaction end.  Just the chain operand.  Returns chain and glue.
+  TEND,
+
   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
   // ATOMIC_LOAD_<op>.
   //
@@ -318,6 +327,7 @@ private:
   SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;

   // If the last instruction before MBBI in MBB was some form of COMPARE,
   // try to replace it with a COMPARE AND BRANCH just before MBBI.
@@ -355,6 +365,10 @@ private:
   MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
                                        MachineBasicBlock *BB,
                                        unsigned Opcode) const;
+  MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
+                                          MachineBasicBlock *MBB,
+                                          unsigned Opcode,
+                                          bool NoFloat) const;
 };
 } // end namespace llvm

Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -20,6 +20,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/IR/Intrinsics.h"
 #include <cctype>

 using namespace llvm;
@@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe
   // Codes for which we want to perform some z-specific combinations.
   setTargetDAGCombine(ISD::SIGN_EXTEND);

+  // Handle intrinsics.
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+
   // We want to use MVC in preference to even a single load/store pair.
   MaxStoresPerMemcpy = 0;
   MaxStoresPerMemcpyOptSize = 0;
@@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai
   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
 }

+// Return true if Op is an intrinsic node with chain that returns the CC value
+// as its only (other) argument.  Provide the associated SystemZISD opcode and
+// the mask of valid CC values if so.
+static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
+                                      unsigned &CCValid) {
+  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  switch (Id) {
+  case Intrinsic::s390_tbegin:
+    Opcode = SystemZISD::TBEGIN;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tbegin_nofloat:
+    Opcode = SystemZISD::TBEGIN_NOFLOAT;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tend:
+    Opcode = SystemZISD::TEND;
+    CCValid = SystemZ::CCMASK_TEND;
+    return true;
+
+  default:
+    return false;
+  }
+}
+
+// Emit an intrinsic with chain with a glued value instead of its CC result.
+static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
+                                             unsigned Opcode) {
+  // Copy all operands except the intrinsic ID.
+  unsigned NumOps = Op.getNumOperands();
+  SmallVector<SDValue, 6> Ops;
+  Ops.reserve(NumOps - 1);
+  Ops.push_back(Op.getOperand(0));
+  for (unsigned I = 2; I < NumOps; ++I)
+    Ops.push_back(Op.getOperand(I));
+
+  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+  SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
+  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
+  SDValue OldChain = SDValue(Op.getNode(), 1);
+  SDValue NewChain = SDValue(Intr.getNode(), 0);
+  DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
+  return Intr;
+}
+
 // CC is a comparison that will be implemented using an integer or
 // floating-point comparison.  Return the condition code mask for
 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
@@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec
   C.CCMask = NewCCMask;
 }

+// Return a Comparison that tests the condition-code result of intrinsic
+// node Call against constant integer CC using comparison code Cond.
+// Opcode is the opcode of the SystemZISD operation for the intrinsic
+// and CCValid is the set of possible condition-code results.
+static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
+                                  SDValue Call, unsigned CCValid, uint64_t CC,
+                                  ISD::CondCode Cond) {
+  Comparison C(Call, SDValue());
+  C.Opcode = Opcode;
+  C.CCValid = CCValid;
+  if (Cond == ISD::SETEQ)
+    // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
+    C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
+  else if (Cond == ISD::SETNE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
+  else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
+    // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
+  else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
+  else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
+    // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
+  else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
+  else
+    llvm_unreachable("Unexpected integer comparison type");
+  C.CCMask &= CCValid;
+  return C;
+}
+
 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
                          ISD::CondCode Cond) {
+  if (CmpOp1.getOpcode() == ISD::Constant) {
+    uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
+    unsigned Opcode, CCValid;
+    if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
+        CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
+        isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
+      return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
+  }
   Comparison C(CmpOp0, CmpOp1);
   C.CCMask = CCMaskForCondCode(Cond);
   if (C.Op0.getValueType().isFloatingPoint()) {
@@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D

 // Emit the comparison instruction described by C.
 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
+  if (!C.Op1.getNode()) {
+    SDValue Op;
+    switch (C.Op0.getOpcode()) {
+    case ISD::INTRINSIC_W_CHAIN:
+      Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
+      break;
+    default:
+      llvm_unreachable("Invalid comparison operands");
+    }
+    return SDValue(Op.getNode(), Op->getNumValues() - 1);
+  }
   if (C.Opcode == SystemZISD::ICMP)
     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
                        DAG.getConstant(C.ICmpType, MVT::i32));
@@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC
 }

 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
-  SDValue Chain    = Op.getOperand(0);
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
   SDValue CmpOp0   = Op.getOperand(2);
   SDValue CmpOp1   = Op.getOperand(3);
@@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C
   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
   SDValue Glue = emitCmp(DAG, DL, C);
   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
-                     Chain, DAG.getConstant(C.CCValid, MVT::i32),
+                     Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
 }

@@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF
                                  Node->getMemoryVT(), Node->getMemOperand());
 }

+// Return an i32 that contains the value of CC immediately after After,
+// whose final operand must be MVT::Glue.
+static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
+  SDValue Glue = SDValue(After, After->getNumValues() - 1);
+  SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
+  return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
+                     DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
+}
+
+SDValue
+SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  unsigned Opcode, CCValid;
+  if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
+    assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+    SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
+    SDValue CC = getCCResult(DAG, Glued.getNode());
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
+    return SDValue();
+  }
+
+  return SDValue();
+}
+
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
@@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper
     return lowerSTACKRESTORE(Op, DAG);
   case ISD::PREFETCH:
     return lowerPREFETCH(Op, DAG);
+  case ISD::INTRINSIC_W_CHAIN:
+    return lowerINTRINSIC_W_CHAIN(Op, DAG);
   default:
     llvm_unreachable("Unexpected node to lower");
   }
@@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa
     OPCODE(SEARCH_STRING);
     OPCODE(IPM);
     OPCODE(SERIALIZE);
+    OPCODE(TBEGIN);
+    OPCODE(TBEGIN_NOFLOAT);
+    OPCODE(TEND);
     OPCODE(ATOMIC_SWAPW);
     OPCODE(ATOMIC_LOADW_ADD);
     OPCODE(ATOMIC_LOADW_SUB);
@@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper
   return DoneMBB;
 }

+// Update TBEGIN instruction with final opcode and register clobbers.
+MachineBasicBlock *
+SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
+                                            MachineBasicBlock *MBB,
+                                            unsigned Opcode,
+                                            bool NoFloat) const {
+  MachineFunction &MF = *MBB->getParent();
+  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
+  const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
+
+  // Update opcode.
+  MI->setDesc(TII->get(Opcode));
+
+  // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
+  // Make sure to add the corresponding GRSM bits if they are missing.
+  uint64_t Control = MI->getOperand(2).getImm();
+  static const unsigned GPRControlBit[16] = {
+    0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
+    0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
+  };
+  Control |= GPRControlBit[15];
+  if (TFI->hasFP(MF))
+    Control |= GPRControlBit[11];
+  MI->getOperand(2).setImm(Control);
+
+  // Add GPR clobbers.
+  for (int I = 0; I < 16; I++) {
+    if ((Control & GPRControlBit[I]) == 0) {
+      unsigned Reg = SystemZMC::GR64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  // Add FPR clobbers.
+  if (!NoFloat && (Control & 4) != 0) {
+    for (int I = 0; I < 16; I++) {
+      unsigned Reg = SystemZMC::FP64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  return MBB;
+}
+
 MachineBasicBlock *SystemZTargetLowering::
 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
   switch (MI->getOpcode()) {
@@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr
     return emitStringWrapper(MI, MBB, SystemZ::MVST);
   case SystemZ::SRSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::SRST);
+  case SystemZ::TBEGIN:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
+  case SystemZ::TBEGIN_nofloat:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
+  case SystemZ::TBEGINC:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
   default:
     llvm_unreachable("Unexpected instr type to insert");
   }
Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -0,0 +1,352 @@
+; Test transactional-execution intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+declare i32 @llvm.s390.tbegin(i8 *, i32)
+declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
+declare void @llvm.s390.tbeginc(i8 *, i32)
+declare i32 @llvm.s390.tend()
+declare void @llvm.s390.tabort(i64)
+declare void @llvm.s390.ntstg(i64, i64 *)
+declare i32 @llvm.s390.etnd()
+declare void @llvm.s390.ppa.txassist(i32)
+
+; TBEGIN.
+define void @test_tbegin() {
+; CHECK-LABEL: test_tbegin:
+; CHECK-NOT: stmg
+; CHECK: std %f8,
+; CHECK: std %f9,
+; CHECK: std %f10,
+; CHECK: std %f11,
+; CHECK: std %f12,
+; CHECK: std %f13,
+; CHECK: std %f14,
+; CHECK: std %f15,
+; CHECK: tbegin 0, 65292
+; CHECK: ld %f8,
+; CHECK: ld %f9,
+; CHECK: ld %f10,
+; CHECK: ld %f11,
+; CHECK: ld %f12,
+; CHECK: ld %f13,
+; CHECK: ld %f14,
+; CHECK: ld %f15,
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat).
+define void @test_tbegin_nofloat1() {
+; CHECK-LABEL: test_tbegin_nofloat1:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with integer CC return value.
+define i32 @test_tbegin_nofloat2() {
+; CHECK-LABEL: test_tbegin_nofloat2:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with implicit CC check.
+define void @test_tbegin_nofloat3(i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat3:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: jnh  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TBEGIN (nofloat) with dual CC use.
+define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat4:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with register.
+define void @test_tbegin_nofloat5(i8 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat5:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0(%r2), 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0x0f00.
+define void @test_tbegin_nofloat6() {
+; CHECK-LABEL: test_tbegin_nofloat6:
+; CHECK: stmg %r6, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 3840
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xf100.
+define void @test_tbegin_nofloat7() {
+; CHECK-LABEL: test_tbegin_nofloat7:
+; CHECK: stmg %r8, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 61696
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
+define void @test_tbegin_nofloat8() {
+; CHECK-LABEL: test_tbegin_nofloat8:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
+define void @test_tbegin_nofloat9() {
+; CHECK-LABEL: test_tbegin_nofloat9:
+; CHECK: stmg %r10, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 64256
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
+define void @test_tbegin_nofloat10(i64 %n) {
+; CHECK-LABEL: test_tbegin_nofloat10:
+; CHECK: stmg %r11, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  %buf = alloca i8, i64 %n
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGINC.
+define void @test_tbeginc() {
+; CHECK-LABEL: test_tbeginc:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbeginc 0, 65288
+; CHECK: br %r14
+  call void @llvm.s390.tbeginc(i8 *null, i32 65288)
+  ret void
+}
+
+; TEND with integer CC return value.
+define i32 @test_tend1() {
+; CHECK-LABEL: test_tend1:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  ret i32 %res
+}
+
+; TEND with implicit CC check.
+define void @test_tend3(i32 *%ptr) {
+; CHECK-LABEL: test_tend3:
+; CHECK: tend
+; CHECK: je  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TEND with dual CC use.
+define i32 @test_tend2(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tend2:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TABORT with register only.
+define void @test_tabort1(i64 %val) {
+; CHECK-LABEL: test_tabort1:
+; CHECK: tabort 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 %val)
+  ret void
+}
+
+; TABORT with immediate only.
+define void @test_tabort2(i64 %val) {
+; CHECK-LABEL: test_tabort2:
+; CHECK: tabort 1234
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 1234)
+  ret void
+}
+
+; TABORT with register + immediate.
+define void @test_tabort3(i64 %val) {
+; CHECK-LABEL: test_tabort3:
+; CHECK: tabort 1234(%r2)
+; CHECK: br %r14
+  %sum = add i64 %val, 1234
+  call void @llvm.s390.tabort(i64 %sum)
+  ret void
+}
+
+; TABORT with out-of-range immediate.
+define void @test_tabort4(i64 %val) {
+; CHECK-LABEL: test_tabort4:
+; CHECK: tabort 0({{%r[1-5]}})
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 4096)
+  ret void
+}
+
+; NTSTG with base pointer only.
+define void @test_ntstg1(i64 *%ptr, i64 %val) {
+; CHECK-LABEL: test_ntstg1:
+; CHECK: ntstg %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with base and index.
+; Check that VSTL doesn't allow an index.
+define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
+; CHECK-LABEL: test_ntstg2:
+; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
+; CHECK: ntstg %r4, 0([[REG]],%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 %index
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the highest in-range displacement.
+define void @test_ntstg3(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg3:
+; CHECK: ntstg %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range positive displacement.
+define void @test_ntstg4(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg4:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the lowest in-range displacement.
+define void @test_ntstg5(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg5:
+; CHECK: ntstg %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range negative displacement.
+define void @test_ntstg6(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg6:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; ETND.
+define i32 @test_etnd() {
+; CHECK-LABEL: test_etnd:
+; CHECK: etnd %r2
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.etnd()
+  ret i32 %res
+}
+
+; PPA (Transaction-Abort Assist)
+define void @test_ppa_txassist(i32 %val) {
+; CHECK-LABEL: test_ppa_txassist:
+; CHECK: ppa %r2, 0, 1
+; CHECK: br %r14
+  call void @llvm.s390.ppa.txassist(i32 %val)
+  ret void
+}
+
Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
@@ -3,6 +3,22 @@
 # RUN: FileCheck < %t %s

 #CHECK: error: invalid operand
+#CHECK: ntstg %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ntstg %r0, 524288
+
+ ntstg %r0, -524289
+ ntstg %r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, 16
+
+ ppa %r0, %r0, -1
+ ppa %r0, %r0, 16
+
+#CHECK: error: invalid operand
 #CHECK: risbgn %r0,%r0,0,0,-1
 #CHECK: error: invalid operand
 #CHECK: risbgn %r0,%r0,0,0,64
@@ -22,3 +38,47 @@
  risbgn %r0,%r0,-1,0,0
  risbgn %r0,%r0,256,0,0

+#CHECK: error: invalid operand
+#CHECK: tabort -1
+#CHECK: error: invalid operand
+#CHECK: tabort 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tabort 0(%r1,%r2)
+
+ tabort -1
+ tabort 4096
+ tabort 0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: tbegin -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbegin 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, 65536
+
+ tbegin -1, 0
+ tbegin 4096, 0
+ tbegin 0(%r1,%r2), 0
+ tbegin 0, -1
+ tbegin 0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: tbeginc -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbeginc 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, 65536
+
+ tbeginc -1, 0
+ tbeginc 4096, 0
+ tbeginc 0(%r1,%r2), 0
+ tbeginc 0, -1
+ tbeginc 0, 65536
Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s
@@ -1,6 +1,48 @@
 # For zEC12 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s

+#CHECK: etnd %r0                     # encoding: [0xb2,0xec,0x00,0x00]
+#CHECK: etnd %r15                    # encoding: [0xb2,0xec,0x00,0xf0]
+#CHECK: etnd %r7                     # encoding: [0xb2,0xec,0x00,0x70]
+
+ etnd %r0
+ etnd %r15
+ etnd %r7
+
+#CHECK: ntstg %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
+#CHECK: ntstg %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
+#CHECK: ntstg %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
+#CHECK: ntstg %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
+#CHECK: ntstg %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
+
+ ntstg %r0, -524288
+ ntstg %r0, -1
+ ntstg %r0, 0
+ ntstg %r0, 1
+ ntstg %r0, 524287
+ ntstg %r0, 0(%r1)
+ ntstg %r0, 0(%r15)
+ ntstg %r0, 524287(%r1,%r15)
+ ntstg %r0, 524287(%r15,%r1)
+ ntstg %r15, 0
+
+#CHECK: ppa %r0, %r0, 0             # encoding: [0xb2,0xe8,0x00,0x00]
+#CHECK: ppa %r0, %r0, 15            # encoding: [0xb2,0xe8,0xf0,0x00]
+#CHECK: ppa %r0, %r15, 0            # encoding: [0xb2,0xe8,0x00,0x0f]
+#CHECK: ppa %r4, %r6, 7             # encoding: [0xb2,0xe8,0x70,0x46]
+#CHECK: ppa %r15, %r0, 0            # encoding: [0xb2,0xe8,0x00,0xf0]
+
+ ppa %r0, %r0, 0
+ ppa %r0, %r0, 15
+ ppa %r0, %r15, 0
+ ppa %r4, %r6, 7
+ ppa %r15, %r0, 0
+
 #CHECK: risbgn %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
 #CHECK: risbgn %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
 #CHECK: risbgn %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
@@ -17,3 +59,68 @@
  risbgn %r15,%r0,0,0,0
  risbgn %r4,%r5,6,7,8

+#CHECK: tabort 0                       # encoding: [0xb2,0xfc,0x00,0x00]
+#CHECK: tabort 0(%r1)                  # encoding: [0xb2,0xfc,0x10,0x00]
+#CHECK: tabort 0(%r15)                 # encoding: [0xb2,0xfc,0xf0,0x00]
+#CHECK: tabort 4095                    # encoding: [0xb2,0xfc,0x0f,0xff]
+#CHECK: tabort 4095(%r1)               # encoding: [0xb2,0xfc,0x1f,0xff]
+#CHECK: tabort 4095(%r15)              # encoding: [0xb2,0xfc,0xff,0xff]
+
+ tabort 0
+ tabort 0(%r1)
+ tabort 0(%r15)
+ tabort 4095
+ tabort 4095(%r1)
+ tabort 4095(%r15)
+
+#CHECK: tbegin 0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 4095, 0                 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
+#CHECK: tbegin 0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 0, 1                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
+#CHECK: tbegin 0, 32767                # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
+#CHECK: tbegin 0, 32768                # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
+#CHECK: tbegin 0, 65535                # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
+#CHECK: tbegin 0(%r1), 42              # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
+#CHECK: tbegin 0(%r15), 42             # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
+#CHECK: tbegin 4095(%r1), 42           # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
+#CHECK: tbegin 4095(%r15), 42          # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
+
+ tbegin 0, 0
+ tbegin 4095, 0
+ tbegin 0, 0
+ tbegin 0, 1
+ tbegin 0, 32767
+ tbegin 0, 32768
+ tbegin 0, 65535
+ tbegin 0(%r1), 42
+ tbegin 0(%r15), 42
+ tbegin 4095(%r1), 42
+ tbegin 4095(%r15), 42
+
+#CHECK: tbeginc 0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 4095, 0                 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
+#CHECK: tbeginc 0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 0, 1                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
+#CHECK: tbeginc 0, 32767                # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
+#CHECK: tbeginc 0, 32768                # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
+#CHECK: tbeginc 0, 65535                # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
+#CHECK: tbeginc 0(%r1), 42              # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
+#CHECK: tbeginc 0(%r15), 42             # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
+#CHECK: tbeginc 4095(%r1), 42           # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
+#CHECK: tbeginc 4095(%r15), 42          # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
+
+ tbeginc 0, 0
+ tbeginc 4095, 0
+ tbeginc 0, 0
+ tbeginc 0, 1
+ tbeginc 0, 32767
+ tbeginc 0, 32768
+ tbeginc 0, 65535
+ tbeginc 0(%r1), 42
+ tbeginc 0(%r15), 42
+ tbeginc 4095(%r1), 42
+ tbeginc 4095(%r15), 42
+
+#CHECK: tend                            # encoding: [0xb2,0xf8,0x00,0x00]
+
+ tend
Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s
+++ llvm-head/test/MC/SystemZ/insn-bad-z196.s
@@ -244,6 +244,11 @@
  cxlgbr %f0, 16, %r0, 0
  cxlgbr %f2, 0, %r0, 0

+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: etnd %r7
+
+ etnd %r7
+
 #CHECK: error: invalid operand
 #CHECK: fidbra %f0, 0, %f0, -1
 #CHECK: error: invalid operand
@@ -546,6 +551,16 @@
  locr %r0,%r0,-1
  locr %r0,%r0,16

+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: ntstg %r0, 524287(%r1,%r15)
+
+ ntstg %r0, 524287(%r1,%r15)
+
+#CHECK: error: {{(instruction requires: processor-assist)?}}
+#CHECK: ppa %r4, %r6, 7
+
+ ppa %r4, %r6, 7
+
 #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
 #CHECK: risbgn %r1, %r2, 0, 0, 0

@@ -690,3 +705,24 @@
  stocg %r0,-524289,1
  stocg %r0,524288,1
  stocg %r0,0(%r1,%r2),1
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tabort 4095(%r1)
+
+ tabort 4095(%r1)
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbegin 4095(%r1), 42
+
+ tbegin 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbeginc 4095(%r1), 42
+
+ tbeginc 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tend
+
+ tend
+
Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt
===================================================================
--- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt
+++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt
@@ -2503,6 +2503,15 @@
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff

+# CHECK: etnd %r0
+0xb2 0xec 0x00 0x00
+
+# CHECK: etnd %r15
+0xb2 0xec 0x00 0xf0
+
+# CHECK: etnd %r7
+0xb2 0xec 0x00 0x70
+
 # CHECK: fidbr %f0, 0, %f0
 0xb3 0x5f 0x00 0x00

@@ -6034,6 +6043,36 @@
 # CHECK: ny %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x54

+# CHECK: ntstg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x25
+
+# CHECK: ntstg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x25
+
+# CHECK: ntstg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x25
+
+# CHECK: ntstg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x25
+
 # CHECK: oc 0(1), 0
 0xd6 0x00 0x00 0x00 0x00 0x00

@@ -6346,6 +6385,21 @@
 # CHECK: popcnt %r7, %r8
 0xb9 0xe1 0x00 0x78

+# CHECK: ppa %r0, %r0, 0
+0xb2 0xe8 0x00 0x00
+
+# CHECK: ppa %r0, %r0, 15
+0xb2 0xe8 0xf0 0x00
+
+# CHECK: ppa %r0, %r15, 0
+0xb2 0xe8 0x00 0x0f
+
+# CHECK: ppa %r4, %r6, 7
+0xb2 0xe8 0x70 0x46
+
+# CHECK: ppa %r15, %r0, 0
+0xb2 0xe8 0x00 0xf0
+
 # CHECK: risbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x55

@@ -8062,6 +8116,93 @@
 # CHECK: sy %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x5b

+# CHECK: tabort 0
+0xb2 0xfc 0x00 0x00
+
+# CHECK: tabort 0(%r1)
+0xb2 0xfc 0x10 0x00
+
+# CHECK: tabort 0(%r15)
+0xb2 0xfc 0xf0 0x00
+
+# CHECK: tabort 4095
+0xb2 0xfc 0x0f 0xff
+
+# CHECK: tabort 4095(%r1)
+0xb2 0xfc 0x1f 0xff
+
+# CHECK: tabort 4095(%r15)
+0xb2 0xfc 0xff 0xff
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 4095, 0
+0xe5 0x60 0x0f 0xff 0x00 0x00
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 0, 1
+0xe5 0x60 0x00 0x00 0x00 0x01
+
+# CHECK: tbegin 0, 32767
+0xe5 0x60 0x00 0x00 0x7f 0xff
+
+# CHECK: tbegin 0, 32768
+0xe5 0x60 0x00 0x00 0x80 0x00
+
+# CHECK: tbegin 0, 65535
+0xe5 0x60 0x00 0x00 0xff 0xff
+
+# CHECK: tbegin 0(%r1), 42
+0xe5 0x60 0x10 0x00 0x00 0x2a
+
+# CHECK: tbegin 0(%r15), 42
+0xe5 0x60 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbegin 4095(%r1), 42
+0xe5 0x60 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbegin 4095(%r15), 42
+0xe5 0x60 0xff 0xff 0x00 0x2a
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 4095, 0
+0xe5 0x61 0x0f 0xff 0x00 0x00
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 0, 1
+0xe5 0x61 0x00 0x00 0x00 0x01
+
+# CHECK: tbeginc 0, 32767
+0xe5 0x61 0x00 0x00 0x7f 0xff
+
+# CHECK: tbeginc 0, 32768
+0xe5 0x61 0x00 0x00 0x80 0x00
+
+# CHECK: tbeginc 0, 65535
+0xe5 0x61 0x00 0x00 0xff 0xff
+
+# CHECK: tbeginc 0(%r1), 42
+0xe5 0x61 0x10 0x00 0x00 0x2a
+
+# CHECK: tbeginc 0(%r15), 42
+0xe5 0x61 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r1), 42
+0xe5 0x61 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r15), 42
+0xe5 0x61 0xff 0xff 0x00 0x2a
+
+# CHECK: tend
+0xb2 0xf8 0x00 0x00
+
 # CHECK: tm 0, 0
 0x91 0x00 0x00 0x00

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233803 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTry to unbreak Clang build to export LLVM_ABI_BREAKING_CHECKS, fixup for r233310.
NAKAMURA Takumi [Wed, 1 Apr 2015 11:46:15 +0000 (11:46 +0000)]
Try to unbreak Clang build to export LLVM_ABI_BREAKING_CHECKS, fixup for r233310.

FIXME: Should ENABLE_ABI_BREAKING_CHECKS be tri-state, "ON/OFF/blank"?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233801 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd -mcpu=native support to opt.
Craig Topper [Wed, 1 Apr 2015 05:32:04 +0000 (05:32 +0000)]
Add -mcpu=native support to opt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233789 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Implement support for catch-all
David Majnemer [Wed, 1 Apr 2015 05:20:42 +0000 (05:20 +0000)]
[WinEH] Implement support for catch-all

A catch (...) doesn't have a type descriptor.  Instead, the 'adjectives'
field has bit six set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233788 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Reflect process symbols into the LLI Orc-lazy JIT.
Lang Hames [Wed, 1 Apr 2015 04:42:56 +0000 (04:42 +0000)]
[Orc] Reflect process symbols into the LLI Orc-lazy JIT.

This makes symbol resolution essentially identical between MCJIT and the LLI
Orc-lazy JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233786 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Cache LLVM_ABI_BREAKING_CHECKS in LLVMConfig.cmake.
Sanjoy Das [Wed, 1 Apr 2015 03:16:10 +0000 (03:16 +0000)]
[CMake] Cache LLVM_ABI_BREAKING_CHECKS in LLVMConfig.cmake.

Not having this breaks clang builds that use an already-built LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233784 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix PR23065. Avoid optimizing bitcast of build_vector with constant input to scalar_t...
Jiangning Liu [Wed, 1 Apr 2015 01:52:38 +0000 (01:52 +0000)]
Fix PR23065. Avoid optimizing bitcast of build_vector with constant input to scalar_to_vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233778 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SimplifyLibCalls] Ignore nobuiltin/unavailable fortified libcalls.
Ahmed Bougacha [Wed, 1 Apr 2015 00:45:09 +0000 (00:45 +0000)]
[SimplifyLibCalls] Ignore nobuiltin/unavailable fortified libcalls.

We used to do this before refactorings around r225640.
Some clang users checked for _chk libcall availability using:
  __has_builtin(__builtin___memcpy_chk)
When compiling with -fno-builtin, this is always true.
When passing -ffreestanding/-mkernel, which both imply -fno-builtin, we
end up with fortified libcalls, which isn't acceptable in a freestanding
environment which only provides their non-fortified counterparts.

Until we change clang and/or teach external users to check for availability
differently, disregard the "nobuiltin" attribute and TLI::has.

Workaround for PR23093.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233776 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] FastISel can't handle i1 return values when using CR bits
Hal Finkel [Wed, 1 Apr 2015 00:40:48 +0000 (00:40 +0000)]
[PowerPC] FastISel can't handle i1 return values when using CR bits

Under normal circumstances, use of CR bits is disabled when running at -O0, but
it is enabled by default otherwise, and if you have optnone functions, they'll
still generally be generated with crbits turned on (because nothing else turns
them off). FastISel can't handle most things dealing with i1 values when using
CR bits, and checks for that, but was not checking the return type on
functions; we can't fast-isel function calls with i1 return values either when
using CR bits for boolean values.

Fixes PR22664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233775 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Fix typo.
Sean Silva [Tue, 31 Mar 2015 22:48:45 +0000 (22:48 +0000)]
[docs] Fix typo.

Based on a patch by Stanislav Manilov!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233771 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] ExitingScope is vacuously true if !PoppedCatches.empty()
David Majnemer [Tue, 31 Mar 2015 22:43:56 +0000 (22:43 +0000)]
[WinEH] ExitingScope is vacuously true if !PoppedCatches.empty()

Remove a redundant condition, no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233770 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Generate .xdata for catch handlers
David Majnemer [Tue, 31 Mar 2015 22:35:44 +0000 (22:35 +0000)]
[WinEH] Generate .xdata for catch handlers

This lets us catch exceptions in simple cases.

N.B. Things that do not work include (but are not limited to):
- Throwing from within a catch handler.
- Catching an object with a named catch parameter.
- 'CatchHigh' is fictitious, we aren't sure of its purpose.
- We aren't entirely efficient with regards to the number of EH states
  that we generate.
- IP-to-State tables are sensitive to the order of emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233767 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] more documentation
Kostya Serebryany [Tue, 31 Mar 2015 21:39:38 +0000 (21:39 +0000)]
[fuzzer] more documentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233763 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotypo; NFC
Sanjay Patel [Tue, 31 Mar 2015 21:24:47 +0000 (21:24 +0000)]
typo; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233761 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Rename replaceWithUniqued() tests from r233751
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 21:05:06 +0000 (21:05 +0000)]
IR: Rename replaceWithUniqued() tests from r233751

replaceWithUniquedUnresolved
replaceWithUniquedUnresolvedChangedOperand
 =>
replaceWithUniquedResolvingOperand
replaceWithUniquedChangingOperand

I find the new names less confusing; they're also more accurate.  Sorry
for the churn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233759 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVerifier: Add a testcase for verifying type refs
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 20:57:56 +0000 (20:57 +0000)]
Verifier: Add a testcase for verifying type refs

r233664 fixed the `Verifier` so that it doesn't crash on bad type refs.
This deserves a test!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233756 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Don't use a vector preferred memory type at -O0
Hal Finkel [Tue, 31 Mar 2015 20:56:09 +0000 (20:56 +0000)]
[PowerPC] Don't use a vector preferred memory type at -O0

Even at -O0, we fall back to SDAG when we hit intrinsics, and if the intrinsic
is a memset/memcpy/etc. we might normally use vector types. At -O0, this is
probably not a good idea (because, if there is a bug in the lowering code,
there would be no good way to turn it off). At -O0, only use scalar preferred
types.

Related to PR22754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233755 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Enable the codegenprepare optimization that promotes operation to form
Quentin Colombet [Tue, 31 Mar 2015 20:52:32 +0000 (20:52 +0000)]
[AArch64] Enable the codegenprepare optimization that promotes operation to form
extended loads.
Implement the related target lowering hook so that the optimization has a better
estimation of the cost of an extension.

rdar://problem/19267165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233753 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix AllocationPriority not getting set for derived register classes.
Matthias Braun [Tue, 31 Mar 2015 20:52:25 +0000 (20:52 +0000)]
Fix AllocationPriority not getting set for derived register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233752 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Enable uniquing callbacks during MDNode::replaceWithUniqued()
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 20:50:50 +0000 (20:50 +0000)]
IR: Enable uniquing callbacks during MDNode::replaceWithUniqued()

Uniqued nodes have more complete registration with
`ReplaceableMetadataImpl` so that they can update themselves when
operands change.  Fix a bug where `MDNode::replaceWithUniqued()` wasn't
enabling these callbacks.

The two most obvious ways missing callbacks causes problems is that
auto-resolution fails and re-uniquing (on changed operands) just doesn't
happen.  I've added tests for both -- in both cases, I confirmed that
the final check was failing before the fix.

rdar://problem/20365935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233751 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MCJIT] Enable MCJIT regression tests on Darwin.
Lang Hames [Tue, 31 Mar 2015 20:48:52 +0000 (20:48 +0000)]
[MCJIT] Enable MCJIT regression tests on Darwin.

Commit r233747 fixed the issue that had been blocking this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233750 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SDAG] Handle non-integer preferred memset types for non-constant values
Hal Finkel [Tue, 31 Mar 2015 20:35:26 +0000 (20:35 +0000)]
[SDAG] Handle non-integer preferred memset types for non-constant values

The existing code in getMemsetValue only handled integer-preferred types when
the fill value was not a constant. Make this more robust in two ways:

  1. If the preferred type is a floating-point value, do the mul-splat trick on
     the corresponding integer type and then bitcast.
  2. If the preferred type is a vector, do the mul-splat trick on one vector
     element, and then build a vector out of them.

Fixes PR22754 (although, we should also turn off use of vector types at -O0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233749 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ExecutionEngine] Fix MCJIT::addGlobalMapping.
Lang Hames [Tue, 31 Mar 2015 20:31:14 +0000 (20:31 +0000)]
[ExecutionEngine] Fix MCJIT::addGlobalMapping.

This patch fixes MCJIT::addGlobalMapping by changing the implementation of the
ExecutionEngineState class. The new implementation maintains a bidirectional
mapping between symbol names (std::strings) and addresses (uint64_ts), rather
than a mapping between Value*s and void*s.

This has fix has been made for backwards compatibility, however the strongly
preferred way to resolve unknown symbols is by writing a custom
RuntimeDyld::SymbolResolver (formerly RTDyldMemoryManager) and overriding the
findSymbol method. The addGlobalMapping method is a hangover from the legacy JIT
(which has was removed in 3.6), and may be deprecated in a future release as
part of a clean-up of the ExecutionEngine interface.

Patch by Murat Bolat. Thanks Murat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233747 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] Add support for token-based fuzzing (e.g. for C++). Allow string flags.
Kostya Serebryany [Tue, 31 Mar 2015 20:13:20 +0000 (20:13 +0000)]
[fuzzer] Add support for token-based fuzzing (e.g. for C++). Allow string flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233745 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoClarify that higher priority means higher values.
Matthias Braun [Tue, 31 Mar 2015 20:04:46 +0000 (20:04 +0000)]
Clarify that higher priority means higher values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233744 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRegAllocGreedy: Allow target to specify register class ordering.
Matthias Braun [Tue, 31 Mar 2015 19:57:53 +0000 (19:57 +0000)]
RegAllocGreedy: Allow target to specify register class ordering.

Specify an allocation order with a register class. This is used by register
allocators with a greedy heuristic. This is usefull as it is sometimes
beneficial to color more constrained classes first.

Differential Revision: http://reviews.llvm.org/D8626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233743 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRegAllocGreedy: Improve live interval order in ReverseLocal mode
Matthias Braun [Tue, 31 Mar 2015 19:57:49 +0000 (19:57 +0000)]
RegAllocGreedy: Improve live interval order in ReverseLocal mode

When allocating live intervals in linear order and all of them are local
to a single basic block you get an optimal coloring. This is also true
if you reverse the order, but it is not true if you sort live ranges
beginnings in reverse order, change to sort live range endings in
reverse order. Take the following live ranges for example:

   |---| |--------|
|----------| |-------|

They get colored suboptimally with 3 registers if you sort the live range
starting points in reverse order (but optimally with live range begins in order,
or live range ends in reverse order).

Apparently the previous strategy was intentional because of allocation
time considerations. I am having a hard time replicating these effects,
while I see substantial improvements in allocation quality with this
change.

No testcase as none of the (in tree) targets use reverse order mode.

Differential Revision: http://reviews.llvm.org/D8625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233742 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Avoid an unused variable warning when assertions are off
Simon Atanasyan [Tue, 31 Mar 2015 19:43:47 +0000 (19:43 +0000)]
[Hexagon] Avoid an unused variable warning when assertions are off

No functional changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233740 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Address review comments for r233689
Ulrich Weigand [Tue, 31 Mar 2015 19:28:50 +0000 (19:28 +0000)]
[SystemZ] Address review comments for r233689

Change lowerCTPOP to:
- Gracefully handle a known-zero input value
- Simplify computation of significant bit size

Thanks to Jay Foad for the review!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233736 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86, AVX] fix zero-extending integer operand load patterns to use integer instructions
Sanjay Patel [Tue, 31 Mar 2015 18:43:43 +0000 (18:43 +0000)]
[X86, AVX] fix zero-extending integer operand load patterns to use integer instructions

This is a follow-on to r233704 and another partial fix for PR22685:
https://llvm.org/bugs/show_bug.cgi?id=22685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233724 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc][MCJIT] Remove the small code model regression tests.
Lang Hames [Tue, 31 Mar 2015 18:19:25 +0000 (18:19 +0000)]
[Orc][MCJIT] Remove the small code model regression tests.

These regression tests are supposed to test small code model support, but have
been XFAIL'd because we don't have an in-tree memory manager that can guarantee
a small-code-model compatible memory layout. Unfortunately, they can
occasionally pass if they get lucky with memory allocation, causing unexpected
passes on the bots. That's not very helpful.

I'm going to remove these until we have the infrastructure (small-code-model
compatible memory manager) to run them properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233722 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: fix v8.1 sqrdmlah tests on Darwin platforms
Tim Northover [Tue, 31 Mar 2015 16:41:38 +0000 (16:41 +0000)]
AArch64: fix v8.1 sqrdmlah tests on Darwin platforms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233709 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRework r233647, "llvm/examples: Suppress building a few JIT examples."
NAKAMURA Takumi [Tue, 31 Mar 2015 16:41:25 +0000 (16:41 +0000)]
Rework r233647, "llvm/examples: Suppress building a few JIT examples."

It didn't work with "install".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233708 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub...
Sanjay Patel [Tue, 31 Mar 2015 16:32:11 +0000 (16:32 +0000)]
[X86, AVX] try to lowerVectorShuffleAsElementInsertion() for all 256-bit vector sub-types

I suggested this change in D7898 (http://llvm.org/viewvc/llvm-project?view=revision&revision=231354)

It improves the v4i64 case although not optimally. This AVX codegen:

  vmovq {{.*#+}} xmm0 = mem[0],zero
  vxorpd %ymm1, %ymm1, %ymm1
  vblendpd {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3]

Becomes:

  vmovsd {{.*#+}} xmm0 = mem[0],zero

Unfortunately, this doesn't completely solve PR22685. There are still at least 2 problems under here:

    We're not handling v32i8 / v16i16.
    We're not getting the FP / int domains right for instruction selection.

But since this patch alone appears to do no harm, reduces code duplication, and helps v4i64,
I'm submitting this patch ahead of fixing the above.

Differential Revision: http://reviews.llvm.org/D8341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233704 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotypos; NFC
Sanjay Patel [Tue, 31 Mar 2015 16:17:51 +0000 (16:17 +0000)]
typos; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233701 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add Analysis to required_libraries (fall-out from r233688)
Ulrich Weigand [Tue, 31 Mar 2015 15:16:13 +0000 (15:16 +0000)]
[SystemZ] Add Analysis to required_libraries (fall-out from r233688)

Should fix build failures with cmake builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233700 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] add cross-reference
Scott Douglass [Tue, 31 Mar 2015 15:07:53 +0000 (15:07 +0000)]
[docs] add cross-reference

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233699 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoExpand MUX instructions early on Hexagon
Krzysztof Parzyszek [Tue, 31 Mar 2015 13:35:12 +0000 (13:35 +0000)]
Expand MUX instructions early on Hexagon

This time with all files included.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233696 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert 233694. Weak SVN-fu.
Krzysztof Parzyszek [Tue, 31 Mar 2015 13:32:32 +0000 (13:32 +0000)]
Revert 233694.  Weak SVN-fu.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233695 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoExpand MUX instructions early on Hexagon
Krzysztof Parzyszek [Tue, 31 Mar 2015 13:29:17 +0000 (13:29 +0000)]
Expand MUX instructions early on Hexagon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233694 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension
Vladimir Sukharev [Tue, 31 Mar 2015 13:15:48 +0000 (13:15 +0000)]
[AArch64] Add v8.1a "Rounding Double Multiply Add/Subtract" extension

Reviewers: t.p.northover, jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8502

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233693 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Support RISBGN instruction on zEC12
Ulrich Weigand [Tue, 31 Mar 2015 12:58:17 +0000 (12:58 +0000)]
[SystemZ] Support RISBGN instruction on zEC12

So far, we do not yet support any instruction specific to zEC12.
Most of the facilities added with zEC12 are indeed not very useful
to compiler code generation, but there is one exception: the
miscellaneous-extensions facility provides the RISBGN instruction,
which is a variant of RISBG that does not set the condition code.

Add support for this facility, MC support for RISBGN, and CodeGen
support for prefering RISBGN over RISBG on zEC12, unless we can
actually make use of the condition code set by RISBG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233690 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Use POPCNT instruction on z196
Ulrich Weigand [Tue, 31 Mar 2015 12:56:33 +0000 (12:56 +0000)]
[SystemZ] Use POPCNT instruction on z196

We already exploit a number of instructions specific to z196,
but not yet POPCNT.  Add support for the population-count
facility, MC support for the POPCNT instruction, CodeGen
support for using POPCNT, and implement the getPopcntSupport
TargetTransformInfo hook.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233689 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Provide basic TargetTransformInfo implementation
Ulrich Weigand [Tue, 31 Mar 2015 12:52:27 +0000 (12:52 +0000)]
[SystemZ] Provide basic TargetTransformInfo implementation

This hooks up the TargetTransformInfo machinery for SystemZ,
and provides an implementation of getIntImmCost.

In addition, the patch adds the isLegalICmpImmediate and
isLegalAddImmediate TargetLowering overrides, and updates
a couple of test cases where we now generate slightly
better code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233688 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the operand encoding in the test instruction.
Rafael Espindola [Tue, 31 Mar 2015 12:31:55 +0000 (12:31 +0000)]
Fix the operand encoding in the test instruction.

Fixes pr22995.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233686 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Remove TargetMachine CPU auto-detection
Ulrich Weigand [Tue, 31 Mar 2015 12:01:06 +0000 (12:01 +0000)]
[PowerPC] Remove TargetMachine CPU auto-detection

As was done for X86 in r206094.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233684 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SDAG] Move TRUNCATE splitting logic into a helper, and use
James Molloy [Tue, 31 Mar 2015 10:20:58 +0000 (10:20 +0000)]
[SDAG] Move TRUNCATE splitting logic into a helper, and use
 it more liberally.

SplitVecOp_TRUNCATE has logic for recursively splitting oversize vectors
that need more than one round of splitting to become legal. There are many
other ISD nodes that could benefit from this logic, so factor it out and
use it for FP_TO_UINT,FP_TO_SINT,SINT_TO_FP,UINT_TO_FP and FTRUNC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233681 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Stop changing result of getHostCPUName based on whether the processor supports...
Craig Topper [Tue, 31 Mar 2015 06:18:31 +0000 (06:18 +0000)]
[X86] Stop changing result of getHostCPUName based on whether the processor supports AVX. getHostCPUFeatures should be used instead to determine whether to support AVX.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233674 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake llc use getHostCPUFeatures when 'native' is specified for cpu.
Craig Topper [Tue, 31 Mar 2015 05:52:57 +0000 (05:52 +0000)]
Make llc use getHostCPUFeatures when 'native' is specified for cpu.

This is necessary for x86 where not all Sandybridge, Ivybrige, Haswell, and Broadwell CPUs support AVX. Currently we modify the CPU name back to Nehalem for this case, but that turns off additional features for these CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233673 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Be more robust against unknown Intel family 6 models. Use feature flags to...
Craig Topper [Tue, 31 Mar 2015 05:42:45 +0000 (05:42 +0000)]
[X86] Be more robust against unknown Intel family 6 models. Use feature flags to guess what it might be.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233671 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Generate MOVNT for all vector types.
Ahmed Bougacha [Tue, 31 Mar 2015 03:16:51 +0000 (03:16 +0000)]
[X86] Generate MOVNT for all vector types.

We used to miss non-Q YMM integer vectors, and, non-Q/D XMM integer
vectors.
While there, change the v4i32 patterns to prefer MOVNTDQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233668 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotools: Unify how verifyModule() is called
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 03:07:23 +0000 (03:07 +0000)]
tools: Unify how verifyModule() is called

Unify the error messages for the various tools when `verifyModule()`
fails on an input module.  The "brave new way" is:

    lltool: path/to/input.ll: error: input module is broken!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233667 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[bpf] mark mov instructions as ReMaterializable
Alexei Starovoitov [Tue, 31 Mar 2015 02:49:58 +0000 (02:49 +0000)]
[bpf] mark mov instructions as ReMaterializable

loading immediate into register is cheap, so take advantage of remat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233666 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVerifier: Don't return early from verifyTypeRefs()
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 02:37:13 +0000 (02:37 +0000)]
Verifier: Don't return early from verifyTypeRefs()

We'll no longer crash in the `verifyTypeRefs()` (used to be called
`verifyDebugInfo()`), so there's no reason to return early here.  Remove
the `EverBroken` member since this was the only use!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233665 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVerifier: Explicitly verify type references
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 02:27:32 +0000 (02:27 +0000)]
Verifier: Explicitly verify type references

`verifyDebugInfo()` was doing two things:

  - Asserting on unresolved type references.
  - Calling `Verify()` functions for various types of debug info.

The `Verify()` functions have been gutted, so rename the function to
`verifyTypeRefs()` and explicitly check those.  Instead of assertions,
we get nice error messages now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233664 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVerifier: Move over DISubprogram::Verify()
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 02:09:55 +0000 (02:09 +0000)]
Verifier: Move over DISubprogram::Verify()

Move over the remaining (somewhat complicated) check from
`DISubprogram::Verify()`.  I suspect this check could be optimized --
e.g., it would be nice not to do another full traversal here -- but it's
not exactly obvious how.  For now, just bring it over as is.

Once we have a better model for the "canonical" subprogram of a
`Function`, we should enforce that all `!dbg` attachments lead to the
canonical one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233663 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Rewrite llvm::getDISubprogram(), NFC
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 02:06:28 +0000 (02:06 +0000)]
DebugInfo: Rewrite llvm::getDISubprogram(), NFC

Simplify implementation of `llvm::getDISubprogram()`.  I might go
through and see how difficult it is to update the users, since this
function doesn't really seem necessary anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233662 91177308-0d34-0410-b5e6-96231b3b80d8