oota-llvm.git
8 years agoAdd a FIXME to TargetMachine to remove the function specific
Eric Christopher [Fri, 26 Sep 2014 01:44:05 +0000 (01:44 +0000)]
Add a FIXME to TargetMachine to remove the function specific
code generation options from TargetMachine. This will depend
upon Function + TargetSubtargetInfo based code generation at
which point resetTargetOptions and this code can be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218491 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoHave setSubtarget take a const subtarget.
Eric Christopher [Fri, 26 Sep 2014 01:28:13 +0000 (01:28 +0000)]
Have setSubtarget take a const subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218490 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove resetTargetOptions from taking a MachineFunction to a Function
Eric Christopher [Fri, 26 Sep 2014 01:28:10 +0000 (01:28 +0000)]
Move resetTargetOptions from taking a MachineFunction to a Function
since we are accessing the TargetMachine that we're a member
function of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218489 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Avoid repeated check lines
Matt Arsenault [Fri, 26 Sep 2014 01:12:36 +0000 (01:12 +0000)]
R600: Avoid repeated check lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218487 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix emitting trailing whitespace after s_waitcnt
Matt Arsenault [Fri, 26 Sep 2014 01:09:46 +0000 (01:09 +0000)]
R600/SI: Fix emitting trailing whitespace after s_waitcnt

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218486 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Simplify use of !con()
Adam Nemet [Fri, 26 Sep 2014 00:53:12 +0000 (00:53 +0000)]
[AVX512] Simplify use of !con()

No change in X86.td.expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218485 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Pull pattern for subvector extract into the instruction definition
Adam Nemet [Thu, 25 Sep 2014 23:48:49 +0000 (23:48 +0000)]
[AVX512] Pull pattern for subvector extract into the instruction definition

No functional change.

I initially thought that pulling the Pat<> into the instruction pattern was
not possible because it was doing a transform on the index in order to convert
it from a per-element (extract_subvector) index into a per-chunk (vextract*x4)
index.

Turns out this also works inside the pattern because the vextract_extract
PatFrag has an OperandTransform EXTRACT_get_vextract{128,256}_imm, so the
index in $idx goes through the same conversion.

The existing test CodeGen/X86/avx512-insert-extract.ll extended in the
previous commit provides coverage for this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218480 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well
Adam Nemet [Thu, 25 Sep 2014 23:48:47 +0000 (23:48 +0000)]
[AVX512] Make vextract*x4/vinsert*x4 tests check for the index as well

Extend test so that it provides coverage for the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218479 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Refactor subvector extracts
Adam Nemet [Thu, 25 Sep 2014 23:48:45 +0000 (23:48 +0000)]
[AVX512] Refactor subvector extracts

No functional change.

These are now implemented as two levels of multiclasses heavily relying on the
new X86VectorVTInfo class.  The multiclass at the first level that is called
with float or int provides the 128 or 256 bit subvector extracts.  The second
level provides the register and memory variants and some more Pat<>s.

I've compared the td.expanded files before and after.  One change is that
ExeDomain for 64x4 is SSEPackedDouble now.  I think this is correct, i.e. a
bugfix.

(BTW, this is the change that was blocked on the recent tablegen fix.  The
class-instance values X86VectorVTInfo inside vextract_for_type weren't
properly evaluated.)

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218478 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AVX512] Fix typo
Adam Nemet [Thu, 25 Sep 2014 23:48:42 +0000 (23:48 +0000)]
[AVX512] Fix typo

F->I in VEXTRACTF32x4rr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218477 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd SDAG TableGen definitions for BR_CC
Hal Finkel [Thu, 25 Sep 2014 23:34:18 +0000 (23:34 +0000)]
Add SDAG TableGen definitions for BR_CC

Add SelectionDAG TableGen definitions for BR_CC so that targets can instruction-select
BR_CC using TableGen pattern matching.

Patch by deadal nix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218476 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Fix some missing conversion testcases
Matt Arsenault [Thu, 25 Sep 2014 23:16:18 +0000 (23:16 +0000)]
R600: Fix some missing conversion testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218474 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove duplicated RUN lines in middle of test
Matt Arsenault [Thu, 25 Sep 2014 23:16:14 +0000 (23:16 +0000)]
Remove duplicated RUN lines in middle of test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218473 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[MachineSink+PGO] Teach MachineSink to use BlockFrequencyInfo
Bruno Cardoso Lopes [Thu, 25 Sep 2014 23:14:26 +0000 (23:14 +0000)]
[MachineSink+PGO] Teach MachineSink to use BlockFrequencyInfo

Machine Sink uses loop depth information to select between successors BBs to
sink machine instructions into, where BBs within smaller loop depths are
preferable.  This patch adds support for choosing between successors by using
profile information from BlockFrequencyInfo instead, whenever the information
is available.

Tested it under SPEC2006 train (average of 30 runs for each program); ~1.5%
execution speedup in average on x86-64 darwin.

<rdar://problem/18021659>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218472 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoObject: Add range iterators for Archive children
David Majnemer [Thu, 25 Sep 2014 22:56:54 +0000 (22:56 +0000)]
Object: Add range iterators for Archive children

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218471 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Support] Fix Format.h to build on Windows
Nick Kledzik [Thu, 25 Sep 2014 21:00:38 +0000 (21:00 +0000)]
[Support] Fix Format.h to build on Windows

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218467 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Support] Add type-safe alternative to llvm::format()
Nick Kledzik [Thu, 25 Sep 2014 20:30:58 +0000 (20:30 +0000)]
[Support] Add type-safe alternative to llvm::format()

llvm::format() is somewhat unsafe. The compiler does not check that integer
parameter size matches the %x or %d size and it does not complain when a
StringRef is passed for a %s.  And correctly using a StringRef with format() is
ugly because you have to convert it to a std::string then call c_str().

The cases where llvm::format() is useful is controlling how numbers and
strings are printed, especially when you want fixed width output.  This
patch adds some new formatting functions to raw_streams to format numbers
and StringRefs in a type safe manner. Some examples:

   OS << format_hex(255, 6)        => "0x00ff"
   OS << format_hex(255, 4)        => "0xff"
   OS << format_decimal(0, 5)      => "    0"
   OS << format_decimal(255, 5)    => "  255"
   OS << right_justify(Str, 5)     => "  foo"
   OS << left_justify(Str, 5)      => "foo  "

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218463 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactoring: raw pointer -> unique_ptr
Anton Yartsev [Thu, 25 Sep 2014 19:55:58 +0000 (19:55 +0000)]
Refactoring: raw pointer -> unique_ptr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218462 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: Remove unneeded check for MI->hasPostISelHook()
Tom Stellard [Thu, 25 Sep 2014 18:59:23 +0000 (18:59 +0000)]
ARM: Remove unneeded check for MI->hasPostISelHook()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218459 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSelectionDAG: Remove #if NDEBUG from check for a post-isel hook
Tom Stellard [Thu, 25 Sep 2014 18:59:22 +0000 (18:59 +0000)]
SelectionDAG: Remove #if NDEBUG from check for a post-isel hook

The InstrEmitter will skip the check of MI.hasPostISelHook()
before calling AdjustInstrPostInstrSelection() when NDEBUG
is not defined.

This was added in r140228, and I'm not sure if it is intentional or not,
but it is a likely source for bugs, because it means with
Release+Asserts builds you can forget to set the hasPostISelHook
flag on TableGen definitions and AdjustInstrPostInstrSelection() will
still be called.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218458 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add support for global atomic add
Tom Stellard [Thu, 25 Sep 2014 18:30:26 +0000 (18:30 +0000)]
R600/SI: Add support for global atomic add

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218457 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoLower idempotent RMWs to fence+load
Robin Morisset [Thu, 25 Sep 2014 17:27:43 +0000 (17:27 +0000)]
Lower idempotent RMWs to fence+load

Summary:
I originally tried doing this specifically for X86 in the backend in D5091,
but it was rather brittle and generally running too late to be general.
Furthermore, other targets may want to implement similar optimizations.
So I reimplemented it at the IR-level, fitting it into AtomicExpandPass
as it interacts with that pass (which could not be cleanly done before
at the backend level).

This optimization relies on a new target hook, which is only used by X86
for now, as the correctness of the optimization on other targets remains
an open question. If it is found correct on other targets, it should be
trivial to enable for them.

Details of the optimization are discussed in D5091.

Test Plan: make check-all + a new test

Reviewers: jfb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5422

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218455 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSince the DisasmMemoryObject only operates on const data, it now only accepts a const...
Aaron Ballman [Thu, 25 Sep 2014 14:02:43 +0000 (14:02 +0000)]
Since the DisasmMemoryObject only operates on const data, it now only accepts a const data pointer. This silences a -Wcast-qual warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218454 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd missing attributes !cmp.[eq,gt,gtu] instructions.
Sid Manning [Thu, 25 Sep 2014 13:09:54 +0000 (13:09 +0000)]
Add missing attributes !cmp.[eq,gt,gtu] instructions.

These instructions do not indicate they are extendable or the
number of bits in the extendable operand.  Rename to match
architected names.  Add a testcase for the intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218453 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd llvm_unreachables() for [ASZ]ExtUpper to X86FastISel.cpp to appease the buildbots.
Daniel Sanders [Thu, 25 Sep 2014 13:08:51 +0000 (13:08 +0000)]
Add llvm_unreachables() for [ASZ]ExtUpper to X86FastISel.cpp to appease the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218452 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struc...
Daniel Sanders [Thu, 25 Sep 2014 12:15:05 +0000 (12:15 +0000)]
[mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values.

Summary:
The N32/N64 ABI's require that structs passed in registers are laid out
such that spilling the register with 'sd' places the struct at the lowest
address. For little endian this is trivial but for big-endian it requires
that structs are shifted into the upper bits of the register.

We also require that structs passed in registers have the 'inreg'
attribute for big-endian N32/N64 to work correctly. This is because the
tablegen-erated calling convention implementation only has access to the
lowered form of struct arguments (one or more integers of up to 64-bits
each) and is unable to determine the original type.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5286

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218451 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd aliases for VAND imm to VBIC ~imm
Renato Golin [Thu, 25 Sep 2014 11:31:24 +0000 (11:31 +0000)]
Add aliases for VAND imm to VBIC ~imm

On ARM NEON, VAND with immediate (16/32 bits) is an alias to VBIC ~imm with
the same type size. Adding that logic to the parser, and generating VBIC
instructions from VAND asm files.

This patch also fixes the validation routines for NEON splat immediates which
were wrong.

Fixes PR20702.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218450 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering to use AVX2 instructions for
Chandler Carruth [Thu, 25 Sep 2014 11:03:55 +0000 (11:03 +0000)]
[x86] Teach the new vector shuffle lowering to use AVX2 instructions for
v4f64 and v8f32 shuffles when they are lane-crossing. We have fully
general lane-crossing permutation functions in AVX2 that make this easy.

Part of this also changes exactly when and how these vectors are split
up when we don't have AVX2. This isn't always a win but it usually is
a win, so on the balance I think its better. The primary regressions are
all things that just need to be fixed anyways such as modeling when
a blend can be completely accomplished via VINSERTF128, etc.

Also, this highlights one of the few remaining big features: we do
a really poor job of inserting elements into AVX registers efficiently.

This completes almost all of the big tricks I have in mind for AVX2. The
only things left that I plan to add:

1) element insertion smarts
2) palignr and other fairly specialized lowerings when they happen to
   apply

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218449 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate my previous commit to fit 80 cols...
Sylvestre Ledru [Thu, 25 Sep 2014 10:58:16 +0000 (10:58 +0000)]
Update my previous commit to fit 80 cols...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218448 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDetails that -debug-only is not available when LLVM is built with --enable-optimized
Sylvestre Ledru [Thu, 25 Sep 2014 10:57:00 +0000 (10:57 +0000)]
Details that -debug-only is not available when LLVM is built with --enable-optimized

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218447 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering a fancier way to lower
Chandler Carruth [Thu, 25 Sep 2014 10:21:15 +0000 (10:21 +0000)]
[x86] Teach the new vector shuffle lowering a fancier way to lower
256-bit vectors with lane-crossing.

Rather than immediately decomposing to 128-bit vectors, try flipping the
256-bit vector lanes, shuffling them and blending them together. This
reduces our worst case shuffle by a pretty significant margin across the
board.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218446 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Thumb2] BXJ should be undefined for v7M, v8A
Oliver Stannard [Thu, 25 Sep 2014 10:02:05 +0000 (10:02 +0000)]
[Thumb2] BXJ should be undefined for v7M, v8A

The Thumb2 BXJ instruction (Branch and Exchange Jazelle) is not
defined for v7M or v8A. It is defined for all other Thumb2-supporting
architectures (v6T2, v7A and v7R).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218445 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix an oversight in the v8i32 path of the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 04:10:27 +0000 (04:10 +0000)]
[x86] Fix an oversight in the v8i32 path of the new vector shuffle
lowering where it only used the mask of the low 128-bit lane rather than
the entire mask.

This allows the new lowering to correctly match the unpack patterns for
v8i32 vectors.

For reference, the reason that we check for the the entire mask rather
than checking the repeated mask is because the repeated masks don't
abide by all of the invariants of normal masks. As a consequence, it is
safer to use the full mask with functions like the generic equivalence
test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218442 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Rearrange the code for v16i16 lowering a bit for clarity and to
Chandler Carruth [Thu, 25 Sep 2014 04:03:22 +0000 (04:03 +0000)]
[x86] Rearrange the code for v16i16 lowering a bit for clarity and to
reduce the amount of checking we do here.

The first realization is that only non-crossing cases between 128-bit
lanes are handled by almost the entire function. It makes more sense to
handle the crossing cases first.

THe second is that until we actually are going to generate fancy shared
lowering strategies that use the repeated semantics of the v8i16
lowering, we should waste time checking for repeated masks. It is
simplest to directly test for the entire unpck masks anyways, so we
gained nothing from this.

This also matches the structure of v32i8 more closely.

No functionality changed here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218441 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Implement AVX2 support for v32i8 in the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 02:52:12 +0000 (02:52 +0000)]
[x86] Implement AVX2 support for v32i8 in the new vector shuffle
lowering.

This completes the basic AVX2 feature support, but there are still some
improvements I'd like to do to really get the last mile of performance
here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218440 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] More tweaks to the v32i8 test cases.
Chandler Carruth [Thu, 25 Sep 2014 02:44:39 +0000 (02:44 +0000)]
[x86] More tweaks to the v32i8 test cases.

I made a mistake in the previous commit and produced the wrong pattern.
Fix that. Also make one more shuffle pattern byte-based rather than
word-based, and add two more blend patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218439 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Re-work a bunch of the v32i8 test cases to actually involve byte
Chandler Carruth [Thu, 25 Sep 2014 02:20:02 +0000 (02:20 +0000)]
[x86] Re-work a bunch of the v32i8 test cases to actually involve byte
shuffles rather than word shuffles.

As you might guess, these were built starting from the word shuffle test
cases and I failed to properly port a bunch of them and left them as
widened word shuffle test cases. We still have a couple of tests that
check our ability to widen shuffles, but now we will test the actual
byte shuffle quite a bit better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218438 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: Use @IMGREL instead of @IMGREL32, which we can't parse
Reid Kleckner [Thu, 25 Sep 2014 02:09:18 +0000 (02:09 +0000)]
MC: Use @IMGREL instead of @IMGREL32, which we can't parse

Nico Rieck added support for this 32-bit COFF relocation some time ago
for Win64 stuff. It appears that as an oversight, the assembly output
used "foo"@IMGREL32 instead of "foo"@IMGREL, which is what we can parse.

Sadly, there were actually tests that took in IMGREL and put out
IMGREL32, and we didn't notice the inconsistency. Oh well. Now LLVM can
assemble it's own output with slightly more fidelity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218437 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Remove the defunct X86ISD::BLENDV entry -- we use vector selects
Chandler Carruth [Thu, 25 Sep 2014 01:16:01 +0000 (01:16 +0000)]
[x86] Remove the defunct X86ISD::BLENDV entry -- we use vector selects
for this now.

Should prevent folks from running afoul of this and not knowing why
their code won't instruction select the way I just did...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218436 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix the v16i16 blend logic I added in the prior commit and add the
Chandler Carruth [Thu, 25 Sep 2014 01:13:38 +0000 (01:13 +0000)]
[x86] Fix the v16i16 blend logic I added in the prior commit and add the
missing test cases for it.

Unsurprisingly, without test cases, there were bugs here. Surprisingly,
this bug wasn't caught at compile time. Yep, there is an X86ISD::BLENDV.
It isn't wired to anything. Oops. I'll fix than next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218434 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm-cov: Combine segments that cover the same location
Justin Bogner [Thu, 25 Sep 2014 00:34:18 +0000 (00:34 +0000)]
llvm-cov: Combine segments that cover the same location

If we have multiple coverage counts for the same segment, we need to
add them up rather than arbitrarily choosing one. This fixes that and
adds a test with template instantiations to exercise it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218432 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86,AVX] Add an isel pattern for X86VBroadcast.
Akira Hatanaka [Thu, 25 Sep 2014 00:26:15 +0000 (00:26 +0000)]
[X86,AVX] Add an isel pattern for X86VBroadcast.

This fixes PR21050 and rdar://problem/18434607.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218431 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Implement v16i16 support with AVX2 in the new vector shuffle
Chandler Carruth [Thu, 25 Sep 2014 00:24:19 +0000 (00:24 +0000)]
[x86] Implement v16i16 support with AVX2 in the new vector shuffle
lowering.

This also implements the fancy blend lowering for v16i16 using AVX2 and
teaches the X86 backend to print shuffle masks for 256-bit PSHUFB
and PBLENDW instructions. It also makes the mask decoding correct for
PBLENDW instructions. The yaks, they are legion.

Tests are updated accordingly. There are some missing tests for the
VBLENDVB lowering, but I'll add those in a follow-up as this commit has
accumulated enough cruft already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218430 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFlush out enough of llvm-objdump’s SymbolizerSymbolLookUp() for Mach-O files to
Kevin Enderby [Wed, 24 Sep 2014 23:08:22 +0000 (23:08 +0000)]
Flush out enough of llvm-objdump’s SymbolizerSymbolLookUp() for Mach-O files to
get the literal string “Hello world” printed as a comment on the instruction
that loads the pointer to it. For now this is just for x86_64. So for object
files with relocation entries it produces things like:

leaq L_.str(%rip), %rax      ## literal pool for: "Hello world\n"

and similar for fully linked images like executables:

leaq 0x4f(%rip), %rax        ## literal pool for: "Hello world\n"

Also to allow testing against darwin’s otool(1), I hooked up the existing
-no-show-raw-insn option to the Mach-O parser code, added the new Mach-O
only -full-leading-addr option to match otool(1)'s printing of addresses and
also added the new -print-imm-hex option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218423 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[asan] don't instrument module CTORs that may be run before asan.module_ctor. This...
Kostya Serebryany [Wed, 24 Sep 2014 22:41:55 +0000 (22:41 +0000)]
[asan] don't instrument module CTORs that may be run before asan.module_ctor. This fixes asan running together -coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218421 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemoving empty ARM tests from failed revert
Renato Golin [Wed, 24 Sep 2014 21:58:04 +0000 (21:58 +0000)]
Removing empty ARM tests from failed revert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218419 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemoving empty tests from failed revert
Renato Golin [Wed, 24 Sep 2014 21:45:26 +0000 (21:45 +0000)]
Removing empty tests from failed revert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218417 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert 218406 - Refactor the RelocVisitor::visit method
Renato Golin [Wed, 24 Sep 2014 21:30:43 +0000 (21:30 +0000)]
Revert 218406 - Refactor the RelocVisitor::visit method

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218416 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert 218407 - Add support for ARM and AArch64 BE object files
Renato Golin [Wed, 24 Sep 2014 21:30:14 +0000 (21:30 +0000)]
Revert 218407 - Add support for ARM and AArch64 BE object files

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218415 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert 218408 - Report endianness in output of {dwarf, obj}dump
Renato Golin [Wed, 24 Sep 2014 21:29:45 +0000 (21:29 +0000)]
Revert 218408 - Report endianness in output of {dwarf, obj}dump

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218414 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert 218411 - XFAIL reloc test on x86/hexagon
Renato Golin [Wed, 24 Sep 2014 21:28:53 +0000 (21:28 +0000)]
Revert 218411 - XFAIL reloc test on x86/hexagon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218413 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoXFAIL reloc test on x86/hexagon
Renato Golin [Wed, 24 Sep 2014 21:00:30 +0000 (21:00 +0000)]
XFAIL reloc test on x86/hexagon

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218411 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert r218380. This was breaking Apple internal build bots.
Akira Hatanaka [Wed, 24 Sep 2014 20:37:14 +0000 (20:37 +0000)]
Revert r218380. This was breaking Apple internal build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218409 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReport endianness in output of {dwarf, obj}dump
Renato Golin [Wed, 24 Sep 2014 20:07:41 +0000 (20:07 +0000)]
Report endianness in output of {dwarf, obj}dump

For biendian targets like ARM and AArch64, it is useful to have the
output of the llvm-dwarfdump and llvm-objdump report the endianness
used when the object files were generated.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218408 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd support for ARM and AArch64 BE object files
Renato Golin [Wed, 24 Sep 2014 20:07:30 +0000 (20:07 +0000)]
Add support for ARM and AArch64 BE object files

This change fixes the ARM and AArch64 relocation visitors in
RelocVisitor.  They were unconditionally assuming the object data are
little-endian.  Tests have been added to ensure that the
llvm-dwarfdump utility does not crash when processing big-endian
object files.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218407 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactor the RelocVisitor::visit method
Renato Golin [Wed, 24 Sep 2014 20:07:22 +0000 (20:07 +0000)]
Refactor the RelocVisitor::visit method

This change replaces the brittle if/else chain of string comparisons
with a switch statement on the detected target triple, removing the
need for testing arbitrary architecture names returned from
getFileFormatName, whose primary purpose seems to be for display
(user-interface) purposes. The visitor now takes a reference to the
object file, rather than its arbitrary file format name to figure out
whether the file is a 32 or 64-bit object file and what the detected
target triple is.

A set of tests have been added to help show that the refactoring processes
relocations for the same targets as the original code.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218406 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agopass environment when invoking llvm-config from lit.cfg
Scott Douglass [Wed, 24 Sep 2014 18:37:48 +0000 (18:37 +0000)]
pass environment when invoking llvm-config from lit.cfg

Use the same environment when invoking llvm-config from lit.cfg as
will be used when running tests, so that ASAN_OPTIONS, INCLUDE, etc.
are present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218403 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdding #ifdef around TermColorMutex based on feedback from Craig Topper.
Chris Bieneman [Wed, 24 Sep 2014 18:35:58 +0000 (18:35 +0000)]
Adding #ifdef around TermColorMutex based on feedback from Craig Topper.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218401 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Factor out the logic to generically decombose a vector shuffle
Chandler Carruth [Wed, 24 Sep 2014 18:20:09 +0000 (18:20 +0000)]
[x86] Factor out the logic to generically decombose a vector shuffle
into unblended shuffles and a blend.

This is the consistent fallback for the lowering paths that have fast
blend operations available, and its getting quite repetitive.

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218399 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "Add support for ARM and AArch64 BE object files"
Kaelyn Takata [Wed, 24 Sep 2014 18:00:20 +0000 (18:00 +0000)]
Revert "Add support for ARM and AArch64 BE object files"

This reverts commit r218389 as it depends on r218388.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218398 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "Report endianness in output of {dwarf, obj}dump"
Kaelyn Takata [Wed, 24 Sep 2014 18:00:17 +0000 (18:00 +0000)]
Revert "Report endianness in output of {dwarf, obj}dump"

This reverts commit r218391 as it depends on r218388 and r218389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218397 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "Refactor the RelocVisitor::visit method"
Kaelyn Takata [Wed, 24 Sep 2014 17:49:07 +0000 (17:49 +0000)]
Revert "Refactor the RelocVisitor::visit method"

This reverts commit faac033f7364bb4226e22c8079c221c96af10d02.

The test depends on all targets to be enabled in llc in order to pass,
and needs to be rewritten/refactored to not have that dependency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218393 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReport endianness in output of {dwarf, obj}dump
Renato Golin [Wed, 24 Sep 2014 17:01:33 +0000 (17:01 +0000)]
Report endianness in output of {dwarf, obj}dump

For biendian targets like ARM and AArch64, it is useful to have the
output of the llvm-dwarfdump and llvm-objdump report the endianness
used when the object files were generated.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218391 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd support for ARM and AArch64 BE object files
Renato Golin [Wed, 24 Sep 2014 17:01:06 +0000 (17:01 +0000)]
Add support for ARM and AArch64 BE object files

This change fixes the ARM and AArch64 relocation visitors in
RelocVisitor.  They were unconditionally assuming the object data are
little-endian.  Tests have been added to ensure that the
llvm-dwarfdump utility does not crash when processing big-endian
object files.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218389 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactor the RelocVisitor::visit method
Renato Golin [Wed, 24 Sep 2014 17:00:42 +0000 (17:00 +0000)]
Refactor the RelocVisitor::visit method

This change replaces the brittle if/else chain of string comparisons
with a switch statement on the detected target triple, removing the
need for testing arbitrary architecture names returned from
getFileFormatName, whose primary purpose seems to be for display
(user-interface) purposes. The visitor now takes a reference to the
object file, rather than its arbitrary file format name to figure out
whether the file is a 32 or 64-bit object file and what the detected
target triple is.

A set of tests have been added to help show that the refactoring processes
relocations for the same targets as the original code.

Patch by Charlie Turner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218388 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix assertion in LICM doFinalization()
David Peixotto [Wed, 24 Sep 2014 16:48:31 +0000 (16:48 +0000)]
Fix assertion in LICM doFinalization()

The doFinalization method checks that the LoopToAliasSetMap is
empty. LICM populates that map as it runs through the loop nest,
deleting the entries for child loops as it goes. However, if a child
loop is deleted by another pass (e.g. unrolling) then the loop will
never be deleted from the map because LICM walks the loop nest to
find entries it can delete.

The fix is to delete the loop from the map and free the alias set
when the loop is deleted from the loop nest.

Differential Revision: http://reviews.llvm.org/D5305

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218387 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Thumb] Make load/store optimizer less conservative.
Moritz Roth [Wed, 24 Sep 2014 16:35:50 +0000 (16:35 +0000)]
[Thumb] Make load/store optimizer less conservative.

If it's safe to clobber the condition flags, we can do a few extra things:
it's then possible to reset the base register writeback using a SUBS, so
we can try to merge even if the base register isn't dead after the merged
instruction.

This is effectively a (heavily bug-fixed) rewrite of r208992.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218386 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Thumb] 32-bit encodings of 'cps' are not valid for v7M
Oliver Stannard [Wed, 24 Sep 2014 14:20:01 +0000 (14:20 +0000)]
[Thumb] 32-bit encodings of 'cps' are not valid for v7M

v7M only allows the 16-bit encoding of the 'cps' (Change Processor
State) instruction, and does not have the 32-bit encoding which is
valid from v6T2 onwards.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218382 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSilencing an "enumeral and non-enumeral type in conditional expression" warning....
Aaron Ballman [Wed, 24 Sep 2014 13:54:56 +0000 (13:54 +0000)]
Silencing an "enumeral and non-enumeral type in conditional expression" warning. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218381 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReplace a hand-written suffix compare with std::lexicographical_compare.
Benjamin Kramer [Wed, 24 Sep 2014 13:19:28 +0000 (13:19 +0000)]
Replace a hand-written suffix compare with std::lexicographical_compare.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218380 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the instruction lowering to add comments describing constant
Chandler Carruth [Wed, 24 Sep 2014 09:39:41 +0000 (09:39 +0000)]
[x86] Teach the instruction lowering to add comments describing constant
pool data being loaded into a vector register.

The comments take the form of:

  # ymm0 = [a,b,c,d,...]
  # xmm1 = <x,y,z...>

The []s are used for generic sequential data and the <>s are used for
specifically ConstantVector loads. Undef elements are printed as the
letter 'u', integers in decimal, and floating point values as floating
point values. Suggestions on improving the formatting or other aspects
of the display are very welcome.

My primary use case for this is to be able to FileCheck test masks
passed to vector shuffle instructions in-register. It isn't fantastic
for that (no decoding special zeroing semantics or other tricks), but it
at least puts the mask onto an instruction line that could reasonably be
checked. I've updated many of the new vector shuffle lowering tests to
leverage this in their test cases so that we're actually checking the
shuffle masks remain as expected.

Before implementing this, I tried a *bunch* of different approaches.
I looked into teaching the MCInstLower code to scan up the basic block
and find a definition of a register used in a shuffle instruction and
then decode that, but this seems incredibly brittle and complex.
I talked to Hal a lot about the "right" way to do this: attach the raw
shuffle mask to the instruction itself in some form of unencoded
operands, and then use that to emit the comments. I still think that's
the optimal solution here, but it proved to be beyond what I'm up for
here. In particular, it seems likely best done by completing the
plumbing of metadata through these layers and attaching the shuffle mask
in metadata which could have fully automatic dropping when encoding an
actual instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218377 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow BB duplication threshold to be adjusted through JumpThreading's ctor
Michael Liao [Wed, 24 Sep 2014 04:59:06 +0000 (04:59 +0000)]
Allow BB duplication threshold to be adjusted through JumpThreading's ctor

- BB duplication may not be desired on targets where there is no or small
  branch penalty and code duplication needs restrict control.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218375 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoWindows/Host.inc: Reformat the header to fit 80-col.
NAKAMURA Takumi [Wed, 24 Sep 2014 04:45:14 +0000 (04:45 +0000)]
Windows/Host.inc: Reformat the header to fit 80-col.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218374 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUnix/Host.inc: Remove <cstdlib>. It has been unused for a long time.
NAKAMURA Takumi [Wed, 24 Sep 2014 04:45:02 +0000 (04:45 +0000)]
Unix/Host.inc: Remove <cstdlib>. It has been unused for a long time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218373 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUnix/Host.inc: Wrap a comment line in 80-col.
NAKAMURA Takumi [Wed, 24 Sep 2014 04:44:50 +0000 (04:44 +0000)]
Unix/Host.inc: Wrap a comment line in 80-col.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218371 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUnix/Host.inc: Remove leading whitespace. It had been here since r56942!
NAKAMURA Takumi [Wed, 24 Sep 2014 04:44:37 +0000 (04:44 +0000)]
Unix/Host.inc: Remove leading whitespace. It had been here since r56942!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218370 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agovalgrind/x86_64-pc-linux-gnu.supp: Suppress also /bin/bash.
NAKAMURA Takumi [Wed, 24 Sep 2014 04:38:20 +0000 (04:38 +0000)]
valgrind/x86_64-pc-linux-gnu.supp: Suppress also /bin/bash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218369 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agovalgrind/x86_64-pc-linux-gnu.supp: Tweak /bin/sed to let calloc recognized.
NAKAMURA Takumi [Wed, 24 Sep 2014 04:38:09 +0000 (04:38 +0000)]
valgrind/x86_64-pc-linux-gnu.supp: Tweak /bin/sed to let calloc recognized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218368 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoClear PreferredExtendType for in each function-specific state FunctionLoweringInfo.
Jiangning Liu [Wed, 24 Sep 2014 03:22:56 +0000 (03:22 +0000)]
Clear PreferredExtendType for in each function-specific state FunctionLoweringInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218364 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] More refactoring of the shuffle comment emission. The previous
Chandler Carruth [Wed, 24 Sep 2014 03:06:37 +0000 (03:06 +0000)]
[x86] More refactoring of the shuffle comment emission. The previous
attempt didn't work out so well. It looks like it will be much better
for introducing extra logic to find a shuffle mask if the finding logic
is totally separate. This also makes it easy to sink the opcode logic
completely out of the routine so we don't re-dispatch across it.

Still no functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218363 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Bypass the shuffle mask comment generation when not using verbose
Chandler Carruth [Wed, 24 Sep 2014 03:06:34 +0000 (03:06 +0000)]
[x86] Bypass the shuffle mask comment generation when not using verbose
asm. This can be somewhat expensive and there is no reason to do it
outside of tests or debugging sessions. I'm also likely to make it
significantly more expensive to support more styles of shuffles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218362 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Hoist the logic for extracting the relevant bits of information
Chandler Carruth [Wed, 24 Sep 2014 02:24:41 +0000 (02:24 +0000)]
[x86] Hoist the logic for extracting the relevant bits of information
from the MachineInstr into the caller which is already doing a switch
over the instruction.

This will make it more clear how to compute different operands to feed
the comment selection for example.

Also, in a drive-by-fix, don't append an empty comment string (which is
a no-op ultimately).

No functionality changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218361 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Add new helper isSGPRClassID
Matt Arsenault [Wed, 24 Sep 2014 02:17:12 +0000 (02:17 +0000)]
R600/SI: Add new helper isSGPRClassID

Move these into header since they are trivial

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218360 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix hardcoded and wrong operand numbers.
Matt Arsenault [Wed, 24 Sep 2014 02:17:09 +0000 (02:17 +0000)]
R600/SI: Fix hardcoded and wrong operand numbers.

Also fix leftover debug printing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218359 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Enable named operand table for SALU instructions
Matt Arsenault [Wed, 24 Sep 2014 02:17:06 +0000 (02:17 +0000)]
R600/SI: Enable named operand table for SALU instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218358 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Start refactoring the comment printing logic in the MC lowering of
Chandler Carruth [Wed, 24 Sep 2014 02:16:12 +0000 (02:16 +0000)]
[x86] Start refactoring the comment printing logic in the MC lowering of
vector shuffles.

This is just the beginning by hoisting it into its own function and
making use of early exit to dramatically simplify the flow of the
function. I'm going to be incrementally refactoring this until it is
a bit less magical how this applies to other instructions, and I can
teach it how to dig a shuffle mask out of a register. Then I plan to
hook it up to VPERMD so we get our mask comments for it.

No functionality changed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218357 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix weird CHECK-DAG usage
Matt Arsenault [Wed, 24 Sep 2014 02:14:26 +0000 (02:14 +0000)]
R600/SI: Fix weird CHECK-DAG usage

This prevents these from failing in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218356 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Enable selecting SALU inside branches
Tom Stellard [Wed, 24 Sep 2014 01:33:28 +0000 (01:33 +0000)]
R600/SI: Enable selecting SALU inside branches

We can do this now that the FixSGPRLiveRanges pass is working.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218353 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Move PHIs that define SGPRs to the VALU in most cases
Tom Stellard [Wed, 24 Sep 2014 01:33:26 +0000 (01:33 +0000)]
R600/SI: Move PHIs that define SGPRs to the VALU in most cases

This fixes a bug that is uncovered by a future commit and will
be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218352 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix the FixSGPRLiveRanges pass
Tom Stellard [Wed, 24 Sep 2014 01:33:24 +0000 (01:33 +0000)]
R600/SI: Fix the FixSGPRLiveRanges pass

The previous implementation was extending the live range of SGPRs
by modifying the live intervals directly.  This was causing a lot
of machine verification errors when the machine scheduler was enabled.

The new implementation adds pseudo instructions with implicit uses to
extend the live ranges of SGPRs, which works much better.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218351 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Mark EXEC_LO and EXEC_HI as reserved
Tom Stellard [Wed, 24 Sep 2014 01:33:23 +0000 (01:33 +0000)]
R600/SI: Mark EXEC_LO and EXEC_HI as reserved

These registers can be allocated and used like other 32-bit registers,
but it seems like a likely source for bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218350 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix SIRegisterInfo::getPhysRegSubReg()
Tom Stellard [Wed, 24 Sep 2014 01:33:22 +0000 (01:33 +0000)]
R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()

Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO,
VCC_HI, and M0.  The previous implementation would assertion fail
when passed these registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218349 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Implement VGPR register spilling for compute at -O0 v3
Tom Stellard [Wed, 24 Sep 2014 01:33:17 +0000 (01:33 +0000)]
R600/SI: Implement VGPR register spilling for compute at -O0 v3

VGPRs are spilled to LDS.  This still needs more testing, but
we need to at least enable it at -O0, because the fast register
allocator spills all registers that are live at the end of blocks
and without this some future commits will break the
flat-address-space.ll test.

v2: Only calculate thread id once

v3: Move insertion of spill instructions to
    SIRegisterInfo::eliminateFrameIndex()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218348 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering to lower v8i32 shuffles with
Chandler Carruth [Wed, 24 Sep 2014 01:24:44 +0000 (01:24 +0000)]
[x86] Teach the new vector shuffle lowering to lower v8i32 shuffles with
the native AVX2 instructions.

Note that the test case is really frustrating here because VPERMD
requires the mask to be in the register input and we don't produce
a comment looking through that to the constant pool. I'm going to
attempt to improve this in a subsequent commit, but not sure if I will
succeed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218347 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix a really terrible bug in the repeated 128-bin-lane shuffle
Chandler Carruth [Wed, 24 Sep 2014 01:03:57 +0000 (01:03 +0000)]
[x86] Fix a really terrible bug in the repeated 128-bin-lane shuffle
detection. It was incorrectly handling undef lanes by actually treating
an undef lane in the first 128-bit lane as a *numeric* shuffle value.

Fortunately, this almost always DTRT and disabled detecting repeated
patterns. But not always. =/ This patch introduces a much more
principled approach and fixes the miscompiles I spotted by inspection
previously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218346 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix swift-atomics testcase
Robin Morisset [Tue, 23 Sep 2014 23:18:01 +0000 (23:18 +0000)]
Fix swift-atomics testcase

This testcase was not testing what it meant: because there were only two checks for
dmb {{ish}} in the second function, it could have missed a bug where one of the three
required dmb {{ish}} became dmb {{ishst}}. As I was fixing it, I also added
CHECK-LABELs to make it a bit less brittle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218341 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the new vector shuffle lowering to lower v4i64 vector
Chandler Carruth [Tue, 23 Sep 2014 22:39:02 +0000 (22:39 +0000)]
[x86] Teach the new vector shuffle lowering to lower v4i64 vector
shuffles using the AVX2 instructions. This is the first step of cutting
in real AVX2 support.

Note that I have spotted at least one bug in the test cases already, but
I suspect it was already present and just is getting surfaced. Will
investigate next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218338 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoGlobalOpt: Preserve comdats of unoptimized initializers
Reid Kleckner [Tue, 23 Sep 2014 22:33:01 +0000 (22:33 +0000)]
GlobalOpt: Preserve comdats of unoptimized initializers

Rather than slurping in and splatting out the whole ctor list, preserve
the existing array entries without trying to understand them.  Only
remove the entries that we know we can optimize away.  This way we don't
need to wire through priority and comdats or anything else we might add.

Fixes a linker issue where the .init_array or .ctors entry would point
to discarded initialization code if the comdat group from the TU with
the faulty global_ctors entry was dropped.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218337 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAArch64: allow constant expressions for shifted reg literals
Jim Grosbach [Tue, 23 Sep 2014 22:16:02 +0000 (22:16 +0000)]
AArch64: allow constant expressions for shifted reg literals

e.g., add w1, w2, w3, lsl #(2 - 1)

This sort of thing comes up in pre-processed assembly playing macro games.
Still validate that it's an assembly time constant. The early exit error check
was just a bit overzealous and disallowed a left paren.

rdar://18430542

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218336 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Teach the rest of the 'target shuffle' machinery about blends and
Chandler Carruth [Tue, 23 Sep 2014 22:14:14 +0000 (22:14 +0000)]
[x86] Teach the rest of the 'target shuffle' machinery about blends and
add VPBLENDD to the InstPrinter's comment generation so we get nice
comments everywhere.

Now that we have the nice comments, I can see the bug introduced by
a silly typo in the commit that enabled VPBLENDD, and have fixed it. Yay
tests that are easy to inspect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218335 91177308-0d34-0410-b5e6-96231b3b80d8