oota-llvm.git
8 years agoFix return sequence on armv4 thumb
Jonathan Roelofs [Tue, 5 Aug 2014 17:13:17 +0000 (17:13 +0000)]
Fix return sequence on armv4 thumb

POP on armv4t cannot be used to change thumb state (unilke later non-m-class
architectures), therefore we need a different return sequence that uses 'bx'
instead:

  POP {r3}
  ADD sp, #offset
  BX r3

This patch also fixes an issue where the return value in r3 would get clobbered
for functions that return 128 bits of data. In that case, we generate this
sequence instead:

  MOV ip, r3
  POP {r3}
  ADD sp, #offset
  MOV lr, r3
  MOV r3, ip
  BX lr

http://reviews.llvm.org/D4748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214881 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPartially revert r214761 that asserted that all concrete debug info variables had...
David Blaikie [Tue, 5 Aug 2014 16:47:23 +0000 (16:47 +0000)]
Partially revert r214761 that asserted that all concrete debug info variables had DIEs, due to a failure on Darwin.

I'll work on a reduction and fix after this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214880 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoImprove test for merged global debug info by using llvm-dwarfdump.
David Blaikie [Tue, 5 Aug 2014 16:20:25 +0000 (16:20 +0000)]
Improve test for merged global debug info by using llvm-dwarfdump.

It's a bit of a tradeoff, since llvm-dwarfdump doesn't print the name of
the global symbol being used as an address in the addressing mode, but
this avoids the dependence on hardcoded set labels that keep changing
(5+ commits over the last few years that each update the set label as it
changes due to other, unrelated differences in output). This could've,
instead, been changed to match the set name then match the name in the
string pool but that would present other issues (needing to skip over
the sets that weren't of interest, etc) and checking that the addresses
(granted, without relocations applied - so it's not the whole story)
match in the two variable location descriptions seems sufficient and
fairly stable here.

There are a few similar other tests with similar label dependence that
I'll update soonish.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214878 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd accessors for the PPC 403 bank registers.
Joerg Sonnenberger [Tue, 5 Aug 2014 15:45:15 +0000 (15:45 +0000)]
Add accessors for the PPC 403 bank registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214875 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd tests for cp10/cp11 on ARMv5/6
Renato Golin [Tue, 5 Aug 2014 15:29:41 +0000 (15:29 +0000)]
Add tests for cp10/cp11 on ARMv5/6

Tests for ARMv7/8 are already on diagnostics.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214872 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSpecify that the thumb setend and blx <immed> instructions are not valid on an m...
Keith Walker [Tue, 5 Aug 2014 15:11:59 +0000 (15:11 +0000)]
Specify that the thumb setend and blx <immed> instructions are not valid on an m-class target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214871 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDefine stc2/stc2l/ldc2/ldc2l as thumb2 instructions
Keith Walker [Tue, 5 Aug 2014 14:58:05 +0000 (14:58 +0000)]
Define stc2/stc2l/ldc2/ldc2l as thumb2 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214868 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAccessors for SSR2 and SSR3 on PPC 403.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:53:05 +0000 (14:53 +0000)]
Accessors for SSR2 and SSR3 on PPC 403.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214867 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Update MUBUF assembly string to match AMD proprietary compiler
Tom Stellard [Tue, 5 Aug 2014 14:48:12 +0000 (14:48 +0000)]
R600/SI: Update MUBUF assembly string to match AMD proprietary compiler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214866 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Avoid generating REGISTER_LOAD instructions.
Tom Stellard [Tue, 5 Aug 2014 14:40:52 +0000 (14:40 +0000)]
R600/SI: Avoid generating REGISTER_LOAD instructions.

SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code
path for 8-bit and 16-bit private loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214865 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd dci/ici instructions for PPC 476 and friends.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:40:32 +0000 (14:40 +0000)]
Add dci/ici instructions for PPC 476 and friends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214864 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd mftblo and mftbhi for PPC 4xx.
Joerg Sonnenberger [Tue, 5 Aug 2014 14:18:16 +0000 (14:18 +0000)]
Add mftblo and mftbhi for PPC 4xx.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214863 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd lswi / stswi for assembler use with a warning to not add patterns
Joerg Sonnenberger [Tue, 5 Aug 2014 13:34:01 +0000 (13:34 +0000)]
Add lswi / stswi for assembler use with a warning to not add patterns
for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214862 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAArch64: Add support for instruction prefetch intrinsic
Yi Kong [Tue, 5 Aug 2014 12:46:47 +0000 (12:46 +0000)]
AArch64: Add support for instruction prefetch intrinsic

Instruction prefetch is not implemented for AArch64, it is incorrectly
translated into data prefetch instruction.

Differential Revision: http://reviews.llvm.org/D4777

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214860 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTeach the SLP Vectorizer that keeping some values live over a callsite can have a...
James Molloy [Tue, 5 Aug 2014 12:30:34 +0000 (12:30 +0000)]
Teach the SLP Vectorizer that keeping some values live over a callsite can have a cost.

Some types, such as 128-bit vector types on AArch64, don't have any callee-saved registers. So if a value needs to stay live over a callsite, it must be spilled and refilled. This cost is now taken into account.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214859 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Reformat some code I moved around in a prior commit but left
Chandler Carruth [Tue, 5 Aug 2014 10:35:30 +0000 (10:35 +0000)]
[x86] Reformat some code I moved around in a prior commit but left
poorly formatted. Sorry about that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214853 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow binary and for tblgen math.
Joerg Sonnenberger [Tue, 5 Aug 2014 09:43:25 +0000 (09:43 +0000)]
Allow binary and for tblgen math.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214851 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix a crash and wrong-code bug in the new vector lowering all
Chandler Carruth [Tue, 5 Aug 2014 08:19:21 +0000 (08:19 +0000)]
[x86] Fix a crash and wrong-code bug in the new vector lowering all
found by a single test reduced out of a failure on llvm-stress.

The start of the problem (and the crash) came when we tried to use
a find of a non-used slot in the move-to half of the move-mask as the
target for two bad-half inputs. While if lucky this will be the first of
a pair of slots which we can place the bad-half inputs into, it isn't
actually guaranteed. This really isn't surprising, not sure what I was
thinking. The correct way to find the two unused slots is to look for
one of the *used* slots. We know it isn't that pair, and we can use some
modular arithmetic to find the other pair by masking off the odd bit and
adding 2 modulo 4. With this, we reliably found a viable pair of slots
for the bad-half inputs.

Sadly, that wasn't enough. We also had a wrong code bug that surfaced
when I reduced the test case for this where we would use the same slot
twice for the two bad inputs. This is because both of the bad inputs
could be in odd slots originally and thus the mod-2 mapping would
actually be the same. The whole point of the weird indexing into the
pair of empty slots was to try to leverage when the end result needed
the two bad-half inputs to be paired in a dword and pre-pair them in the
correct orrientation. This is less important with the powerful combining
we're now doing, and also easier and more reliable to achieve be noting
that we add the bad-half inputs in order. Thus, if they are in a dword
pair, the low part of that will be the first input in the sequence.
Always putting that in the low element will just do the right thing in
addition to computing the correct result.

Test case added. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214849 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastIsel][AArch64] Fix previous commit r214844 (Don't perform sign-/zero-extension...
Juergen Ributzka [Tue, 5 Aug 2014 07:31:30 +0000 (07:31 +0000)]
[FastIsel][AArch64] Fix previous commit r214844 (Don't perform sign-/zero-extension for function arguments that have already been sign-/zero-extended.)

The original code would fail for unsupported value types like i1, i8, and i16.
This fix changes the code to only create a sub-register copy for i64 value types
and all other types (i1/i8/i16/i32) just use the source register without any
modifications.

getRegClassFor() is now guarded by the i64 value type check, that guarantees
that we always request a register for a valid value type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214848 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Implement the FastLowerArguments hook.
Juergen Ributzka [Tue, 5 Aug 2014 05:43:48 +0000 (05:43 +0000)]
[FastISel][AArch64] Implement the FastLowerArguments hook.

This implements basic argument lowering for AArch64 in FastISel. It only
handles a small subset of the C calling convention. It supports simple
arguments that can be passed in GPR and FPR registers.

This should cover most of the trivial cases without falling back to
SelectionDAG.

This fixes <rdar://problem/17890986>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214846 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "r214832 - MachineCombiner Pass for selecting faster instruction"
Kevin Qin [Tue, 5 Aug 2014 05:43:47 +0000 (05:43 +0000)]
Revert "r214832 - MachineCombiner Pass for selecting faster instruction"

It broke compiling of most Benchmark and internal test, as clang got
clashed by segmentation fault or assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214845 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Don't perform sign-/zero-extension for function arguments that...
Juergen Ributzka [Tue, 5 Aug 2014 05:43:44 +0000 (05:43 +0000)]
[FastISel][AArch64] Don't perform sign-/zero-extension for function arguments that have already been sign-/zero-extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214844 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoProvide convenient access to the zext/sext attributes of function arguments. NFC.
Juergen Ributzka [Tue, 5 Aug 2014 05:43:41 +0000 (05:43 +0000)]
Provide convenient access to the zext/sext attributes of function arguments. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214843 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoHave MachineFunction cache a pointer to the subtarget to make lookups
Eric Christopher [Tue, 5 Aug 2014 02:39:49 +0000 (02:39 +0000)]
Have MachineFunction cache a pointer to the subtarget to make lookups
shorter/easier and have the DAG use that to do the same lookup. This
can be used in the future for TargetMachine based caching lookups from
the MachineFunction easily.

Update the MIPS subtarget switching machinery to update this pointer
at the same time it runs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214838 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMachineCombiner Pass for selecting faster instruction
Gerolf Hoflehner [Tue, 5 Aug 2014 01:16:13 +0000 (01:16 +0000)]
MachineCombiner Pass for selecting faster instruction
 sequence on AArch64

Re-commit of r214669 without changes to test cases
LLVM::CodeGen/AArch64/arm64-neon-mul-div.ll and
LLVM:: CodeGen/AArch64/dp-3source.ll
This resolves the reported compfails of the original commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214832 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd TCR register access
Joerg Sonnenberger [Mon, 4 Aug 2014 23:53:42 +0000 (23:53 +0000)]
Add TCR register access

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214826 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd PPC 603's tlbld and tlbli instructions.
Joerg Sonnenberger [Mon, 4 Aug 2014 23:49:45 +0000 (23:49 +0000)]
Add PPC 603's tlbld and tlbli instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214825 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow CP10/CP11 operations on ARMv5/v6
Renato Golin [Mon, 4 Aug 2014 23:21:56 +0000 (23:21 +0000)]
Allow CP10/CP11 operations on ARMv5/v6

Those registers are VFP/NEON and vector instructions should be used instead,
but old cores rely on those co-processors to enable VFP unwinding. This change
was prompted by the libc++abi's unwinding routine and is also present in many
legacy low-level bare-metal code that we ought to compile/assemble.

Fixing bug PR20025 and allowing PR20529 to proceed with a fix in libc++abi.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214802 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi
Bill Schmidt [Mon, 4 Aug 2014 23:21:01 +0000 (23:21 +0000)]
[PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi

My original LE implementation of the vsldoi instruction, with its
altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect
shufflevector operations in the LLVM IR.  Correct code is generated
because the back end handles the incorrect shufflevector in a
consistent manner.

This patch and a companion patch for Clang correct this problem by
removing the fixup from altivec.h and the corresponding fixup from the
PowerPC back end.  Several test cases are also modified to reflect the
now-correct LLVM IR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214800 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoEnable Darwin vararg parameters support in assembler macros.
Kevin Enderby [Mon, 4 Aug 2014 23:14:37 +0000 (23:14 +0000)]
Enable Darwin vararg parameters support in assembler macros.

Duplicate the vararg tests for linux and add a tests which mixed
vararg arguments with darwin positional parameters.

Patch by: Janne Grunau <j@jannau.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214799 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoChanged the liveness tracking in the RegisterScavenger
Pedro Artigas [Mon, 4 Aug 2014 23:07:49 +0000 (23:07 +0000)]
Changed the liveness tracking in the RegisterScavenger
to use register units instead of registers.

reviewed by Jakob Stoklund Olesen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214798 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd simplified aliases for access to DCCR, ICCR, DEAR and ESR
Joerg Sonnenberger [Mon, 4 Aug 2014 22:56:42 +0000 (22:56 +0000)]
Add simplified aliases for access to DCCR, ICCR, DEAR and ESR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214797 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix SmallDenseMap assignment operator.
Andrew Trick [Mon, 4 Aug 2014 22:18:25 +0000 (22:18 +0000)]
Fix SmallDenseMap assignment operator.

Self assignment would lead to buckets of garbage, causing quadratic probing to hang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214790 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[FastISel][AArch64] Fix shift lowering for i8 and i16 value types.
Juergen Ributzka [Mon, 4 Aug 2014 21:49:51 +0000 (21:49 +0000)]
[FastISel][AArch64] Fix shift lowering for i8 and i16 value types.

This fix changes the parameters #r and #s that are passed to the UBFM/SBFM
instruction to get the zero/sign-extension for free.

The original problem was that the shift left would use the 32-bit shift even for
i8/i16 value types, which could leave the upper bits set with "garbage" values.

The arithmetic shift right on the other side would use the wrong MSB as sign-bit
to determine what bits to shift into the value.

This fixes <rdar://problem/17907720>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214788 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoIR: Fix up doxygen comment for LLVMContext::diagnose
Justin Bogner [Mon, 4 Aug 2014 21:49:15 +0000 (21:49 +0000)]
IR: Fix up doxygen comment for LLVMContext::diagnose

This comment was referring to the DiagnosticSeverity with RS_
prefixes, but they're actually DS_. I've also modernized the comment
style since I was changing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214787 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SDAG] Fix a really, really terrible bug in the DAG combiner.
Chandler Carruth [Mon, 4 Aug 2014 21:29:59 +0000 (21:29 +0000)]
[SDAG] Fix a really, really terrible bug in the DAG combiner.

This code is completely wrong. It is also dead, as if it were to *ever*
run, it would crash. Fortunately, after my work to the combiner, it is
at least *possible* to reach the code, and llvm-stress has found a test
case. Thanks to Patrick for reporting.

It would be really good if anyone who remembers how this code works and
what it was intended to do could add some more obvious test coverage
instead of my completely contrived and reduced test case. My test case
was so brittle I left a bread crumb comment in it to help the next
person to stumble on it and not know what it was actually testing for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214785 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agotlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.
Joerg Sonnenberger [Mon, 4 Aug 2014 21:28:22 +0000 (21:28 +0000)]
tlbre / tlbwe / tlbsx / tlbsx. variants for the PPC 4xx CPUs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214784 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReorder to keep data and routines separate and to keep a couple of
Eric Christopher [Mon, 4 Aug 2014 21:25:44 +0000 (21:25 +0000)]
Reorder to keep data and routines separate and to keep a couple of
similar routines close to each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214782 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRemove the TargetMachine forwards for TargetSubtargetInfo based
Eric Christopher [Mon, 4 Aug 2014 21:25:23 +0000 (21:25 +0000)]
Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214781 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReimplement the temporary non-const getSubtargetImpl routine so
Eric Christopher [Mon, 4 Aug 2014 21:24:07 +0000 (21:24 +0000)]
Reimplement the temporary non-const getSubtargetImpl routine so
that we can avoid implementing it on every target. Thanks to Richard
Smith for the suggestions!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214780 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
Chad Rosier [Mon, 4 Aug 2014 21:20:25 +0000 (21:20 +0000)]
[AArch64] Extend the number of scalar instructions supported in the AdvSIMD
scalar integer instruction pass.

This is a patch I had lying around from a few months ago.  The pass is
currently disabled by default, so nothing to interesting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214779 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC uses .lcomm now, so adjust.
Joerg Sonnenberger [Mon, 4 Aug 2014 21:06:00 +0000 (21:06 +0000)]
MC uses .lcomm now, so adjust.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214776 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix failure to invoke exception handler on Win64
Reid Kleckner [Mon, 4 Aug 2014 21:05:27 +0000 (21:05 +0000)]
Fix failure to invoke exception handler on Win64

When the last instruction prior to a function epilogue is a call, we
need to emit a nop so that the return address is not in the epilogue IP
range.  This is consistent with MSVC's behavior, and may be a workaround
for a bug in the Win64 unwinder.

Differential Revision: http://reviews.llvm.org/D4751

Patch by Vadim Chugunov!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214775 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCorrect the emission kind constants committed in r214771
David Blaikie [Mon, 4 Aug 2014 20:36:00 +0000 (20:36 +0000)]
Correct the emission kind constants committed in r214771

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214772 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDocument the "emission kind" field of the DICompileUnit in LLVM's Source Level Debugg...
David Blaikie [Mon, 4 Aug 2014 20:32:48 +0000 (20:32 +0000)]
Document the "emission kind" field of the DICompileUnit in LLVM's Source Level Debugging metadata.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214771 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRecognize mftbl as alias for mftb, for symmetry with mttb.
Joerg Sonnenberger [Mon, 4 Aug 2014 20:28:34 +0000 (20:28 +0000)]
Recognize mftbl as alias for mftb, for symmetry with mttb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214769 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a sentence that all entries should include an email address.
Joerg Sonnenberger [Mon, 4 Aug 2014 19:33:25 +0000 (19:33 +0000)]
Add a sentence that all entries should include an email address.
Add one for Greg Clayton, Peter Collingbourne, Tobias Grosser and
Jakob Olesen based on recent commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214762 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoReapply "DebugInfo: Ensure that all debug location scope chains from instructions...
David Blaikie [Mon, 4 Aug 2014 19:30:08 +0000 (19:30 +0000)]
Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself."

Originally reverted in r213432 with flakey failures on an ASan self-host
build. After reduction it seems to be the same issue fixed in r213805
(ArgPromo + DebugInfo: Handle updating debug info over multiple
applications of argument promotion) and r213952 (by having
LiveDebugVariables strip dbg_value intrinsics in functions that are not
described by debug info). Though I cannot explain why this failure was
flakey...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214761 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix definitions for ds_read2 / ds_write2 instructions.
Matt Arsenault [Mon, 4 Aug 2014 18:49:22 +0000 (18:49 +0000)]
R600/SI: Fix definitions for ds_read2 / ds_write2 instructions.

These were just wrong, using the wrong register classes
and store2 was missing an operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214756 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRename PPCLinuxMCAsmInfo to PPCELFMCAsmInfo to better reflect the
Joerg Sonnenberger [Mon, 4 Aug 2014 18:46:13 +0000 (18:46 +0000)]
Rename PPCLinuxMCAsmInfo to PPCELFMCAsmInfo to better reflect the
systems it represents.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214755 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAllow .lcomm with alignment on ELF targets.
Joerg Sonnenberger [Mon, 4 Aug 2014 18:45:10 +0000 (18:45 +0000)]
Allow .lcomm with alignment on ELF targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214754 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCoverage: add HasCodeBefore flag to a mapping region.
Alex Lorenz [Mon, 4 Aug 2014 18:00:51 +0000 (18:00 +0000)]
Coverage: add HasCodeBefore flag to a mapping region.

This flag will be used by the coverage tool to help
compute the execution counts for each line in a source file.

Differential Revision: http://reviews.llvm.org/D4746

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214740 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMove the R600 intrinsic support back to the target machine - there's
Eric Christopher [Mon, 4 Aug 2014 17:37:43 +0000 (17:37 +0000)]
Move the R600 intrinsic support back to the target machine - there's
nothing subtarget dependent about the intrinsic support in any
backend as far as I can tell.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214738 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPath: Stop claiming path::const_iterator is bidirectional
Justin Bogner [Mon, 4 Aug 2014 17:36:41 +0000 (17:36 +0000)]
Path: Stop claiming path::const_iterator is bidirectional

path::const_iterator claims that it's a bidirectional iterator, but it
doesn't satisfy all of the contracts for a bidirectional iterator.
For example, n3376 24.2.5 p6 says "If a and b are both dereferenceable,
then a == b if and only if *a and *b are bound to the same object",
but this doesn't work with how we stash and recreate Components.

This means that our use of reverse_iterator on this type is invalid
and leads to many of the valgrind errors we're hitting, as explained
by Tilmann Scheller here:

    http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140728/228654.html

Instead, we admit that path::const_iterator is only an input_iterator,
and implement a second input_iterator for path::reverse_iterator (by
changing const_iterator::operator-- to reverse_iterator::operator++).
All of the uses of this just traverse once over the path in one
direction or the other anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214737 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRefactor SPRG instructions.
Joerg Sonnenberger [Mon, 4 Aug 2014 17:26:15 +0000 (17:26 +0000)]
Refactor SPRG instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214733 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Place parentheses around "isMask_32(STReturns) && N <= 2".
Akira Hatanaka [Mon, 4 Aug 2014 17:23:38 +0000 (17:23 +0000)]
[X86] Place parentheses around "isMask_32(STReturns) && N <= 2".

This corrects r214672, which was committed to silence a gcc warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214732 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd support for m[ft][di]bat[ul] instructions.
Joerg Sonnenberger [Mon, 4 Aug 2014 17:07:41 +0000 (17:07 +0000)]
Add support for m[ft][di]bat[ul] instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214731 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse the known address space constant rather than checking it
Matt Arsenault [Mon, 4 Aug 2014 16:55:35 +0000 (16:55 +0000)]
Use the known address space constant rather than checking it

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214729 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600: Remove unused include
Matt Arsenault [Mon, 4 Aug 2014 16:55:33 +0000 (16:55 +0000)]
R600: Remove unused include

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214728 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a dummy subtarget to the CPP backend target machine. This will
Eric Christopher [Mon, 4 Aug 2014 16:40:55 +0000 (16:40 +0000)]
Add a dummy subtarget to the CPP backend target machine. This will
allow us to forward all of the standard TargetMachine calls to the
subtarget and still return null as we were before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214727 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd features for PPC 4xx and e500/e500mc instructions.
Joerg Sonnenberger [Mon, 4 Aug 2014 15:47:38 +0000 (15:47 +0000)]
Add features for PPC 4xx and e500/e500mc instructions.
Move the test cases for them into separate files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214724 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Add target triple to vec_urem_const.ll test case
Ulrich Weigand [Mon, 4 Aug 2014 14:55:26 +0000 (14:55 +0000)]
[PowerPC] Add target triple to vec_urem_const.ll test case

This should hopefully fix build bots on other architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214721 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SKX] Enabling load/store instructions: encoding
Robert Khasanov [Mon, 4 Aug 2014 14:35:15 +0000 (14:35 +0000)]
[SKX] Enabling load/store instructions: encoding
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214719 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Swap arguments to vpkuhum/vpkuwum on little-endian
Ulrich Weigand [Mon, 4 Aug 2014 13:53:40 +0000 (13:53 +0000)]
[PowerPC] Swap arguments to vpkuhum/vpkuwum on little-endian

In commit r213915, Bill fixed little-endian usage of vmrgh* and vmrgl*
by swapping the input arguments.  As it turns out, the exact same fix
is also required for the vpkuhum/vpkuwum patterns.

This fixes another regression in llvmpipe when vector support is
enabled.

Reviewed by Bill Schmidt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214718 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoImproving the name of the function parameter, which happens to solve two likely-less...
Aaron Ballman [Mon, 4 Aug 2014 13:51:27 +0000 (13:51 +0000)]
Improving the name of the function parameter, which happens to solve two likely-less-than-useful MSVC warnings: warning C4258: 'I' : definition from the for loop is ignored; the definition from the enclosing scope is used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214717 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] MULHU/MULHS are not legal for vector types
Ulrich Weigand [Mon, 4 Aug 2014 13:27:12 +0000 (13:27 +0000)]
[PowerPC] MULHU/MULHS are not legal for vector types

I ran into some test failures where common code changed vector division
by constant into a multiply-high operation (MULHU).  But these are not
implemented by the back-end, so we failed to recognize the insn.

Fixed by marking MULHU/MULHS as Expand for vector types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214716 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFixed accidental use of reserved identifier in r214709.
Daniel Sanders [Mon, 4 Aug 2014 13:27:03 +0000 (13:27 +0000)]
Fixed accidental use of reserved identifier in r214709.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214715 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Fix and improve vector comparisons
Ulrich Weigand [Mon, 4 Aug 2014 13:13:57 +0000 (13:13 +0000)]
[PowerPC] Fix and improve vector comparisons

This patch refactors code generation of vector comparisons.

This fixes a wrong code-gen bug for ISD::SETGE for floating-point types,
and improves generated code for vector comparisons in general.

Specifically, the patch moves all logic deciding how to implement vector
comparisons into getVCmpInst, which gets two extra boolean outputs
indicating to its caller whether its needs to swap the input operands
and/or negate the result of the comparison.  Apart from implementing
these two modifications as directed by getVCmpInst, there is no need
to ever implement vector comparisons in any other manner; in particular,
there is never a need to perform two separate comparisons (e.g. one for
equal and one for greater-than, as code used to do before this patch).

Reviewed by Bill Schmidt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214714 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips] Add assembler support for '.set mipsX'.
Daniel Sanders [Mon, 4 Aug 2014 12:20:00 +0000 (12:20 +0000)]
[mips] Add assembler support for '.set mipsX'.

Summary:
This patch also fixes an issue with the way the Mips assembler enables/disables architecture
features. Before this patch, the assembler never disabled feature bits. For example,
.set mips64
.set mips32r2

would result in the 'OR' of mips64 with mips32r2 feature bits which isn't right.
Unfortunately this isn't trivial to fix because there's not an easy way to clear
feature bits as the algorithm in MCSubtargetInfo (ToggleFeature) only clears the bits
that imply the feature being cleared and not the implied bits by the feature (there's a
better explanation to the code I added).

Patch by Matheus Almeida and updated by Toma Tabacu

Reviewers: vmedic, matheusalmeida, dsanders

Reviewed By: dsanders

Subscribers: tomatabacu, llvm-commits

Differential Revision: http://reviews.llvm.org/D4123

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214709 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTargetInstrInfo::genAlternativeCodeSequence(): Fix a couple of \param(s). [-Wdocument...
NAKAMURA Takumi [Mon, 4 Aug 2014 10:23:22 +0000 (10:23 +0000)]
TargetInstrInfo::genAlternativeCodeSequence(): Fix a couple of \param(s). [-Wdocumentation]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214708 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Just unilaterally prefer SSSE3-style PSHUFB lowerings over clever
Chandler Carruth [Mon, 4 Aug 2014 10:17:35 +0000 (10:17 +0000)]
[x86] Just unilaterally prefer SSSE3-style PSHUFB lowerings over clever
use of PACKUS. It's cleaner that way.

I looked at implementing clever combine-based folding of PACKUS chains
into PSHUFB but it is quite hard and doesn't seem likely to be worth it.
The most annoying part would be detecting that the correct masking had
been done to use PACKUS-style instructions as a blend operation rather
than there being any saturating as is indicated by its name. We generate
really nice code for what few test cases I've come up with that aren't
completely contrived for this by just directly prefering PSHUFB and so
let's go with that strategy for now. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214707 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Implement more aggressive use of PACKUS chains for lowering common
Chandler Carruth [Mon, 4 Aug 2014 09:40:02 +0000 (09:40 +0000)]
[x86] Implement more aggressive use of PACKUS chains for lowering common
patterns of v16i8 shuffles.

This implements one of the more important FIXMEs for the SSE2 support in
the new shuffle lowering. We now generate the optimal shuffle sequence
for truncate-derived shuffles which show up essentially everywhere.

Unfortunately, this exposes a weakness in other parts of the shuffle
logic -- we can no longer form PSHUFB here. I'll add the necessary
support for that and other things in a subsequent commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214702 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate links to the gcc and java documentation that 404'd.
Benjamin Kramer [Mon, 4 Aug 2014 09:26:40 +0000 (09:26 +0000)]
Update links to the gcc and java documentation that 404'd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214700 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "r214669 - MachineCombiner Pass for selecting faster instruction"
Kevin Qin [Mon, 4 Aug 2014 05:10:33 +0000 (05:10 +0000)]
Revert "r214669 - MachineCombiner Pass for selecting faster instruction"

This commit broke "make check" for several hours, so get it reverted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214697 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMemoryBuffer: Don't use mmap when FileSize is multiple of 4k on Cygwin.
NAKAMURA Takumi [Mon, 4 Aug 2014 01:43:37 +0000 (01:43 +0000)]
MemoryBuffer: Don't use mmap when FileSize is multiple of 4k on Cygwin.

On Cygwin, getpagesize() returns 64k(AllocationGranularity).

In r214580, the size of X86GenInstrInfo.inc became 1499136.

FIXME: We should reorganize again getPageSize() on Win32.
MapFile allocates address along AllocationGranularity but view is mapped by physical page.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214681 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Handle single input shuffles in the SSSE3 case more intelligently.
Chandler Carruth [Mon, 4 Aug 2014 01:14:24 +0000 (01:14 +0000)]
[x86] Handle single input shuffles in the SSSE3 case more intelligently.

I spent some time looking into a better or more principled way to handle
this. For example, by detecting arbitrary "unneeded" ORs... But really,
there wasn't any point. We just shouldn't build blatantly wrong code so
late in the pipeline rather than adding more stages and logic later on
to fix it. Avoiding this is just too simple.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214680 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Fix the test case added in r214670 and tweaked in r214674 further.
Chandler Carruth [Mon, 4 Aug 2014 00:54:28 +0000 (00:54 +0000)]
[x86] Fix the test case added in r214670 and tweaked in r214674 further.

Fundamentally, there isn't a really portable way to test the constant
pool contents. Instead, pin this test to the bare-metal triple. This
also makes it a 64-bit triple which allows us to only match a single
constant pool rather than two. It can also just hard code the '.' prefix
as the format should be stable now that it has a fixed triple. Finally,
I've switched it to use CHECK-NEXT to be more precise in the instruction
sequence expected and to use variables rather than hard coding decisions
by the register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214679 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[OCaml] Add Llvm.{string_of_const,const_element}.
Peter Zotov [Sun, 3 Aug 2014 23:54:22 +0000 (23:54 +0000)]
[OCaml] Add Llvm.{string_of_const,const_element}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214677 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LLVM-C] Add LLVM{IsConstantString,GetAsString,GetElementAsConstant}.
Peter Zotov [Sun, 3 Aug 2014 23:54:16 +0000 (23:54 +0000)]
[LLVM-C] Add LLVM{IsConstantString,GetAsString,GetElementAsConstant}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214676 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAccount for possible leading '.' in label string.
Sanjay Patel [Sun, 3 Aug 2014 23:20:16 +0000 (23:20 +0000)]
Account for possible leading '.' in label string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214674 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Don't add nodes to the combined set (and prune subsequent
Chandler Carruth [Sun, 3 Aug 2014 23:10:59 +0000 (23:10 +0000)]
[x86] Don't add nodes to the combined set (and prune subsequent
combines) until they are legal.

Doing it the old way could, when the stars align *just* right, cause
a node to get into the combine set prior to being legalized. Then, when
the same node showed up as an operand to another node later on (but not
so much later on that it had been deleted as dead) we would fail to add
it back to the worklist thinking it had already been combined. This
would in turn cause it to not be legalized. Fortunately, we can also
walk the operands looking for uncombined (and thus potentially
un-legalized) nodes late. It will still ensure that we walk all operands
of all nodes and send all of them through both the legalizer without
changes and the combiner at least once. (Which was the original goal of
this).

I have a test case for this bug, but it is terribly brittle. For
example, it will stop finding the bug the moment I enable the new
shuffle lowering. I don't yet have any test case that reliably exercises
this bug, and it isn't clear that it will be possible to craft one. It
is entirely possible that with the new shuffle lowering the two forms of
doing this are precisely equivalent. That doesn't mean we shouldn't take
the more conservative approach of insisting on things in the combined
set having survived the legalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214673 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86: silence warning (-Wparentheses)
Saleem Abdulrasool [Sun, 3 Aug 2014 23:00:39 +0000 (23:00 +0000)]
X86: silence warning (-Wparentheses)

GCC 4.8.2 points out the ambiguity in evaluation of the assertion condition:

lib/Target/X86/X86FloatingPoint.cpp:949:49: warning: suggest parentheses around ‘&&’ within ‘||’ [-Wparentheses]
   assert(STReturns == 0 || isMask_32(STReturns) && N <= 2);

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214672 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoCodeGen: silence a warning
Saleem Abdulrasool [Sun, 3 Aug 2014 23:00:38 +0000 (23:00 +0000)]
CodeGen: silence a warning

GCC 4.8.2 objects to the tautological condition in the assert as the unsigned
value is guaranteed to be >= 0.  Simplify the assertion by dropping the
tautological condition.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214671 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofix for PR20354 - Miscompile of fabs due to vectorization
Sanjay Patel [Sun, 3 Aug 2014 22:48:23 +0000 (22:48 +0000)]
fix for PR20354 - Miscompile of fabs due to vectorization

This is intended to be the minimal change needed to fix PR20354 ( http://llvm.org/bugs/show_bug.cgi?id=20354 ). The check for a vector operation was wrong; we need to check that the fabs itself is not a vector operation.

This patch will not generate the optimal code. A constant pool load and 'and' op will be generated instead of just returning a value that we can calculate in advance (as we do for the scalar case). I've put a 'TODO' comment for that here and expect to have that patch ready soon.

There is a very similar optimization that we can do in visitFNEG, so I've put another 'TODO' there and expect to have another patch for that too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214670 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMachineCombiner Pass for selecting faster instruction
Gerolf Hoflehner [Sun, 3 Aug 2014 22:03:40 +0000 (22:03 +0000)]
MachineCombiner Pass for selecting faster instruction
 sequence -  AArch64 target support

 This patch turns off madd/msub generation in the DAGCombiner and generates
 them in the MachineCombiner instead. It replaces the original code sequence
 with the combined sequence when it is beneficial to do so.

 When there is no machine model support it always generates the madd/msub
 instruction. This is true also when the objective is to optimize for code
 size: when the combined sequence is shorter is always chosen and does not
 get evaluated.

 When there is a machine model the combined instruction sequence
 is evaluated for critical path and resource length using machine
 trace metrics and the original code sequence is replaced when it is
 determined to be faster.

 rdar://16319955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214669 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMachineCombiner Pass for selecting faster instruction
Gerolf Hoflehner [Sun, 3 Aug 2014 21:35:39 +0000 (21:35 +0000)]
MachineCombiner Pass for selecting faster instruction
 sequence -  target independent framework

 When the DAGcombiner selects instruction sequences
 it could increase the critical path or resource len.

 For example, on arm64 there are multiply-accumulate instructions (madd,
 msub). If e.g. the equivalent  multiply-add sequence is not on the
 crictial path it makes sense to select it instead of  the combined,
 single accumulate instruction (madd/msub). The reason is that the
 conversion from add+mul to the madd could lengthen the critical path
 by the latency of the multiply.

 But the DAGCombiner would always combine and select the madd/msub
 instruction.

 This patch uses machine trace metrics to estimate critical path length
 and resource length of an original instruction sequence vs a combined
 instruction sequence and picks the faster code based on its estimates.

 This patch only commits the target independent framework that evaluates
 and selects code sequences. The machine instruction combiner is turned
 off for all targets and expected to evolve over time by gradually
 handling DAGCombiner pattern in the target specific code.

 This framework lays the groundwork for fixing
 rdar://16319955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214666 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: virtualise EmitWindowsUnwindTables
Saleem Abdulrasool [Sun, 3 Aug 2014 18:51:26 +0000 (18:51 +0000)]
MC: virtualise EmitWindowsUnwindTables

This makes EmitWindowsUnwindTables a virtual function and lowers the
implementation of the function to the X86WinCOFFStreamer.  This method is a
target specific operation.  This enables making the behaviour target dependent
by isolating it entirely to the target specific streamer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214664 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: rename Win64EHFrameInfo to WinEH::FrameInfo
Saleem Abdulrasool [Sun, 3 Aug 2014 18:51:17 +0000 (18:51 +0000)]
MC: rename Win64EHFrameInfo to WinEH::FrameInfo

The frame information stored in this structure is driven by the requirements for
Windows NT unwinding rather than Windows 64 specifically.  As a result, this
type can be shared across multiple architectures (ARM, AXP, MIPS, PPC, SH).
Rename this class in preparation for adding support for supporting unwinding
information for Windows on ARM.

Take the opportunity to constify the members as everything except the
ChainedParent is read-only.  This required some adjustment to the label
handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214663 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoR600/SI: Fix extra whitespace in asm str
Matt Arsenault [Sun, 3 Aug 2014 05:27:14 +0000 (05:27 +0000)]
R600/SI: Fix extra whitespace in asm str

This slipped in in r214467, so something like

V_MOV_B32_e32  v0, ... is now printed with 2 spaces
between the instruction name and first operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214660 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SimplifyCFG] fix accessing deleted PHINodes in switch-to-table conversion.
Manman Ren [Sat, 2 Aug 2014 23:41:54 +0000 (23:41 +0000)]
[SimplifyCFG] fix accessing deleted PHINodes in switch-to-table conversion.

When we have a covered lookup table, make sure we don't delete PHINodes that
are cached in PHIs.

rdar://17887153

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214642 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agotlbia support
Joerg Sonnenberger [Sat, 2 Aug 2014 20:16:29 +0000 (20:16 +0000)]
tlbia support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214640 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agomfdcr / mtdcr support
Joerg Sonnenberger [Sat, 2 Aug 2014 20:00:26 +0000 (20:00 +0000)]
mfdcr / mtdcr support

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214639 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofix bug 20513 - Crash in SLP Vectorizer
Erik Eckstein [Sat, 2 Aug 2014 19:39:42 +0000 (19:39 +0000)]
fix bug 20513 - Crash in SLP Vectorizer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214638 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUpdate test to use a more modern AArch64 triple, as requested by Renato.
James Molloy [Sat, 2 Aug 2014 17:15:11 +0000 (17:15 +0000)]
Update test to use a more modern AArch64 triple, as requested by Renato.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214637 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDon't use additional arguments for dss and friends to satisfy DSS_Form,
Joerg Sonnenberger [Sat, 2 Aug 2014 15:09:41 +0000 (15:09 +0000)]
Don't use additional arguments for dss and friends to satisfy DSS_Form,
when let can do the same thing. Keep the 64bit variants as codegen-only.
While they have a different register class, the encoding is the same for
32bit and 64bit mode. Having both present would otherwise confuse the
disassembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load...
James Molloy [Sat, 2 Aug 2014 14:51:24 +0000 (14:51 +0000)]
[AArch64] Teach DAGCombiner that converting two consecutive loads into a vector load is not a good transform when paired loads are available.

The combiner was creating Q-register loads and stores, which then had to be spilled because there are no callee-save Q registers!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214634 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Remove the FIXME that was implemented in r214628. Managed to
Chandler Carruth [Sat, 2 Aug 2014 11:34:23 +0000 (11:34 +0000)]
[x86] Remove the FIXME that was implemented in r214628. Managed to
forget to update the comment here... =/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214630 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Give this test a bare metal triple so it doesn't use the weird
Chandler Carruth [Sat, 2 Aug 2014 11:17:41 +0000 (11:17 +0000)]
[x86] Give this test a bare metal triple so it doesn't use the weird
Darwin x86 asm comment prefix designed to work around GAS on that
platform. That makes the comment-matching of the test much more stable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214629 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Largely complete the use of PSHUFB in the new vector shuffle
Chandler Carruth [Sat, 2 Aug 2014 10:39:15 +0000 (10:39 +0000)]
[x86] Largely complete the use of PSHUFB in the new vector shuffle
lowering with a small addition to it and adding PSHUFB combining.

There is one obvious place in the new vector shuffle lowering where we
should form PSHUFBs directly: when without them we will unpack a vector
of i8s across two different registers and do a potentially 4-way blend
as i16s only to re-pack them into i8s afterward. This is the crazy
expensive fallback path for i8 shuffles and we can just directly use
pshufb here as it will always be cheaper (the unpack and pack are
two instructions so even a single shuffle between them hits our
three instruction limit for forming PSHUFB).

However, this doesn't generate very good code in many cases, and it
leaves a bunch of common patterns not using PSHUFB. So this patch also
adds support for extracting a shuffle mask from PSHUFB in the X86
lowering code, and uses it to handle PSHUFBs in the recursive shuffle
combining. This allows us to combine through them, combine multiple ones
together, and generally produce sufficiently high quality code.

Extracting the PSHUFB mask is annoyingly complex because it could be
either pre-legalization or post-legalization. At least this doesn't have
to deal with re-materialized constants. =] I've added decode routines to
handle the different patterns that show up at this level and we dispatch
through them as appropriate.

The two primary test cases are updated. For the v16 test case there is
still a lot of room for improvement. Since I was going through it
systematically I left behind a bunch of FIXME lines that I'm hoping to
turn into ALL lines by the end of this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214628 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[x86] Switch to using the variable we extracted this operand into.
Chandler Carruth [Sat, 2 Aug 2014 10:29:36 +0000 (10:29 +0000)]
[x86] Switch to using the variable we extracted this operand into.

Spotted this missed refactoring by inspection when reading code, and it
doesn't changethe functionality at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214627 91177308-0d34-0410-b5e6-96231b3b80d8