7 years ago[PBQP] Fix comment wording. NFC
Arnaud A. de Grandmaison [Fri, 6 Feb 2015 11:28:16 +0000 (11:28 +0000)]
[PBQP] Fix comment wording. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228390 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add assembler and disassembler test cases for clflushopt, clwb, pcommit, xsaves...
Craig Topper [Fri, 6 Feb 2015 06:19:28 +0000 (06:19 +0000)]
[X86] Add assembler and disassembler test cases for clflushopt, clwb, pcommit, xsaves, xrstors, xsavec

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228385 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Remove a ton of duplicate test cases for the assembler.
Craig Topper [Fri, 6 Feb 2015 05:50:50 +0000 (05:50 +0000)]
[X86] Remove a ton of duplicate test cases for the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228383 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders
Michel Danzer [Fri, 6 Feb 2015 02:51:29 +0000 (02:51 +0000)]
R600/SI: Amend a test to ensure WQM is enabled for LDS in pixel shaders

Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228374 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Don't enable WQM for V_INTERP_* instructions v2
Michel Danzer [Fri, 6 Feb 2015 02:51:25 +0000 (02:51 +0000)]
R600/SI: Don't enable WQM for V_INTERP_* instructions v2

Doesn't seem necessary anymore. I think this was mostly compensating for
not enabling WQM for texture sampling instructions.

v2: Add test coverage
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228373 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Also enable WQM for image opcodes which calculate LOD v3
Michel Danzer [Fri, 6 Feb 2015 02:51:20 +0000 (02:51 +0000)]
R600/SI: Also enable WQM for image opcodes which calculate LOD v3

If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing

v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228372 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIntroduce print-memderefs to test isDereferenceablePointer
Ramkumar Ramachandra [Fri, 6 Feb 2015 01:46:42 +0000 (01:46 +0000)]
Introduce print-memderefs to test isDereferenceablePointer

Since testing the function indirectly is tricky, introduce a direct
print-memderefs pass, in the same spirit as print-memdeps, which prints
dereferenceability information matched by FileCheck.

Differential Revision: http://reviews.llvm.org/D7075

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228369 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: Make test more robust.
Matthias Braun [Thu, 5 Feb 2015 23:52:14 +0000 (23:52 +0000)]
AArch64: Make test more robust.

Avoid the creation of select instructions which can result in different
scheduling of the selects.

I also added a bunch of additional store volatiles. Those avoid A
CodeGen problem (bug?) where normalizes and denomarlizing the control
moves all shift instructions into the first block where ISel can't match
them together with the cmps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228362 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86: Test cleanup
Matthias Braun [Thu, 5 Feb 2015 23:52:12 +0000 (23:52 +0000)]
X86: Test cleanup

Use FileCheck, make it more consistent and do not rely on unoptimized
or(cmp,cmp) getting combined for max to be matched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228361 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSmall cleanup of MachineLICM.cpp
Daniel Jasper [Thu, 5 Feb 2015 22:39:46 +0000 (22:39 +0000)]
Small cleanup of MachineLICM.cpp

- Calculate the loop pre-header once at the stat of HoistOutOfLoop, so:
  - We don't-DFS walk the MachineDomTree if we aren't going to do anything
  - Don't call getCurPreheader for each Scope
- Don't needlessly use a do-while loop
- Use early exit for Scopes.size() == 0

No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228350 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Renaming v4 compare-and-jump instructions.
Colin LeMahieu [Thu, 5 Feb 2015 22:03:32 +0000 (22:03 +0000)]
[Hexagon] Renaming v4 compare-and-jump instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228349 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Deleting unused patterns.
Colin LeMahieu [Thu, 5 Feb 2015 21:43:56 +0000 (21:43 +0000)]
[Hexagon] Deleting unused patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228348 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Simplifying and formatting several patterns. Changing a pattern multiply...
Colin LeMahieu [Thu, 5 Feb 2015 21:13:25 +0000 (21:13 +0000)]
[Hexagon] Simplifying and formatting several patterns.  Changing a pattern multiply to be expanded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228347 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[BasicAA] Add datalayouts to make some tests more useful. NFC.
Ahmed Bougacha [Thu, 5 Feb 2015 21:10:14 +0000 (21:10 +0000)]
[BasicAA] Add datalayouts to make some tests more useful.  NFC.

Fixes PR22462: two of the tests have regressed for a while,
but were using CHECK-NOT to match "May:".  The actual output
was changed to "MayAlias:" at some point, which made the tests
Two others return MayAlias only because of a lack of analysis;
BasicAA returns PartialAlias in those cases, when a datalayout
is present.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228346 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Factoring a class out of some store patterns, deleting unused definitions...
Colin LeMahieu [Thu, 5 Feb 2015 20:38:58 +0000 (20:38 +0000)]
[Hexagon] Factoring a class out of some store patterns, deleting unused definitions and reformatting some patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228345 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Factoring out a class for immediate transfers and cleaning up formatting.
Colin LeMahieu [Thu, 5 Feb 2015 20:08:52 +0000 (20:08 +0000)]
[Hexagon] Factoring out a class for immediate transfers and cleaning up formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228343 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Avoid using std::to_string
Justin Bogner [Thu, 5 Feb 2015 19:54:27 +0000 (19:54 +0000)]
InstrProf: Avoid using std::to_string

Apparently std::to_string doesn't exist in mingw32:


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228340 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ASan] Enable -asan-stack-dynamic-alloca by default.
Alexey Samsonov [Thu, 5 Feb 2015 19:39:20 +0000 (19:39 +0000)]
[ASan] Enable -asan-stack-dynamic-alloca by default.

By default, store all local variables in dynamic alloca instead of
static one. It reduces the stack space usage in use-after-return mode
(dynamic alloca will not be called if the local variables are stored
in a fake stack), and improves the debug info quality for local
variables (they will not be described relatively to %rbp/%rsp, which
are assumed to be clobbered by function calls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228336 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove the use of getSubtarget in the creation of the X86
Eric Christopher [Thu, 5 Feb 2015 19:27:04 +0000 (19:27 +0000)]
Remove the use of getSubtarget in the creation of the X86
PassManager instance. In one case we can make the determination
from the Triple, in the other (execution dependency pass) the
pass will avoid running if we don't have any code that uses that
register class so go ahead and add it to the pipeline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228334 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse cached subtargets inside X86FixupLEAs.
Eric Christopher [Thu, 5 Feb 2015 19:27:01 +0000 (19:27 +0000)]
Use cached subtargets inside X86FixupLEAs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228333 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMigrate the X86 AsmPrinter away from using the subtarget when
Eric Christopher [Thu, 5 Feb 2015 19:06:45 +0000 (19:06 +0000)]
Migrate the X86 AsmPrinter away from using the subtarget when
dealing with module level emission. Currently this is using
the Triple to determine, but eventually the logic should
probably migrate to TLOF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228332 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix an incorrect identifier
Sylvestre Ledru [Thu, 5 Feb 2015 18:57:02 +0000 (18:57 +0000)]
Fix an incorrect identifier

EIEIO is not a correct declaration and breaks the build under Debian HURD.
Instead, E_IEIO is used.

Some additional classes of identifier names are reserved for future
extensions to the C language or the POSIX.1 environment. While using
these names for your own purposes right now might not cause a problem,
they do raise the possibility of conflict with future versions of the C
or POSIX standards, so you should avoid these names.
Names beginning with a capital ‘E’ followed a digit or uppercase letter
may be used for additional error code names. See Error Reporting.//

Reported here:
And patch wrote by Svante Signell
With this patch, LLVM, Clang & LLDB build under Debian HURD:

Reviewers: hfinkel

Reviewed By: hfinkel

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7437

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228331 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Renaming Y2_barrier. Fixing issues where doubleword variants of instructio...
Colin LeMahieu [Thu, 5 Feb 2015 18:56:28 +0000 (18:56 +0000)]
[Hexagon] Renaming Y2_barrier.  Fixing issues where doubleword variants of instructions can't be newvalue producers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228330 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Prepare loops for pre-increment loads/stores
Hal Finkel [Thu, 5 Feb 2015 18:43:00 +0000 (18:43 +0000)]
[PowerPC] Prepare loops for pre-increment loads/stores

PowerPC supports pre-increment load/store instructions (except for Altivec/VSX
vector load/stores). Using these on embedded cores can be very important, but
most loops are not naturally set up to use them. We can often change that,
however, by placing loops into a non-canonical form. Generically, this means
transforming loops like this:

  for (int i = 0; i < n; ++i)
    array[i] = c;

to look like this:

  T *p = array[-1];
  for (int i = 0; i < n; ++i)
    *++p = c;

the key point is that addresses accessed are pulled into dedicated PHIs and
"pre-decremented" in the loop preheader. This allows the use of pre-increment
load/store instructions without loop peeling.

A target-specific late IR-level pass (running post-LSR), PPCLoopPreIncPrep, is
introduced to perform this transformation. I've used this code out-of-tree for
generating code for the PPC A2 for over a year. Somewhat to my surprise,
running the test suite + externals on a P7 with this transformation enabled
showed no performance regressions, and one speedup:

-2.32514% +/- 1.03736%

So I'm going to enable it on everything for now. I was surprised by this
because, on the POWER cores, these pre-increment load/store instructions are
cracked (and, thus, harder to schedule effectively). But seeing no regressions,
and feeling that it is generally easier to split instructions apart late than
it is to combine them late, this might be the better approach regardless.

In the future, we might want to integrate this functionality into LSR (but
currently LSR does not create new PHI nodes, so (for that and other reasons)
significant work would need to be done).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228328 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Generate pre-increment floating-point ld/st instructions
Hal Finkel [Thu, 5 Feb 2015 18:42:53 +0000 (18:42 +0000)]
[PowerPC] Generate pre-increment floating-point ld/st instructions

PowerPC supports pre-increment floating-point load/store instructions, both r+r
and r+i, and we had patterns for them, but they were not marked as legal. Mark
them as legal (and add a test case).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228327 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.
Colin LeMahieu [Thu, 5 Feb 2015 18:38:08 +0000 (18:38 +0000)]
[Hexagon] Renaming A2_subri, A2_andir, A2_orir.  Fixing formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228326 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Add hook/combine to form vector extloads, enabled on X86.
Ahmed Bougacha [Thu, 5 Feb 2015 18:31:02 +0000 (18:31 +0000)]
[CodeGen] Add hook/combine to form vector extloads, enabled on X86.

The combine that forms extloads used to be disabled on vector types,
because "None of the supported targets knows how to perform load and
sign extend on vectors in one instruction."

That's not entirely true, since at least SSE4.1 X86 knows how to do
those sextloads/zextloads (with PMOVS/ZX).
But there are several aspects to getting this right.
First, vector extloads are controlled by a profitability callback.
For instance, on ARM, several instructions have folded extload forms,
so it's not always beneficial to create an extload node (and trying to
match extloads is a whole 'nother can of worms).

The interesting optimization enables folding of s/zextloads to illegal
(splittable) vector types, expanding them into smaller legal extloads.

It's not ideal (it introduces some legalization-like behavior in the
combine) but it's better than the obvious alternative: form illegal
extloads, and later try to split them up.  If you do that, you might
generate extloads that can't be split up, but have a valid ext+load
expansion.  At vector-op legalization time, it's too late to generate
this kind of code, so you end up forced to scalarize. It's better to
just avoid creating egregiously illegal nodes.

This optimization is enabled unconditionally on X86.

Note that the splitting combine is happy with "custom" extloads. As
is, this bypasses the actual custom lowering, and just unrolls the
extload. But from what I've seen, this is still much better than the
current custom lowering, which does some kind of unrolling at the end
anyway (see for instance load_sext_4i8_to_4i64 on SSE2, and the added

Also note that the existing combine that forms extloads is now also
enabled on legal vectors.  This doesn't have a big effect on X86
(because sext+load is usually combined to sext_inreg+aextload).
On ARM it fires on some rare occasions; that's for a separate commit.

Differential Revision: http://reviews.llvm.org/D6904

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228325 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Add isLoadExtLegalOrCustom helper to TargetLowering.
Ahmed Bougacha [Thu, 5 Feb 2015 18:15:59 +0000 (18:15 +0000)]
[CodeGen] Add isLoadExtLegalOrCustom helper to TargetLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228322 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86 ABI fix for return values > 24 bytes.
Andrew Trick [Thu, 5 Feb 2015 18:09:05 +0000 (18:09 +0000)]
X86 ABI fix for return values > 24 bytes.

The return value's address must be returned in %rax.
i.e. the callee needs to copy the sret argument (%rdi)
into the return value (%rax).

This probably won't manifest as a bug when the caller is LLVM-compiled
code. But it is an ABI guarantee and tools expect it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228321 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Renaming A2_addi and formatting.
Colin LeMahieu [Thu, 5 Feb 2015 17:49:13 +0000 (17:49 +0000)]
[Hexagon] Renaming A2_addi and formatting.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228318 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agomove fold comments to the corresponding fold; NFC
Sanjay Patel [Thu, 5 Feb 2015 17:33:59 +0000 (17:33 +0000)]
move fold comments to the corresponding fold; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228317 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default...
Colin LeMahieu [Thu, 5 Feb 2015 17:32:17 +0000 (17:32 +0000)]
[Hexagon] Since decoding conflicts have been resolved, isCodeGenOnly = 0 by default and remove explicitly setting it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228316 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIdentical code for different branches (CID 1254883)
Sylvestre Ledru [Thu, 5 Feb 2015 17:00:23 +0000 (17:00 +0000)]
Identical code for different branches (CID 1254883)

Reviewers: kledzik, rafael

Reviewed By: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228313 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerSwitch: Use ConstantInt for CaseRange::{Low,High}
Hans Wennborg [Thu, 5 Feb 2015 16:58:10 +0000 (16:58 +0000)]
LowerSwitch: Use ConstantInt for CaseRange::{Low,High}

Case values are always ConstantInt. This allows us to remove
a bunch of casts. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228312 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerSwitch: remove default args from CaseRange ctor; NFC
Hans Wennborg [Thu, 5 Feb 2015 16:50:27 +0000 (16:50 +0000)]
LowerSwitch: remove default args from CaseRange ctor; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228311 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agorevert 228308. The code has changed since the review
Sylvestre Ledru [Thu, 5 Feb 2015 16:35:44 +0000 (16:35 +0000)]
revert 228308. The code has changed since the review

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228309 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIdentical code for different branches (CID 1254883)
Sylvestre Ledru [Thu, 5 Feb 2015 16:30:25 +0000 (16:30 +0000)]
Identical code for different branches (CID 1254883)

Reviewers: kledzik, rafael

Reviewed By: rafael

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228308 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Fix bug in TTI loop unrolling preferences
Tom Stellard [Thu, 5 Feb 2015 15:32:18 +0000 (15:32 +0000)]
R600/SI: Fix bug in TTI loop unrolling preferences

We should be setting UnrollingPreferences::MaxCount to MAX_UINT instead
of UnrollingPreferences::Count.

Count is a 'forced unrolling factor', while MaxCount sets an upper
limit to the unrolling factor.

Setting Count to MAX_UINT was causing the loop in the testcase to be
unrolled 15 times, when it only had a maximum of 4 iterations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228303 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Fix bug from insertion of llvm.SI.end.cf into loop headers
Tom Stellard [Thu, 5 Feb 2015 15:32:15 +0000 (15:32 +0000)]
R600/SI: Fix bug from insertion of llvm.SI.end.cf into loop headers

The llvm.SI.end.cf intrinsic is used to mark the end of if-then blocks,
if-then-else blocks, and loops.  It is responsible for updating the
exec mask to re-enable threads that had been masked during the preceding
control flow block.  For example:

s_mov_b64 exec, 0x3                 ; Initial exec mask
s_mov_b64 s[0:1], exec              ; Saved exec mask
v_cmpx_gt_u32 exec, s[2:3], v0, 0   ; llvm.SI.if
s_or_b64 exec, exec, s[0:1]         ; llvm.SI.end.cf

The bug fixed by this patch was one where the llvm.SI.end.cf intrinsic
was being inserted into the header of loops.  This would happen when
an if block terminated in a loop header and we would end up with
code like this:

s_mov_b64 exec, 0x3                 ; Initial exec mask
s_mov_b64 s[0:1], exec              ; Saved exec mask
v_cmpx_gt_u32 exec, s[2:3], v0, 0   ; llvm.SI.if

LOOP:                       ; Start of loop header
s_or_b64 exec, exec, s[0:1] ; llvm.SI.end.cf <-BUG: The exec mask has the
                              same value at the beginning of each loop
s_cbranch_execnz LOOP

The fix is to create a new basic block before the loop and insert the
llvm.SI.end.cf there.  This way the exec mask is restored before the
start of the loop instead of at the beginning of each iteration.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228302 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Implement the vclz instructions for PWR8
Bill Schmidt [Thu, 5 Feb 2015 15:24:47 +0000 (15:24 +0000)]
[PowerPC] Implement the vclz instructions for PWR8

Patch by Kit Barton.

Add the vector count leading zeros instruction for byte, halfword,
word, and doubleword sizes.  This is a fairly straightforward addition
after the changes made for vpopcnt:

 1. Add the correct definitions for the various instructions in
 2. Make the CTLZ operation legal on vector types when using P8Altivec
    in PPCISelLowering.cpp

Test Plan

Created new test case in test/CodeGen/PowerPC/vec_clz.ll to check the
instructions are being generated when the CTLZ operation is used in

Check the encoding and decoding in test/MC/PowerPC/ppc_encoding_vmx.s
and test/Disassembler/PowerPC/ppc_encoding_vmx.txt respectively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228301 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a FIXME.
Rafael Espindola [Thu, 5 Feb 2015 14:57:47 +0000 (14:57 +0000)]
Add a FIXME.

Thanks to Eric for the suggestion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228300 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemoving an unused variable warning I accidentally introduced with my last warning...
Aaron Ballman [Thu, 5 Feb 2015 13:52:42 +0000 (13:52 +0000)]
Removing an unused variable warning I accidentally introduced with my last warning fix; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228295 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilencing an MSVC warning about a switch statement with no cases; NFC.
Aaron Ballman [Thu, 5 Feb 2015 13:40:04 +0000 (13:40 +0000)]
Silencing an MSVC warning about a switch statement with no cases; NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228294 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][MMX] Handle i32->mmx conversion using movd
Bruno Cardoso Lopes [Thu, 5 Feb 2015 13:23:07 +0000 (13:23 +0000)]
[X86][MMX] Handle i32->mmx conversion using movd

Implement a BITCAST dag combine to transform i32->mmx conversion patterns
into a X86 specific node (MMX_MOVW2D) and guarantee that moves between
i32 and x86mmx are better handled, i.e., don't use store-load to do the

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228293 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][MMX] Add several bitcast tests
Bruno Cardoso Lopes [Thu, 5 Feb 2015 13:22:57 +0000 (13:22 +0000)]
[X86][MMX] Add several bitcast tests

Avoid regression in previously supported MMX code by adding different
combinations of tests which exercise MMX bitcasts. Small improvements
to these patterns should come next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228292 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][MMX] Move MMX DAG node to proper file
Bruno Cardoso Lopes [Thu, 5 Feb 2015 13:22:50 +0000 (13:22 +0000)]
[X86][MMX] Move MMX DAG node to proper file

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228291 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTeach isDereferenceablePointer() to look through bitcast constant expressions.
Michael Kuperstein [Thu, 5 Feb 2015 09:15:37 +0000 (09:15 +0000)]
Teach isDereferenceablePointer() to look through bitcast constant expressions.
This fixes a LICM regression due to the new load+store pair canonicalization.

Differential Revision: http://reviews.llvm.org/D7411

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228284 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions
Craig Topper [Thu, 5 Feb 2015 08:51:06 +0000 (08:51 +0000)]
[X86] Add xrstors/xsavec/xsaves/clflushopt/clwb/pcommit instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228283 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Remove two feature flags that covered sets of instructions that have no pattern...
Craig Topper [Thu, 5 Feb 2015 08:51:02 +0000 (08:51 +0000)]
[X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Fix i64 truncate to i1
Matt Arsenault [Thu, 5 Feb 2015 06:05:13 +0000 (06:05 +0000)]
R600/SI: Fix i64 truncate to i1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228273 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDisable enumeral mismatch warning when compiling llvm with gcc.
Larisse Voufo [Thu, 5 Feb 2015 04:54:51 +0000 (04:54 +0000)]
Disable enumeral mismatch warning when compiling llvm with gcc.
Tested with gcc 4.9.2.
Compiling with -Werror was producing:
.../llvm/lib/Target/X86/X86ISelLowering.cpp: In function 'llvm::SDValue lowerVectorShuffleAsBitMask(llvm::SDLoc, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, llvm::SelectionDAG&)':
.../llvm/lib/Target/X86/X86ISelLowering.cpp:7771:40: error: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' [-Werror=enum-compare]
   V = DAG.getNode(VT.isFloatingPoint() ? X86ISD::FAND : ISD::AND, DL, VT, V,

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228271 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd addrspacecast node to tablegen
Matt Arsenault [Thu, 5 Feb 2015 03:35:34 +0000 (03:35 +0000)]
Add addrspacecast node to tablegen

The node is still defined oddly so that the
address spaces are not operands and not accessible
from tablegen, but as-is this can now be used to write
a ComplexPattern with an addrspacecast root node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228270 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for double / float to EndianStream
Matt Arsenault [Thu, 5 Feb 2015 03:30:08 +0000 (03:30 +0000)]
Add support for double / float to EndianStream

Also add new unit tests for endian::Writer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228269 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImplement new heuristic for complete loop unrolling.
Michael Zolotukhin [Thu, 5 Feb 2015 02:34:00 +0000 (02:34 +0000)]
Implement new heuristic for complete loop unrolling.

Complete loop unrolling can make some loads constant, thus enabling a
lot of other optimizations. To catch such cases, we look for loads that
might become constants and estimate number of instructions that would be
simplified or become dead after substitution.

Suppose we have:
int a[] = {0, 1, 0};
v = 0;
for (i = 0; i < 3; i ++)
  v += b[i]*a[i];

If we completely unroll the loop, we would get:
v = b[0]*a[0] + b[1]*a[1] + b[2]*a[2]

Which then will be simplified to:
v = b[0]* 0 + b[1]* 1 + b[2]* 0

And finally:
v = b[1]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228265 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoValue soft float calls as more expensive in the inliner.
Cameron Esfahani [Thu, 5 Feb 2015 02:09:33 +0000 (02:09 +0000)]
Value soft float calls as more expensive in the inliner.

Summary: When evaluating floating point instructions in the inliner, ask the TTI whether it is an expensive operation.  By default, it's not an expensive operation.  This keeps the default behavior the same as before.  The ARM TTI has been updated to return back TCC_Expensive for targets which don't have hardware floating point.

Reviewers: chandlerc, echristo

Reviewed By: echristo

Subscribers: t.p.northover, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D6936

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228263 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Use patterns instead of hardcoded regs in test. NFC.
Ahmed Bougacha [Thu, 5 Feb 2015 01:52:19 +0000 (01:52 +0000)]
[ARM] Use patterns instead of hardcoded regs in test.  NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228259 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Make testcase more explicit. NFC.
Ahmed Bougacha [Thu, 5 Feb 2015 01:45:28 +0000 (01:45 +0000)]
[ARM] Make testcase more explicit.  NFC.

The q8/d16 thing is silly;  I'd be happy to hear about a better
way to write those tests where simple substitution isn't enough..

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228258 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTry to fix the build in MCValue.cpp
Reid Kleckner [Thu, 5 Feb 2015 01:23:14 +0000 (01:23 +0000)]
Try to fix the build in MCValue.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228256 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixup.
Sean Silva [Thu, 5 Feb 2015 01:13:47 +0000 (01:13 +0000)]

Didn't see these calls in my release build locally when testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228254 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Split out getOperandAs(), NFC
Duncan P. N. Exon Smith [Thu, 5 Feb 2015 01:07:47 +0000 (01:07 +0000)]
IR: Split out getOperandAs(), NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228250 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MC] Remove various unused MCAsmInfo parameters.
Sean Silva [Thu, 5 Feb 2015 00:58:51 +0000 (00:58 +0000)]
[MC] Remove various unused MCAsmInfo parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228244 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Rename 'operator ==()' to 'isKeyOf()', NFC
Duncan P. N. Exon Smith [Thu, 5 Feb 2015 00:51:35 +0000 (00:51 +0000)]
IR: Rename 'operator ==()' to 'isKeyOf()', NFC

`isKeyOf()` is a clearer name than overloading `operator==()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228242 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoADT: Add int64_t interoperability to APSInt
Duncan P. N. Exon Smith [Thu, 5 Feb 2015 00:17:43 +0000 (00:17 +0000)]
ADT: Add int64_t interoperability to APSInt

Add some API to `APSInt` to make it easier to compare with `int64_t`.

  - `APSInt::compareValues(APSInt, APSInt)` returns 1, -1 or 0 for
    greater, lesser, or equal, doing the right thing for mismatched
    "has-sign" and bitwidths.  This is just like `isSameValue()` (and is
    now the implementation of it).
  - `APSInt::get(int64_t)` gets a signed `APSInt`.
  - `operator<(int64_t)`, etc., are implemented trivially via `get()`
    and `compareValues()`.
  - Also added `APSInt::getUnsigned(uint64_t)` to make it easier to test

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228239 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.
Colin LeMahieu [Thu, 5 Feb 2015 00:10:16 +0000 (00:10 +0000)]
[Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228238 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Updating load extend to i64 patterns.
Colin LeMahieu [Wed, 4 Feb 2015 23:55:16 +0000 (23:55 +0000)]
[Hexagon] Updating load extend to i64 patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228237 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] add flag prefer_small_during_initial_shuffle, be a bit more verbose
Kostya Serebryany [Wed, 4 Feb 2015 23:42:42 +0000 (23:42 +0000)]
[fuzzer] add flag prefer_small_during_initial_shuffle, be a bit more verbose

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228235 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Cleaning up i1 load and extension patterns.
Colin LeMahieu [Wed, 4 Feb 2015 23:27:48 +0000 (23:27 +0000)]
[Hexagon] Cleaning up i1 load and extension patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228232 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Simplifying more load and store patterns and using new addressing patterns.
Colin LeMahieu [Wed, 4 Feb 2015 23:23:16 +0000 (23:23 +0000)]
[Hexagon] Simplifying more load and store patterns and using new addressing patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228231 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove useless call to isOSCygMing()
Reid Kleckner [Wed, 4 Feb 2015 23:17:19 +0000 (23:17 +0000)]
Remove useless call to isOSCygMing()

This used to do something when we modeled the Cygwin and MinGW
environments as distinct OSs, but now it is not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228229 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Enable subreg liveness by default
Tom Stellard [Wed, 4 Feb 2015 23:14:18 +0000 (23:14 +0000)]
R600/SI: Enable subreg liveness by default

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228228 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Simplifying some load and store patterns.
Colin LeMahieu [Wed, 4 Feb 2015 23:10:21 +0000 (23:10 +0000)]
[Hexagon] Simplifying some load and store patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228227 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Split out LineField, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:59:18 +0000 (22:59 +0000)]
AsmParser: Split out LineField, NFC

Split out `LineField`, which restricts the legal line numbers.  This
will make it easier to be consistent between different node parsers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228226 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Converting absolute-address load patterns to use AddrGP.
Colin LeMahieu [Wed, 4 Feb 2015 22:54:51 +0000 (22:54 +0000)]
[Hexagon] Converting absolute-address load patterns to use AddrGP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228225 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Converting atomic store/load to use AddrGP addressing.
Colin LeMahieu [Wed, 4 Feb 2015 22:40:36 +0000 (22:40 +0000)]
[Hexagon] Converting atomic store/load to use AddrGP addressing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228223 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't warn or note if bash is missing
Reid Kleckner [Wed, 4 Feb 2015 22:36:52 +0000 (22:36 +0000)]
Don't warn or note if bash is missing

We haven't needed bash on Windows to run the test suite for a long time

Patch by Michael Edwards!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228221 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
Colin LeMahieu [Wed, 4 Feb 2015 22:36:28 +0000 (22:36 +0000)]
[Hexagon] Simplifying some store patterns.  Adding AddrGP addressing forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228220 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoHandle LLVM_USE_SANITIZER=Address;Undefined (and the other way around)
Filipe Cabecinhas [Wed, 4 Feb 2015 22:33:31 +0000 (22:33 +0000)]
Handle LLVM_USE_SANITIZER=Address;Undefined (and the other way around)

Handle LLVM_USE_SANITIZER=Address;Undefined to enable ASan and UBSan
If UBSan is compatible with more of the other sanitizers, maybe we should
deal with this in a better way where we allow combining UBSan with any of
the other sanitizers.

Reviewers: samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228219 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] add -runs=N to limit the number of runs per session. Also, make sure we...
Kostya Serebryany [Wed, 4 Feb 2015 22:20:09 +0000 (22:20 +0000)]
[fuzzer] add -runs=N to limit the number of runs per session. Also, make sure we do some mutations w/o cross over.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228214 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix GCC error caused by r228211
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:13:28 +0000 (22:13 +0000)]
Fix GCC error caused by r228211

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228213 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Reduce boilerplate in DenseMapInfo overrides, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:08:30 +0000 (22:08 +0000)]
IR: Reduce boilerplate in DenseMapInfo overrides, NFC

Minimize the boilerplate required for the `MDNode` subclass
`DenseMapInfo<>` overrides in `LLVMContextImpl`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228212 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Move MDField details to source file, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:05:21 +0000 (22:05 +0000)]
AsmParser: Move MDField details to source file, NFC

Move all the types of `MDField` to an anonymous namespace in the source
file.  This also eliminates the duplication of `ParseMDField()`
declarations in the header for each new field type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228211 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Simplify assertion, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:02:18 +0000 (22:02 +0000)]
AsmParser: Simplify assertion, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228209 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Remove dead code, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 22:00:59 +0000 (22:00 +0000)]
AsmParser: Remove dead code, NFC

This condition is checked in the generic `ParseMDField()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228208 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAsmParser: Simplify MDUnsignedField
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:57:52 +0000 (21:57 +0000)]
AsmParser: Simplify MDUnsignedField

We only need `uint64_t` for storage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228205 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Initialize MDNode abbreviations en masse, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:54:12 +0000 (21:54 +0000)]
IR: Initialize MDNode abbreviations en masse, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228203 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIR: Define MDNode uniquing sets automatically, NFC
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 21:46:12 +0000 (21:46 +0000)]
IR: Define MDNode uniquing sets automatically, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228200 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd code to llvm-objdump so the -section option with -macho will dump ‘C’ string
Kevin Enderby [Wed, 4 Feb 2015 21:38:42 +0000 (21:38 +0000)]
Add code to llvm-objdump so the -section option with -macho will dump ‘C’ string
sections with the Mach-O S_CSTRING_LITERALS section type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228198 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon' try to make sections in comdats SHF_MERGE.
Rafael Espindola [Wed, 4 Feb 2015 21:27:24 +0000 (21:27 +0000)]
Don' try to make sections in comdats SHF_MERGE.

Parts of llvm were not expecting it and we wouldn't print
the entity size of the section.

Given what comdats are used for, having SHF_MERGE sections would be
just a small improvement, so just disable it for now.

Fixes pr22463.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228196 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Put an explicit link to InAlloca.rst
Sean Silva [Wed, 4 Feb 2015 20:51:19 +0000 (20:51 +0000)]
[docs] Put an explicit link to InAlloca.rst

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228192 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Expand misaligned 16-bit memory accesses
Tom Stellard [Wed, 4 Feb 2015 20:49:52 +0000 (20:49 +0000)]
R600/SI: Expand misaligned 16-bit memory accesses

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228190 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Make more store operations legal
Tom Stellard [Wed, 4 Feb 2015 20:49:51 +0000 (20:49 +0000)]
R600/SI: Make more store operations legal

v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces.  We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.

This enables lowering of misaligned stores of these types in the

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228189 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Don't promote i64 stores to v2i32 during DAG legalization
Tom Stellard [Wed, 4 Feb 2015 20:49:49 +0000 (20:49 +0000)]
R600: Don't promote i64 stores to v2i32 during DAG legalization

We take care of this during instruction selection now.  This
fixes a potential infinite loop when lowering misaligned stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228188 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStructurizeCFG: Remove obsolete fix for loop backedge detection
Tom Stellard [Wed, 4 Feb 2015 20:49:47 +0000 (20:49 +0000)]
StructurizeCFG: Remove obsolete fix for loop backedge detection

This is no longer needed now that we are using a reverse post-order

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228187 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoStructurizeCFG: Use a reverse post-order traversal
Tom Stellard [Wed, 4 Feb 2015 20:49:44 +0000 (20:49 +0000)]
StructurizeCFG: Use a reverse post-order traversal

We were previously doing a post-order traversal and operating on the
list in reverse, however this would occasionaly cause backedges for
loops to be visited before some of the other blocks in the loop.

We know use a reverse post-order traversal, which avoids this issue.

The reverse post-order traversal is not completely ideal, so we need
to manually fixup the list to ensure that inner loop backedges are
visited before outer loop backedges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228186 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns...
Colin LeMahieu [Wed, 4 Feb 2015 20:38:01 +0000 (20:38 +0000)]
[Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228184 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd missing test case from r228046
Bill Schmidt [Wed, 4 Feb 2015 20:00:04 +0000 (20:00 +0000)]
Add missing test case from r228046

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228182 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUtils: Resolve cycles under distinct MDNodes
Duncan P. N. Exon Smith [Wed, 4 Feb 2015 19:44:34 +0000 (19:44 +0000)]
Utils: Resolve cycles under distinct MDNodes

Track unresolved nodes under distinct `MDNode`s during `MapMetadata()`,
and resolve them at the end.  Previously, these cycles wouldn't get

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228180 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineCSE: Clear dead-def flag on CSE.
Matthias Braun [Wed, 4 Feb 2015 19:35:16 +0000 (19:35 +0000)]
MachineCSE: Clear dead-def flag on CSE.

In case CSE reuses a previoulsy unused register the dead-def flag has to
be cleared on the def operand, as exposed by the arm64-cse.ll test.

This fixes PR22439 and the corresponding rdar://19694987

Differential Revision: http://reviews.llvm.org/D7395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228178 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd range adapters predecessors() and successors() for BBs
Reid Kleckner [Wed, 4 Feb 2015 19:14:57 +0000 (19:14 +0000)]
Add range adapters predecessors() and successors() for BBs

Use them in two isolated transforms so we know they work and aren't dead

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228173 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[fuzzer] make multi-process execution more verbose; fix mutation to actually respect...
Kostya Serebryany [Wed, 4 Feb 2015 19:10:20 +0000 (19:10 +0000)]
[fuzzer] make multi-process execution more verbose; fix mutation to actually respect mutation depth and to never produce empty units

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228170 91177308-0d34-0410-b5e6-96231b3b80d8