oota-llvm.git
8 years ago[SimplifyLibCalls] Use any_of(). Suggested by David Blaikie!
Davide Italiano [Sat, 28 Nov 2015 22:27:48 +0000 (22:27 +0000)]
[SimplifyLibCalls] Use any_of(). Suggested by David Blaikie!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254239 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SimplifyLibCalls] Fix inverted condition that lead to an uninitialized memory read...
Benjamin Kramer [Sat, 28 Nov 2015 21:43:12 +0000 (21:43 +0000)]
[SimplifyLibCalls] Fix inverted condition that lead to an uninitialized memory read below.

Found by msan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254238 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][AVX] Regenerate ADDSUB tests
Simon Pilgrim [Sat, 28 Nov 2015 19:20:49 +0000 (19:20 +0000)]
[X86][AVX] Regenerate ADDSUB tests

Tidied up triple and regenerate tests using update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254237 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Move value profile format related structures and APIs to common file
Xinliang David Li [Sat, 28 Nov 2015 19:07:09 +0000 (19:07 +0000)]
[PGO] Move value profile format related structures and APIs to common file

This is the last step to enable profile runtime to share the same value prof
data format and reader/writer code with llvm host tools. The VP related
data structures are moved to a section in InstrProfData.inc enabled with macro
INSTR_PROF_VALUE_PROF_DATA, and common API implementations are enabled with
INSTR_PROF_COMMON_API_IMPL. There should be no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254235 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoRevert "[ARM] Generate ABI_optimization_goals build attribute, as described in the...
Renato Golin [Sat, 28 Nov 2015 17:23:46 +0000 (17:23 +0000)]
Revert "[ARM] Generate ABI_optimization_goals build attribute, as described in the ARM ARM."

This reverts commit r254201 and r254202, as it broke test-suite,
self-hosting and sanitizer tests on ARM buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254234 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][FMA] Added 512-bit tests to match 128/256-bit tests coverage
Simon Pilgrim [Sat, 28 Nov 2015 16:04:24 +0000 (16:04 +0000)]
[X86][FMA] Added 512-bit tests to match 128/256-bit tests coverage

As discussed on D14909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254233 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][FMA] More thorough FMA tests
Simon Pilgrim [Sat, 28 Nov 2015 14:28:44 +0000 (14:28 +0000)]
[X86][FMA] More thorough FMA tests

Added FMADD/FMSUB/FNMADD/FNMSUB tests for all types

Added load folding tests for 512-bit vectors

NOTE: Many of the AVX512 FMA instructions don't yet commute/fold correctly

As discussed on D14909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254232 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][AVX2] Tidied up PBROADCAST tests
Simon Pilgrim [Sat, 28 Nov 2015 14:15:40 +0000 (14:15 +0000)]
[X86][AVX2] Tidied up PBROADCAST tests

Tidied up triple and regenerate tests using update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254231 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agollvm/test/CodeGen/SystemZ/alloca-04.ll REQUIRES asserts due to -debug-pass.
NAKAMURA Takumi [Sat, 28 Nov 2015 13:05:49 +0000 (13:05 +0000)]
llvm/test/CodeGen/SystemZ/alloca-04.ll REQUIRES asserts due to -debug-pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254230 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Stack realignment] Handling of aligned allocas.
Jonas Paulsson [Sat, 28 Nov 2015 11:02:32 +0000 (11:02 +0000)]
[Stack realignment] Handling of aligned allocas.

This patch implements dynamic realignment of stack objects for targets
with a non-realigned stack pointer. Behaviour in FunctionLoweringInfo
is changed so that for a target that has StackRealignable set to
false, over-aligned static allocas are considered to be variable-sized
objects and are handled with DYNAMIC_STACKALLOC nodes.

It would be good to group aligned allocas into a single big alloca as
an optimization, but this is yet todo.

SystemZ benefits from this, due to its stack frame layout.

New tests SystemZ/alloca-03.ll for aligned allocas, and
SystemZ/alloca-04.ll for "no-realign-stack" attribute on functions.

Review and help from Ulrich Weigand and Hal Finkel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254227 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse range-based for loops. NFC
Craig Topper [Sat, 28 Nov 2015 08:23:04 +0000 (08:23 +0000)]
Use range-based for loops. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254222 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[TableGen] Use SmallString instead of std::string to build up a string to avoid heap...
Craig Topper [Sat, 28 Nov 2015 08:23:02 +0000 (08:23 +0000)]
[TableGen] Use SmallString instead of std::string to build up a string to avoid heap allocations. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254221 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Add return code for vp rt record init routine to indicate error condition
Xinliang David Li [Sat, 28 Nov 2015 05:47:34 +0000 (05:47 +0000)]
[PGO] Add return code for vp rt record init routine to indicate error condition

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254220 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Allow value profile writer interface to allocated target buffer
Xinliang David Li [Sat, 28 Nov 2015 05:37:01 +0000 (05:37 +0000)]
[PGO] Allow value profile writer interface to allocated target buffer

Raw profile writer needs to write all data of one kind in one continuous block,
so the buffer needs to be pre-allocated and passed to the writer method in
pieces for function profile data. The change adds the support for raw value data
writing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254219 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFunction name cleanup (NFC)
Xinliang David Li [Sat, 28 Nov 2015 05:06:00 +0000 (05:06 +0000)]
Function name cleanup (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254218 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Extract VP data integrity check code into a helper function (NFC)
Xinliang David Li [Sat, 28 Nov 2015 04:56:07 +0000 (04:56 +0000)]
[PGO] Extract VP data integrity check code into a helper function (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254217 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[autoconf] Fix MinGW build
Keno Fischer [Sat, 28 Nov 2015 00:54:12 +0000 (00:54 +0000)]
[autoconf] Fix MinGW build

This is the autoconf analog of r251201. I realize autoconf is
deprecated, but while it's in tree, it should at least be kept working.

Also add the deprecation message to configure.ac such that AutoRegen
actually picks ip up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254215 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPass .ll directly to llvm-link.
Rafael Espindola [Fri, 27 Nov 2015 23:47:15 +0000 (23:47 +0000)]
Pass .ll directly to llvm-link.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254214 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoPass .ll directly to llvm-link
Rafael Espindola [Fri, 27 Nov 2015 23:21:45 +0000 (23:21 +0000)]
Pass .ll directly to llvm-link

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254213 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSamplePGO - Add initial support for inliner annotations.
Diego Novillo [Fri, 27 Nov 2015 23:14:51 +0000 (23:14 +0000)]
SamplePGO - Add initial support for inliner annotations.

This adds two thresholds to the sample profiler to affect inlining
decisions: the concept of global hotness and coldness.

Functions that have accumulated more than a certain fraction of samples at
runtime, are annotated with the InlineHint attribute. Conversely,
functions that accumulate less than a certain fraction of samples, are
annotated with the Cold attribute.

This is very similar to the hints emitted by Clang when using
instrumentation profiles.

Notice that this is a very blunt instrument. A function may have
globally collected a significant fraction of samples, but that does not
necessarily mean that every callsite for that function is hot.

Ideally, we would annotate each callsite with the samples collected at
that callsite. This way, the inliner can incorporate all these weights
into its cost model.

Once the inliner offers this functionality, we can change the hints
emitted here to a more precise per-callsite annotation. For now, this is
providing some measure of speedups with our internal benchmarks. I've
observed speedups of up to 23% (though the geo mean is about 3%). I expect
these numbers to improve as the inliner gets better annotations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254212 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSamplePGO - Fix default threshold for hot callsites.
Diego Novillo [Fri, 27 Nov 2015 23:14:49 +0000 (23:14 +0000)]
SamplePGO - Fix default threshold for hot callsites.

Based on testing of internal benchmarks, I'm lowering this threshold to
a value of 0.1%.  This means that SamplePGO will respect 99.9% of the
original inline decisions when following a profile.

The performance difference is noticeable in some tests. With the
previous threshold, the speedups over baseline -O2 was about 0.63%. With
the new default, the speedups are around 3% on average.

The point of this threshold is not to do more aggressive inlining. When
an inlined callsite crosses this threshold, SamplePGO will redo the
inline decision so that it can better apply the input profile.

By respecting most original inline decisions, we can apply more of the
input profile because the shape of the code follows the profile more
closely.

In the next series, I'll be looking at adding some inline hints for the
cold callsites and for toplevel functions that are hot/cold as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254211 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoModernize the test a bit
Rafael Espindola [Fri, 27 Nov 2015 23:13:17 +0000 (23:13 +0000)]
Modernize the test a bit

Remove out of date comment.
Pass .ll files to llvm-link.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254210 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoSimplify the linking of recursive data.
Rafael Espindola [Fri, 27 Nov 2015 20:28:19 +0000 (20:28 +0000)]
Simplify the linking of recursive data.

Now the ValueMapper has two callbacks. The first one maps the
declaration. The ValueMapper records the mapping and then materializes
the body/initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254209 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFollow-up fix for r254201
Artyom Skrobov [Fri, 27 Nov 2015 16:20:34 +0000 (16:20 +0000)]
Follow-up fix for r254201

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254202 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[ARM] Generate ABI_optimization_goals build attribute, as described in the ARM ARM.
Artyom Skrobov [Fri, 27 Nov 2015 15:30:51 +0000 (15:30 +0000)]
[ARM] Generate ABI_optimization_goals build attribute, as described in the ARM ARM.

Summary:
Since this build attribute corresponds to a whole module, and
different functions in a module may differ in the optimizations
enabled for them, this attribute is emitted after all functions,
and only in the case that the optimization goals for all
functions match.

Reviewers: logan, hans

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D14934

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254201 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add ARMv8.2-A FP16 scalar instructions
Oliver Stannard [Fri, 27 Nov 2015 13:04:48 +0000 (13:04 +0000)]
[AArch64] Add ARMv8.2-A FP16 scalar instructions

ARMv8.2-A adds 16-bit floating point versions of all existing VFP
floating-point instructions. This is an optional extension, so all of
these instructions require the FeatureFullFP16 subtarget feature.

Most of these instructions are the same as the 32- and 64-bit versions,
but with the type field (bits 23-22) set to 0b11. Previously the top bit
of the size field was always 0, so the instruction classes only provided
a 1-bit size field, which I have widened to 2 bits.

Differential Revision: http://reviews.llvm.org/D15014

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254198 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[sanitizer] [dfsan] Unify aarch64 mapping
Adhemerval Zanella [Fri, 27 Nov 2015 12:42:39 +0000 (12:42 +0000)]
[sanitizer] [dfsan] Unify aarch64 mapping

This patch changes the DFSan instrumentation for aarch64 to instead
of using fixes application mask defined by SANITIZER_AARCH64_VMA
to read the application shadow mask value from compiler-rt. The value
is initialized based on runtime VAM detection.

Along with this patch a compiler-rt one will also be added to export
the shadow mask variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254196 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SimplifyLibCalls] Use range-based loop. NFC.
Davide Italiano [Fri, 27 Nov 2015 08:05:40 +0000 (08:05 +0000)]
[SimplifyLibCalls] Use range-based loop. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254193 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[TableGen] Sort pattern predicates before concatenating into a string so that differe...
Craig Topper [Fri, 27 Nov 2015 05:44:04 +0000 (05:44 +0000)]
[TableGen] Sort pattern predicates before concatenating into a string so that different orders of the same set will produce the same string. This can reduce the number of unique predicates in the isel tables. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254192 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Pair a NoVLX with HasAVX512 to match the others and remove a unique predicate...
Craig Topper [Fri, 27 Nov 2015 05:44:02 +0000 (05:44 +0000)]
[X86] Pair a NoVLX with HasAVX512 to match the others and remove a unique predicate check in the isel tables. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254191 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agotest: bail early if tool_path is None
Andrew Wilkins [Fri, 27 Nov 2015 05:07:26 +0000 (05:07 +0000)]
test: bail early if tool_path is None

tool_path will be None for llvm-go if Go cannot be found

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254190 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agotest: check if go_executable is set
Andrew Wilkins [Fri, 27 Nov 2015 04:51:13 +0000 (04:51 +0000)]
test: check if go_executable is set

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254189 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoUse $GO_EXECUTABLE in Go-based lit tests
Andrew Wilkins [Fri, 27 Nov 2015 04:44:51 +0000 (04:44 +0000)]
Use $GO_EXECUTABLE in Go-based lit tests

Summary:
When running tests, pass the GO_EXECUTABLE CMake
cache variable to llvm-go. The "go" binary may
not be in $PATH, or may be different to the one
passed to CMake.

Reviewers: pcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254187 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoTest both input file orders.
Rafael Espindola [Fri, 27 Nov 2015 03:50:34 +0000 (03:50 +0000)]
Test both input file orders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254186 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd missing file.
Rafael Espindola [Fri, 27 Nov 2015 03:47:29 +0000 (03:47 +0000)]
Add missing file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254185 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMake the test a bit more interesting.
Rafael Espindola [Fri, 27 Nov 2015 02:07:37 +0000 (02:07 +0000)]
Make the test a bit more interesting.

It now covers a regular function replacing an available_externally one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254184 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoMC: Simplify handling of temporary symbols in COFF writer.
Peter Collingbourne [Thu, 26 Nov 2015 23:29:27 +0000 (23:29 +0000)]
MC: Simplify handling of temporary symbols in COFF writer.

The COFF object writer was previously adding unnecessary symbols to its
temporary data structures and cleaning them up later. This made the code
harder to understand and caused a bug (aliases classed as temporary symbols
would cause an assertion failure). A much simpler way of handling such
symbols is to ask the layout for their section-relative position when needed.

Tested with a bootstrap on Windows and by building Chrome.

Differential Revision: http://reviews.llvm.org/D14975

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254183 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][FMA] Begun adding AVX512 FMA tests
Simon Pilgrim [Thu, 26 Nov 2015 20:53:28 +0000 (20:53 +0000)]
[X86][FMA] Begun adding AVX512 FMA tests

As discussed on D14909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254180 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[LoopVectorize] Use MapVector rather than DenseMap for MinBWs.
Charlie Turner [Thu, 26 Nov 2015 20:39:51 +0000 (20:39 +0000)]
[LoopVectorize] Use MapVector rather than DenseMap for MinBWs.

The order in which instructions are truncated in truncateToMinimalBitwidths
effects code generation. Switch to a map with a determinisic order, since the
iteration order over a DenseMap is not defined.

This code is not hot, so the difference in container performance isn't
interesting.

Many thanks to David Blaikie for making me aware of MapVector!

Fixes PR25490.

Differential Revision: http://reviews.llvm.org/D14981

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254179 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Now that X86VPermt2 is used in all the avx512_perm_t_sizes just hardcode it...
Craig Topper [Thu, 26 Nov 2015 20:21:29 +0000 (20:21 +0000)]
[X86] Now that X86VPermt2 is used in all the avx512_perm_t_sizes just hardcode it into the patterns instead of passing as an argument. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254177 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Merge X86VPermt2Fp and X86VPermt2Int back together by weakening them just enoug...
Craig Topper [Thu, 26 Nov 2015 20:02:01 +0000 (20:02 +0000)]
[X86] Merge X86VPermt2Fp and X86VPermt2Int back together by weakening them just enough. The SDTCisSameSizeAs introduced in r254138 helps here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254176 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd a few passing lto tests.
Rafael Espindola [Thu, 26 Nov 2015 19:53:12 +0000 (19:53 +0000)]
Add a few passing lto tests.

I found these while trying to get a prototype to bootstrap.

They cover things like
* Handling of non linker visible stuff (append, available_externally)
* Type merging
* Alias to dropped globals
* Dropping linkage when converting to a declaration.

These should hopefully be generally useful for anyone refactoring the
plugin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254174 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Split ISD node for Vfpclass and Vfpclasss so that we can write strong type...
Craig Topper [Thu, 26 Nov 2015 19:41:34 +0000 (19:41 +0000)]
[X86] Split ISD node for Vfpclass and Vfpclasss so that we can write strong type constraints for each that don't cause ambiguous isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254172 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[bugpoint] Fix "Alias must point to a definition" problems
Hal Finkel [Thu, 26 Nov 2015 19:23:49 +0000 (19:23 +0000)]
[bugpoint] Fix "Alias must point to a definition" problems

GlobalAliases may reference function definitions, but not function declarations.

bugpoint would sometimes create invalid IR by deleting a function's body (thus
mutating a function definition into a declaration) without first 'fixing' any
GlobalAliases that reference that function definition.

This change iteratively prevents that issue. Before deleting a function's body,
it scans the module for GlobalAliases which reference that function. When
found, it eliminates them using replaceAllUsesWith.

Fixes PR20788.

Patch by Nick Johnson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254171 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoDisallow aliases to available_externally.
Rafael Espindola [Thu, 26 Nov 2015 19:22:59 +0000 (19:22 +0000)]
Disallow aliases to available_externally.

They are as much trouble as aliases to declarations. They are requiring
the code generator to define a symbol with the same value as another
symbol, but the second symbol is undefined.

If representing this is important for some optimization, we could add
support for available_externally aliases. They would be *required* to
point to a declaration (or available_externally definition).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254170 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Revert part of r254167 to recover bots.
Craig Topper [Thu, 26 Nov 2015 19:13:05 +0000 (19:13 +0000)]
[X86] Revert part of r254167 to recover bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254169 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Lowering of V60/HVX vector types
Krzysztof Parzyszek [Thu, 26 Nov 2015 18:38:27 +0000 (18:38 +0000)]
[Hexagon] Lowering of V60/HVX vector types

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254168 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Strengthen more type constraints to reduce isel table size.
Craig Topper [Thu, 26 Nov 2015 18:31:19 +0000 (18:31 +0000)]
[X86] Strengthen more type constraints to reduce isel table size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254167 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Hexagon V60 HVX intrinsic defintions
Krzysztof Parzyszek [Thu, 26 Nov 2015 16:54:33 +0000 (16:54 +0000)]
[Hexagon] Hexagon V60 HVX intrinsic defintions

Author: Ron Lieberman <ronl@codeaurora.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254165 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips][ias] Range check uimm5 operands and fix several bugs this revealed.
Daniel Sanders [Thu, 26 Nov 2015 16:35:41 +0000 (16:35 +0000)]
[mips][ias] Range check uimm5 operands and fix several bugs this revealed.

Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254164 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add ARMv8.2-A new AT instruction variants
Oliver Stannard [Thu, 26 Nov 2015 15:34:44 +0000 (15:34 +0000)]
[AArch64] Add ARMv8.2-A new AT instruction variants

ARMv8.2-A adds new variants of the "at" (address translate) system
instruction, which take the PSTATE.PAN bit (added in ARMv8.1-A). These
are a required part of ARMv8.2-A, so no additional subtarget features
are required.

Differential Revision: http://reviews.llvm.org/D15018

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254159 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoARM: address WOA unsigned division overflow crash
Martell Malone [Thu, 26 Nov 2015 15:34:03 +0000 (15:34 +0000)]
ARM: address WOA unsigned division overflow crash

Building on r253865 the crash is not limited to signed overflows.

Disable custom handling of unsigned 32-bit and 64-bit integer divide.
Add test cases for both 32-bit and 64-bit unsigned integer overflow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254158 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add ARMv8.2-A UAO PSTATE bit
Oliver Stannard [Thu, 26 Nov 2015 15:32:30 +0000 (15:32 +0000)]
[AArch64] Add ARMv8.2-A UAO PSTATE bit

ARMv8.2-A adds a new PSTATE bit, PSTATE.UAO, which allows the LDTR/STTR
instructions to behave the same as LDR/STR with respect to execute-only
pages at higher privilege levels. New variants of the MSR/MRS
instructions are added to allow reading and writing this bit. It is a
required part of ARMv8.2-A, so no additional subtarget features are
required.

Differential Revision: http://reviews.llvm.org/D15020

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254157 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add ARMv8.2-A persistent memory instruction
Oliver Stannard [Thu, 26 Nov 2015 15:28:47 +0000 (15:28 +0000)]
[AArch64] Add ARMv8.2-A persistent memory instruction

ARMv8.2-A adds the "dc cvap" instruction, which is a system instruction
that cleans caches to the point of persistence (for systems that have
persistent memory). It is a required part of ARMv8.2-A, so no additional
subtarget features are required.

Differential Revision: http://reviews.llvm.org/D15016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254156 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register
Oliver Stannard [Thu, 26 Nov 2015 15:26:10 +0000 (15:26 +0000)]
[AArch64] Add ARMv8.2-A ID_A64MMFR2_EL1 register

ARMv8.2-A adds a new ID register, ID_A64MMFR2_EL1, which behaves in the
same way as ID_A64MMFR0_EL1 and ID_A64MMFR1_EL1. It is a required part
of ARMv8.2-A, so no additional subtarget features are required.

Differential Revision: http://reviews.llvm.org/D15017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254155 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[AArch64] Add subtarget features for ARMv8.2-A
Oliver Stannard [Thu, 26 Nov 2015 15:23:32 +0000 (15:23 +0000)]
[AArch64] Add subtarget features for ARMv8.2-A

This adds subtarget features for ARMv8.2-A, which builds on (and
requires the features from) ARMv8.1-A. Most assembler-visible features
of ARMv8.2-A are system instructions, and are all required parts of the
architecture, so just depend on the HasV8_2aOps subtarget feature. There
is also one large, optional feature, which adds 16-bit floating point
versions of all existing floating-point instructions (VFP and SIMD),
this is represented by the FeatureFullFP16 subtarget feature.

Differential Revision: http://reviews.llvm.org/D15013

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254154 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips][ias] Explicitly disable IAS on tests that depend on not assembling.
Daniel Sanders [Thu, 26 Nov 2015 11:23:03 +0000 (11:23 +0000)]
[mips][ias] Explicitly disable IAS on tests that depend on not assembling.

Summary:
no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register
in inline assembly and expects the compiler to insert a move to an
even-numbered register.

inlineasm-operand-code.ll and inlineasm_constraint.ll:
Checks for IAS's output will be added once a matcher bug is resolved. This bug
causes the canonical output emitted by IAS to be incorrect for uimm16 constants
with the MSB set. We will still need the non-IAS checks at this point since
these tests primarily test formatting of operands.

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254148 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[mips][ias] Replace anchor comments with anchor instructions in tests.
Daniel Sanders [Thu, 26 Nov 2015 10:26:18 +0000 (10:26 +0000)]
[mips][ias] Replace anchor comments with anchor instructions in tests.

Summary:
This is because IAS will delete the comments. NFC at the moment but it will
prevent a failure once IAS is the default.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254147 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SimplifyLibCalls] Don't depend on a called function having a name, it might be an...
Benjamin Kramer [Thu, 26 Nov 2015 09:51:17 +0000 (09:51 +0000)]
[SimplifyLibCalls] Don't depend on a called function having a name, it might be an indirect call.

Fixes the crasher in PR25651 and related crashers using the same pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254145 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Strengthen more type constraints to reduce isel table size.
Craig Topper [Thu, 26 Nov 2015 07:58:20 +0000 (07:58 +0000)]
[X86] Strengthen more type constraints to reduce isel table size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254142 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoX86-FMA3: Improved/enabled the memory folding optimization for scalar loads
Vyacheslav Klochkov [Thu, 26 Nov 2015 07:45:30 +0000 (07:45 +0000)]
X86-FMA3: Improved/enabled the memory folding optimization for scalar loads
generated for _mm_losd_s{s,d}() intrinsics and used in scalar FMAs generated
for FMA intrinsics _mm_f{madd,msub,nmadd,nmsub}_s{s,d}().

Reviewer: David Kreitzer
Differential Revision: http://reviews.llvm.org/D14762

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254140 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86] Strengthen the type constraints on X86psadbw and X86dbpsadbw to reduce some...
Craig Topper [Thu, 26 Nov 2015 07:02:21 +0000 (07:02 +0000)]
[X86] Strengthen the type constraints on X86psadbw and X86dbpsadbw to reduce some of the type checks in the isel matching tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254139 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ensure...
Craig Topper [Thu, 26 Nov 2015 07:02:18 +0000 (07:02 +0000)]
[SelectionDAG] Add a SDTCisSameSizeAs type constraint that can be used to ensure vector widths match even if the element size and count don't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254138 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd type constraints to masked_load/masked_store to ensure the mask vector has the...
Craig Topper [Thu, 26 Nov 2015 06:30:42 +0000 (06:30 +0000)]
Add type constraints to masked_load/masked_store to ensure the mask vector has the same number of elements as the other vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254137 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[TableGen] Flip reversed comments.
Craig Topper [Thu, 26 Nov 2015 06:30:40 +0000 (06:30 +0000)]
[TableGen] Flip reversed comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254136 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] HVX vector register classes and more isel patterns
Krzysztof Parzyszek [Thu, 26 Nov 2015 04:33:11 +0000 (04:33 +0000)]
[Hexagon] HVX vector register classes and more isel patterns

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254132 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU: Fix typo
Tom Stellard [Thu, 26 Nov 2015 02:04:11 +0000 (02:04 +0000)]
AMDGPU: Fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254120 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[OperandBundles] Treat "deopt" operand bundles specially
Sanjoy Das [Thu, 26 Nov 2015 01:16:05 +0000 (01:16 +0000)]
[OperandBundles] Treat "deopt" operand bundles specially

Teach LLVM optimize to more precisely in the presence of "deopt" operand
bundles.  "deopt" operand bundles imply that the call they're attached
to is at least `readonly` (i.e. they don't imply clobber semantics), and
they don't capture their bundle operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254118 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsic
Tom Stellard [Thu, 26 Nov 2015 00:43:29 +0000 (00:43 +0000)]
AMDGPU: Add llvm.amdgcn.dispatch.ptr intrinsic

Summary:
This returns a pointer to the dispatch packet, which can be used to load
information about the kernel dispach.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D14898

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254116 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[libFuzzer] clean up the docs, add one more link
Kostya Serebryany [Thu, 26 Nov 2015 00:12:57 +0000 (00:12 +0000)]
[libFuzzer] clean up the docs, add one more link

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254115 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix a typo introduced in previous patches
Xinliang David Li [Thu, 26 Nov 2015 00:02:23 +0000 (00:02 +0000)]
Fix a typo introduced in previous patches

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254112 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Implement ValueProfiling Closure interfaces for runtime value profile data
Xinliang David Li [Wed, 25 Nov 2015 23:31:18 +0000 (23:31 +0000)]
[PGO] Implement ValueProfiling Closure interfaces for runtime value profile data

This is one of the many steps to commonize value profiling support between profile
runtime and compiler/llvm tools.

After this change, profiler runtime now can share the same C APIs to do VP
serialization/deseriazation with LLVM host tools (and produces value data
in identical format between indexed and raw profile).

It is not yet enabled in profiler runtime yet.

Also added a unit test case to test runtime profile data serialization/deserialization
interfaces implemented using common closure code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254110 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[safestack] Fix alignment of dynamic allocas.
Evgeniy Stepanov [Wed, 25 Nov 2015 22:52:30 +0000 (22:52 +0000)]
[safestack] Fix alignment of dynamic allocas.

Fixes PR25588.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254109 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix a use-after-free in `llvm-config`.
Richard Diamond [Wed, 25 Nov 2015 22:49:48 +0000 (22:49 +0000)]
Fix a use-after-free in `llvm-config`.

Summary:
This could happen if `GetComponentNames` is true, because `Name` from
`VisitComponent` would reference a stack instance of `std::string` in
`ComputeLibsForComponents`.

Reviewers: beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254108 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Fix inline asm support for i64 operands.
Dan Gohman [Wed, 25 Nov 2015 22:28:50 +0000 (22:28 +0000)]
[WebAssembly] Fix inline asm support for i64 operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254106 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Fold setne and seteq comparisons into selects.
Dan Gohman [Wed, 25 Nov 2015 22:13:48 +0000 (22:13 +0000)]
[WebAssembly] Fold setne and seteq comparisons into selects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254104 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[libFuzzer] add a flag -exact_artifact_path
Kostya Serebryany [Wed, 25 Nov 2015 21:40:46 +0000 (21:40 +0000)]
[libFuzzer] add a flag -exact_artifact_path

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254100 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[Hexagon] Treat transfers of FP immediates are pseudo instructions
Krzysztof Parzyszek [Wed, 25 Nov 2015 21:40:03 +0000 (21:40 +0000)]
[Hexagon] Treat transfers of FP immediates are pseudo instructions

This is a temporary fix to address ICE on 2005-10-21-longlonggtu.ll.
The proper fix will be to use A2_tfrsi, but it will need more work to
teach all users of A2_tfrsi to also expect a floating-point operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254099 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Add some comments. NFC.
Dan Gohman [Wed, 25 Nov 2015 21:32:06 +0000 (21:32 +0000)]
[WebAssembly] Add some comments. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254096 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU/SI: select S_ABS_I32 when possible (v2)
Marek Olsak [Wed, 25 Nov 2015 21:22:45 +0000 (21:22 +0000)]
AMDGPU/SI: select S_ABS_I32 when possible (v2)

v2: added more tests, moved the SALU->VALU conversion to a separate function

It looks like it's not possible to get subregisters in the S_ABS lowering
code, and I don't feel like guessing without testing what the correct code
would look like.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254095 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Fix WebAssembly register numbering for registers added late.
Dan Gohman [Wed, 25 Nov 2015 21:13:02 +0000 (21:13 +0000)]
[WebAssembly] Fix WebAssembly register numbering for registers added late.

If virtual registers are created late, mappings to WebAssembly
registers need to be added explicitly. This patch adds a function
to do so and teaches WebAssemblyPeephole to use it. This fixes
an out-of-bounds access on the WARegs vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254094 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[SCCP] More informative message if we don't know how to handle a terminator.
Davide Italiano [Wed, 25 Nov 2015 21:03:36 +0000 (21:03 +0000)]
[SCCP] More informative message if we don't know how to handle a terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254093 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU: Check feature attributes in SIMachineFunctionInfo
Matt Arsenault [Wed, 25 Nov 2015 20:55:12 +0000 (20:55 +0000)]
AMDGPU: Check feature attributes in SIMachineFunctionInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254091 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAdd hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default
Krzysztof Parzyszek [Wed, 25 Nov 2015 20:30:59 +0000 (20:30 +0000)]
Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the default

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254089 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU: Add some tests for promotion of v2i64 scalar_to_vector
Matt Arsenault [Wed, 25 Nov 2015 20:01:03 +0000 (20:01 +0000)]
AMDGPU: Add some tests for promotion of v2i64 scalar_to_vector

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254087 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAMDGPU: Make v2i64/v2f64 legal types.
Matt Arsenault [Wed, 25 Nov 2015 19:58:34 +0000 (19:58 +0000)]
AMDGPU: Make v2i64/v2f64 legal types.

They can be loaded and stored, so count them as legal. This is
mostly to fix a number of common cases for load/store merging.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254086 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoExpose isXxxConstant() functions from SelectionDAGNodes.h (NFC)
Artyom Skrobov [Wed, 25 Nov 2015 19:41:11 +0000 (19:41 +0000)]
Expose isXxxConstant() functions from SelectionDAGNodes.h (NFC)

Summary:
Many target lowerings copy-paste the code to test SDValues for known constants.
This code can instead be shared in SelectionDAG.cpp, and reused in the targets.

Reviewers: MatzeB, andreadb, tstellarAMD

Subscribers: arsenm, jyknight, llvm-commits

Differential Revision: http://reviews.llvm.org/D14945

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254085 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Use a physical register to describe ARGUMENT liveness.
Dan Gohman [Wed, 25 Nov 2015 19:36:19 +0000 (19:36 +0000)]
[WebAssembly] Use a physical register to describe ARGUMENT liveness.

Instead of trying to move ARGUMENT instructions back up to the top after
they've been scheduled or sunk down, use a fake physical register to
create a liveness constraint that prevents ARGUMENT instructions from
moving down in the first place. This is still not entirely ideal, however
it is more robust than letting them move and moving them back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254084 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PGO] Regroup functions in better order (NFC)
Xinliang David Li [Wed, 25 Nov 2015 19:13:00 +0000 (19:13 +0000)]
[PGO] Regroup functions in better order (NFC)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254080 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Clean up several FIXME comments.
Dan Gohman [Wed, 25 Nov 2015 18:13:18 +0000 (18:13 +0000)]
[WebAssembly] Clean up several FIXME comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254079 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Make several tests more strict.
Dan Gohman [Wed, 25 Nov 2015 17:33:15 +0000 (17:33 +0000)]
[WebAssembly] Make several tests more strict.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254077 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Support for register stackifying with load and store instructions.
Dan Gohman [Wed, 25 Nov 2015 16:55:01 +0000 (16:55 +0000)]
[WebAssembly] Support for register stackifying with load and store instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254076 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Codegen support for ISD::ExternalSymbol
Dan Gohman [Wed, 25 Nov 2015 16:44:29 +0000 (16:44 +0000)]
[WebAssembly] Codegen support for ISD::ExternalSymbol

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254075 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Add 'final' to some classes. NFC.
Dan Gohman [Wed, 25 Nov 2015 16:29:24 +0000 (16:29 +0000)]
[WebAssembly] Add 'final' to some classes. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254073 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[WebAssembly] Whitespace consistency. NFC.
Dan Gohman [Wed, 25 Nov 2015 16:26:14 +0000 (16:26 +0000)]
[WebAssembly] Whitespace consistency. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254071 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agofix typo; NFC
Sanjay Patel [Wed, 25 Nov 2015 15:33:36 +0000 (15:33 +0000)]
fix typo; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254069 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[PowerPC] Don't generate mfocrf on the e500mc
Hal Finkel [Wed, 25 Nov 2015 10:14:31 +0000 (10:14 +0000)]
[PowerPC] Don't generate mfocrf on the e500mc

The e500mc does not actually support the mfocrf instruction; update the
processor definitions to reflect that fact.

Patch by Tom Rix (with some test-case cleanup by me).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254064 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoAccept any stack offset, including none, here.
Eric Christopher [Wed, 25 Nov 2015 09:21:36 +0000 (09:21 +0000)]
Accept any stack offset, including none, here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254062 91177308-0d34-0410-b5e6-96231b3b80d8

8 years agoFix some places where we were assuming that memory type had been legalized
Eric Christopher [Wed, 25 Nov 2015 09:11:53 +0000 (09:11 +0000)]
Fix some places where we were assuming that memory type had been legalized
to a simple type when lowering a truncating store of a vector type. In this
case for an EVT we'll return Expand as we should in all of the cases anyhow.

The testcase triggered at the one in VectorLegalizer::LegalizeOp, inspection
found the rest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254061 91177308-0d34-0410-b5e6-96231b3b80d8

8 years ago[X86][AVX] Regenerate Splat OptSize tests
Simon Pilgrim [Wed, 25 Nov 2015 09:06:17 +0000 (09:06 +0000)]
[X86][AVX] Regenerate Splat OptSize tests

Tidied up triple and regenerate tests using update_llc_test_checks.py

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@254060 91177308-0d34-0410-b5e6-96231b3b80d8