oota-llvm.git
9 years agoUse early returns to reduce indentation.
David Blaikie [Fri, 3 Apr 2015 21:32:06 +0000 (21:32 +0000)]
Use early returns to reduce indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234057 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a typo
David Majnemer [Fri, 3 Apr 2015 20:56:24 +0000 (20:56 +0000)]
Fix a typo

CHECK-LABEL had the wrong function name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234051 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[InstCombine] Use DataLayout to determine vector element width
David Majnemer [Fri, 3 Apr 2015 20:18:40 +0000 (20:18 +0000)]
[InstCombine] Use DataLayout to determine vector element width

InstCombine didn't realize that it needs to use DataLayout to determine
how wide pointers are.  This lead to assertion failures.

This fixes PR23113.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234046 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFixing a build error
Andrew Kaylor [Fri, 3 Apr 2015 19:55:30 +0000 (19:55 +0000)]
Fixing a build error

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234045 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFixing build warnings.
Andrew Kaylor [Fri, 3 Apr 2015 19:45:32 +0000 (19:45 +0000)]
Fixing build warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234043 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[opaque pointer type] More GEP API migrations in IRBuilder uses
David Blaikie [Fri, 3 Apr 2015 19:41:44 +0000 (19:41 +0000)]
[opaque pointer type] More GEP API migrations in IRBuilder uses

The plan here is to push the API changes out from the common components
(like Constant::getGetElementPtr and IRBuilder::CreateGEP related
functions) and just update callers to either pass the type if it's
obvious, or pass null.

Do this with LoadInst as well and anything else that comes up, then to
start porting specific uses to not pass null anymore - this may require
some refactoring in each case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234042 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Handle nested landing pads in outlined catch handlers
Andrew Kaylor [Fri, 3 Apr 2015 19:37:50 +0000 (19:37 +0000)]
[WinEH] Handle nested landing pads in outlined catch handlers

Differential Revision: http://reviews.llvm.org/D8596

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234041 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCodeGen: Assert that inlined-at locations agree
Duncan P. N. Exon Smith [Fri, 3 Apr 2015 19:20:26 +0000 (19:20 +0000)]
CodeGen: Assert that inlined-at locations agree

As a follow-up to r234021, assert that a debug info intrinsic variable's
`MDLocalVariable::getInlinedAt()` always matches the
`MDLocation::getInlinedAt()` of its `!dbg` attachment.

The goal here is to get rid of `MDLocalVariable::getInlinedAt()`
entirely (PR22778), but I'll let these assertions bake for a while
first.

If you have an out-of-tree backend that just broke, you're probably
attaching the wrong `DebugLoc` to a `DBG_VALUE` instruction.  The one
you want is the location that was attached to the corresponding
`@llvm.dbg.declare` or `@llvm.dbg.value` call that you started with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234038 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Fold cast into assertion based on review feedback
Reid Kleckner [Fri, 3 Apr 2015 18:18:06 +0000 (18:18 +0000)]
[WinEH] Fold cast into assertion based on review feedback

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234034 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[GraphWriter] Attempt to open .dot files with xdg-open/open first
Matthias Braun [Fri, 3 Apr 2015 17:22:36 +0000 (17:22 +0000)]
[GraphWriter] Attempt to open .dot files with xdg-open/open first

Most desktop environments let the users specify his preferred application per
file type. On mac/linux we can use open/xdg-open for that and should try this
first before starting a heuristic search for various programs.

Differential Revision: http://reviews.llvm.org/D6534

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234031 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking; remove unnecessary testing params
Sanjay Patel [Fri, 3 Apr 2015 17:17:50 +0000 (17:17 +0000)]
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234029 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking; remove unnecessary testing params
Sanjay Patel [Fri, 3 Apr 2015 17:13:31 +0000 (17:13 +0000)]
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234027 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoSelectionDAG: Use specialized metadata nodes in EmitFuncArgumentDbgValue(), NFC
Duncan P. N. Exon Smith [Fri, 3 Apr 2015 17:11:42 +0000 (17:11 +0000)]
SelectionDAG: Use specialized metadata nodes in EmitFuncArgumentDbgValue(), NFC

Use `MDLocalVariable` and `MDExpression` directly for the arguments of
`EmitFuncArgumentDbgValue()` to simplify a follow-up patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234026 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking; remove unnecessary testing params
Sanjay Patel [Fri, 3 Apr 2015 17:09:37 +0000 (17:09 +0000)]
use update_llc_test_checks.py to tighten checking; remove unnecessary testing params

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234024 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking
Sanjay Patel [Fri, 3 Apr 2015 17:02:48 +0000 (17:02 +0000)]
use update_llc_test_checks.py to tighten checking

remove redundant and unnecessary test parameters

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234022 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoVerifier: Check that inlined-at locations agree
Duncan P. N. Exon Smith [Fri, 3 Apr 2015 16:54:30 +0000 (16:54 +0000)]
Verifier: Check that inlined-at locations agree

Check that the `MDLocalVariable::getInlinedAt()` in a debug info
intrinsic's variable always matches the `MDLocation::getInlinedAt()` of
its `!dbg` attachment.

The goal here is to get rid of `MDLocalVariable::getInlinedAt()`
entirely (PR22778), since it's expensive and unnecessary, but I'll let
this verifier check bake for a while (a week maybe?) first.  I've
updated the testcases that had the wrong value for `inlinedAt:`.

This checks that things are sane in the IR, but currently things go out
of whack in a few places in the backend.  I'll follow shortly with
assertions in the backend (with code fixes).

If you have out-of-tree testcases that just started failing, here's how
I updated these ones:

 1. The verifier check gives you the basic block, function, instruction,
    and relevant metadata arguments (metadata numbering doesn't
    necessarily match the source file, unfortunately).
 2. Look at the `@llvm.dbg.*()` instruction, and compare the
    `inlinedAt:` fields of the variable argument (second `metadata`
    argument) and the `!dbg` attachment.
 3. Figure out based on the variable `scope:` chain and the functions in
    the file whether the variable has been inlined (and into what), so
    you can determine which `inlinedAt:` is actually correct.  In all of
    the in-tree testcases, the `!MDLocation()` was correct and the
    `!MDLocalVariable()` was wrong, but YMMV.
 4. Duplicate the metadata that you're going to change, and add/drop the
    `inlinedAt:` field from one of them.  Be careful that the other
    references to the same metadata node point at the correct one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234021 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoadd checks; remove redundant testing parameters
Sanjay Patel [Fri, 3 Apr 2015 16:44:42 +0000 (16:44 +0000)]
add checks; remove redundant testing parameters

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234020 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoCodeGen: Fix MachineInstr::print() for DBG_VALUE
Duncan P. N. Exon Smith [Fri, 3 Apr 2015 16:23:04 +0000 (16:23 +0000)]
CodeGen: Fix MachineInstr::print() for DBG_VALUE

Grab the `MDLocalVariable` from the second-to-last argument; the last
argument is an `MDExpression`, and mixing them up will crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234019 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[MachineLICM] Small cleanup: Constify and rangeify.
Daniel Jasper [Fri, 3 Apr 2015 16:19:48 +0000 (16:19 +0000)]
[MachineLICM] Small cleanup: Constify and rangeify.

NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234018 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agouse update_llc_test_checks.py to tighten checking; remove darwin and sandybridge...
Sanjay Patel [Fri, 3 Apr 2015 16:06:58 +0000 (16:06 +0000)]
use update_llc_test_checks.py to tighten checking; remove darwin and sandybridge overspecification

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234017 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdded vector tests for DAGCombiner::ReassociateOps
Simon Pilgrim [Fri, 3 Apr 2015 15:04:46 +0000 (15:04 +0000)]
Added vector tests for DAGCombiner::ReassociateOps

Missing vector tests for rL233482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234015 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Added SSE4.2 CRC32 memory folding patterns + tests
Simon Pilgrim [Fri, 3 Apr 2015 14:24:40 +0000 (14:24 +0000)]
[X86] Added SSE4.2 CRC32 memory folding patterns + tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234013 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Enable splat generation for BUILD_VECTOR with little endian
Bill Schmidt [Fri, 3 Apr 2015 13:48:24 +0000 (13:48 +0000)]
[PowerPC] Enable splat generation for BUILD_VECTOR with little endian

When enabling PPC64LE, I disabled some optimizations of BUILD_VECTOR
nodes for little endian because wrong results were produced.  I've
subsequently investigated and found this is due to a call to
BuildVectorSDNode::isConstantSplat that was always specifying
big-endian.  With this changed to correctly identify the target
endianness, the optimizations work as expected.

I found another case of a call to the same method with big-endian
hardcoded, in PPC::isAllNegativeZeroVector().  I discovered this was
an orphaned method with no callers, so I've just removed it.

The existing test/CodeGen/PowerPC/vec_constants.ll checks these
optimizations, so for testing I've just added a variant for little
endian.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234011 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][3DNow] Added 3DNow! memory folding patterns + tests
Simon Pilgrim [Fri, 3 Apr 2015 11:50:30 +0000 (11:50 +0000)]
[X86][3DNow] Added 3DNow! memory folding patterns + tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234008 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86][MMX] Added MMX stack folding tests
Simon Pilgrim [Fri, 3 Apr 2015 11:01:15 +0000 (11:01 +0000)]
[X86][MMX] Added MMX stack folding tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234006 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTOR
Simon Pilgrim [Fri, 3 Apr 2015 10:02:21 +0000 (10:02 +0000)]
[DAGCombiner] Combine shuffles of BUILD_VECTOR and SCALAR_TO_VECTOR

This patch attempts to fold the shuffling of 'scalar source' inputs - BUILD_VECTOR and SCALAR_TO_VECTOR nodes - if the shuffle node is the only user. This folds away a lot of unnecessary shuffle nodes, and allows quite a bit of constant folding that was being missed.

Differential Revision: http://reviews.llvm.org/D8516

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234004 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMC: For variable symbols, maintain MCSymbol::Section as a cache.
Peter Collingbourne [Fri, 3 Apr 2015 01:46:11 +0000 (01:46 +0000)]
MC: For variable symbols, maintain MCSymbol::Section as a cache.

Fixes PR19582.

Previously, when an asm assignment (.set or =) was created, we would look up
the section immediately in MCSymbol::setVariableValue. This caused symbols
to receive the wrong section if the RHS of the assignment had not been seen
yet. This had a knock-on effect in the object file emitters, causing them
to emit extra symbols, or to give symbols the wrong visibility or the wrong
section. For example, in the following asm:

.data
.Llocal:

.text
leaq .Llocal1(%rip), %rdi
.Llocal1 = .Llocal2
.Llocal2 = .Llocal

the first assignment would give .Llocal1 a null section, which would never get
fixed up by the second assignment. This would cause the ELF object file emitter
to consider .Llocal1 to be an undefined symbol and give it external linkage,
even though .Llocal1 should not have been emitted at all in the object file.

Or in the following asm:

alias_to_local = Ltmp0
Ltmp0:

the Mach-O object file emitter would give the alias_to_local symbol a n_type
of N_SECT and a n_sect of 0.  This is invalid under the Mach-O specification,
which requires N_SECT symbols to receive a non-zero section number if the
symbol is defined in a section in the object file.

https://developer.apple.com/library/mac/documentation/DeveloperTools/Conceptual/MachORuntime/#//apple_ref/c/tag/nlist

After this change we do not look up the section when the assignment is created,
but instead look it up on demand and store it in Section, which is treated
as a cache if the symbol is a variable symbol.

This change also fixes a bug in MCExpr::FindAssociatedSection. Previously,
if we saw a subtraction, we would return the first referenced section, even in
cases where we should have been returning the absolute pseudo-section. Now we
always return the absolute pseudo-section for expressions that subtract two
section-derived expressions. This isn't always correct (e.g. if one of the
sections ends up being laid out at an absolute address), but it's probably
the best we can do without more context.

This allows us to remove code in two places where we appear to have been
working around this bug, in MachObjectWriter::markAbsoluteVariableSymbols
and in X86AsmPrinter::EmitStartOfAsmFile.

Re-applies r233595 (aka D8586), which was reverted in r233898.

Differential Revision: http://reviews.llvm.org/D8798

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233995 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReturn iterator from BasicBlock::eraseFromParent
Daniel Berlin [Fri, 3 Apr 2015 01:20:33 +0000 (01:20 +0000)]
Return iterator from BasicBlock::eraseFromParent

Summary:
Same as the last patch, but for BasicBlock
(Requires same code movement)

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8801

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233992 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[opaque pointer types] Push explicit type parameter for geps through the constant...
David Blaikie [Fri, 3 Apr 2015 01:15:16 +0000 (01:15 +0000)]
[opaque pointer types] Push explicit type parameter for geps through the constant folders

Next: more IRBuilder changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233991 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoARM: Handle physreg targets in RegPair hints gracefully
Matthias Braun [Fri, 3 Apr 2015 00:18:38 +0000 (00:18 +0000)]
ARM: Handle physreg targets in RegPair hints gracefully

Register coalescing can change the target of a RegPair hint to a
physreg, we should not crash on this. This also slightly improved the
way ARMBaseRegisterInfo::updateRegAllocHint() works.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233987 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMachineRegisterInfo: Make it clear that hints are for vregs
Matthias Braun [Fri, 3 Apr 2015 00:18:33 +0000 (00:18 +0000)]
MachineRegisterInfo: Make it clear that hints are for vregs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233986 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agollvm/examples/BrainF: Give an explicit pointee type to ConstantExpr::getGetElementPtr...
NAKAMURA Takumi [Thu, 2 Apr 2015 22:44:00 +0000 (22:44 +0000)]
llvm/examples/BrainF: Give an explicit pointee type to ConstantExpr::getGetElementPtr(ty...), according to r233938.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233983 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ASan] Don't use stack malloc for 32-bit functions using inline asm
Reid Kleckner [Thu, 2 Apr 2015 21:44:55 +0000 (21:44 +0000)]
[ASan] Don't use stack malloc for 32-bit functions using inline asm

This prevents us from running out of registers in the backend.

Introducing stack malloc calls prevents the backend from recognizing the
inline asm operands as stack objects. When the backend recognizes a
stack object, it doesn't need to materialize the address of the memory
in a physical register. Instead it generates a simple SP-based memory
operand. Introducing a stack malloc forces the backend to find a free
register for every memory operand. 32-bit x86 simply doesn't have enough
registers for this to succeed in most cases.

Reviewers: kcc, samsonov

Differential Revision: http://reviews.llvm.org/D8790

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233979 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix unused variable in NDEBUG builds
Reid Kleckner [Thu, 2 Apr 2015 21:43:22 +0000 (21:43 +0000)]
Fix unused variable in NDEBUG builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233978 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SLSR] handles off bounds GEPs
Jingyue Wu [Thu, 2 Apr 2015 21:18:32 +0000 (21:18 +0000)]
[SLSR] handles off bounds GEPs

Summary:
The old requirement on GEP candidates being in bounds is unnecessary.
For off-bound GEPs, we still have

  &B[i * S] = B + (i * S) * e = B + (i * e) * S

Test Plan: slsr_offbound_gep in slsr-gep.ll

Reviewers: meheff

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8809

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233949 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Make llvm.eh.actions use frameescape indices for catch params
Reid Kleckner [Thu, 2 Apr 2015 21:13:31 +0000 (21:13 +0000)]
[WinEH] Make llvm.eh.actions use frameescape indices for catch params

This makes it possible to use the same representation of llvm.eh.actions
in outlined handlers as we use in the parent function because i32's are
just constants that can be copied freely between functions.

I had to add a sentinel alloca to the list of child allocas so that we
don't try to sink the catch object into the handler. Normally, one would
use nullptr for this kind of thing, but TinyPtrVector doesn't support
null elements. More than that, it's elements have to have a suitable
alignment. Therefore, I settled on this for my sentinel:

  AllocaInst *getCatchObjectSentinel() {
    return static_cast<AllocaInst *>(nullptr) + 1;
  }

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233947 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vector
Sanjay Patel [Thu, 2 Apr 2015 20:21:52 +0000 (20:21 +0000)]
[AVX] Improve insertion of i8 or i16 into low element of 256-bit zero vector

Without this patch, we split the 256-bit vector into halves and produced something like:
movzwl (%rdi), %eax
vmovd %eax, %xmm0
vxorps %xmm1, %xmm1, %xmm1
vblendps $15, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]

Now, we eliminate the xor and blend because those zeros are free with the vmovd:
        movzwl  (%rdi), %eax
        vmovd   %eax, %xmm0

This should be the final fix needed to resolve PR22685:
https://llvm.org/bugs/show_bug.cgi?id=22685

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233941 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[opaque pointer type] API migration for GEP constant factories
David Blaikie [Thu, 2 Apr 2015 18:55:32 +0000 (18:55 +0000)]
[opaque pointer type] API migration for GEP constant factories

Require the pointee type to be passed explicitly and assert that it is
correct. For now it's possible to pass nullptr here (and I've done so in
a few places in this patch) but eventually that will be disallowed once
all clients have been updated or removed. It'll be a long road to get
all the way there... but if you have the cahnce to update your callers
to pass the type explicitly without depending on a pointer's element
type, that would be a good thing to do soon and a necessary thing to do
eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233938 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Add a comment to make it explicit why we increased the complexity.
Quentin Colombet [Thu, 2 Apr 2015 18:54:23 +0000 (18:54 +0000)]
[AArch64] Add a comment to make it explicit why we increased the complexity.
Follow-up of r233653.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233936 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86, AVX] adjust tablegen patterns to generate better code for scalar insertion...
Sanjay Patel [Thu, 2 Apr 2015 17:56:17 +0000 (17:56 +0000)]
[X86, AVX] adjust tablegen patterns to generate better code for scalar insertion into zero vector (PR23073)

For code like this:

define <8 x i32> @load_v8i32() {
  ret <8 x i32> <i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
}

We produce this AVX code:

_load_v8i32:                            ## @load_v8i32
  movl $7, %eax
  vmovd %eax, %xmm0
  vxorps %ymm1, %ymm1, %ymm1
  vblendps $1, %ymm0, %ymm1, %ymm0 ## ymm0 = ymm0[0],ymm1[1,2,3,4,5,6,7]
  retq

There are at least 2 bugs in play here:

    We're generating a blend when a move scalar does the same job using 2 less instruction bytes (see FIXMEs).
    We're not matching an existing pattern that would eliminate the xor and blend entirely. The zero bytes are free with vmovd.

The 2nd fix involves an adjustment of "AddedComplexity" [1] and mostly masks the 1st problem.

[1] AddedComplexity has close to no documentation in the source.
The best we have is this comment: "roughly corresponds to the number of nodes that are covered".
It appears that x86 has bastardized this definition by inflating its values for some other
undocumented reason. For example, we have a pattern with "AddedComplexity = 400" (!).

I searched my way to this page:
https://groups.google.com/forum/#!topic/llvm-dev/5UX-Og9M0xQ

Differential Revision: http://reviews.llvm.org/D8794

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233931 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopAccesses] Handle case when no memchecks are needed after partitioning
Adam Nemet [Thu, 2 Apr 2015 17:51:57 +0000 (17:51 +0000)]
[LoopAccesses] Handle case when no memchecks are needed after partitioning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233930 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd an LLVM_PTR_SIZE macro to make LLVM_ALIGNAS more useful
Reid Kleckner [Thu, 2 Apr 2015 17:43:35 +0000 (17:43 +0000)]
Add an LLVM_PTR_SIZE macro to make LLVM_ALIGNAS more useful

MSVC 2013 requires the argument to __declspec(align()) to be an integer
constant expression that doesn't involve any identifiers like sizeof.

For GCC and Clang, LLVM_PTR_SIZE is equivalent to __SIZEOF_POINTER__,
which dates back to GCC 4.6 and Clang 2010. If that's not available, we
get sizeof(void*), which works with alignas() and
__attribute__((aligned())).

For MSVC, LLVM_PTR_SIZE is 4 or 8 depending on _WIN64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233929 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix typo and reword in LangRef
Eli Bendersky [Thu, 2 Apr 2015 15:20:04 +0000 (15:20 +0000)]
Fix typo and reword in LangRef

Patch by Douglas Katzman

Differential Revision: http://reviews.llvm.org/D8785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233920 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[alignof] Put back the hack for old versions of GCC.
Benjamin Kramer [Thu, 2 Apr 2015 13:31:50 +0000 (13:31 +0000)]
[alignof] Put back the hack for old versions of GCC.

This works around a bug (PR56859) that is fixed in all versions of GCC I tested
with but was present in 4.8.0. Using 4.8.0 is of course a terrible idea, but looks
like we can't drop it just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233916 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[support] Add a macro wrapper for alignas and simplify some code.
Benjamin Kramer [Thu, 2 Apr 2015 11:32:48 +0000 (11:32 +0000)]
[support] Add a macro wrapper for alignas and simplify some code.

We wrap __attribute((aligned)) for GCC 4.7 and __declspec(align) for
MSVC. The latter behaves weird in some contexts so this should be used
carefully.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233910 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.
Vasileios Kalintiris [Thu, 2 Apr 2015 11:09:40 +0000 (11:09 +0000)]
[mips] Implement eliminateCallFramePseudoInstr() in MipsFrameLowering. NFC.

Summary:
Avoid duplicate code in Mips16FrameLowering and MipsSEFrameLowering by
providing an implementation of the eliminateCallFramePseudoInstr()
function from their base class.

Depends on D8640.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8641

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233909 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
Elena Demikhovsky [Thu, 2 Apr 2015 10:51:40 +0000 (10:51 +0000)]
AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
by Asaf Badouh (asaf.badouh@intel.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233906 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.
Vasileios Kalintiris [Thu, 2 Apr 2015 10:42:44 +0000 (10:42 +0000)]
[mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.

Summary:
adjustStackPtr() is implemented from both MipsSEInstrInfo and
Mips16InstrInfo. It makes sense to expose this function from
MipsInstrInfo and avoid explicit casting in some cases.

Depends on D8638.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233905 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[mips] Make sure that we don't adjust the stack pointer by zero amount.
Vasileios Kalintiris [Thu, 2 Apr 2015 10:14:54 +0000 (10:14 +0000)]
[mips] Make sure that we don't adjust the stack pointer by zero amount.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8638

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233904 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Rename v8.1a from "extension" to "architecture": follow-up
Vladimir Sukharev [Thu, 2 Apr 2015 09:32:14 +0000 (09:32 +0000)]
[ARM] Rename v8.1a from "extension" to "architecture": follow-up

Corrected forgotten change to remove excess "generic-armv8.1-a" cpu

Subscribers: llvm-commits

Completion of http://reviews.llvm.org/rL233811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233903 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRevert r233595, "MC: For variable symbols, maintain MCSymbol::Section as a cache."
Peter Collingbourne [Thu, 2 Apr 2015 07:02:51 +0000 (07:02 +0000)]
Revert r233595, "MC: For variable symbols, maintain MCSymbol::Section as a cache."

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233898 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Fix local-linkage handling in the CompileOnDemand layer.
Lang Hames [Thu, 2 Apr 2015 05:28:10 +0000 (05:28 +0000)]
[Orc] Fix local-linkage handling in the CompileOnDemand layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233895 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[gcroot] Remove unused items from an enum
Philip Reames [Thu, 2 Apr 2015 05:02:16 +0000 (05:02 +0000)]
[gcroot] Remove unused items from an enum

These two were never implemented for gcroot, so there's no point in keeping them around now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233892 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTeach gcroot how to handle dynamically realigned frames
Philip Reames [Thu, 2 Apr 2015 05:00:40 +0000 (05:00 +0000)]
Teach gcroot how to handle dynamically realigned frames

I'm playing with supporting custom stack map formats with statepoints.  While
doing so, I noticed that the existing implementation didn't indicate inherently
unsized frames.  This change essentially just ports the functionality that already
exists for the default StackMaps section to custom stackmaps.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233891 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ADT] Increment epoch from DenseMap::swap.
Sanjoy Das [Thu, 2 Apr 2015 04:58:12 +0000 (04:58 +0000)]
[ADT] Increment epoch from DenseMap::swap.

Swapping DenseMap A with DenseMap B invalidates iterators pointing into
both A and B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233890 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ADT] Remove dead code.
Sanjoy Das [Thu, 2 Apr 2015 04:58:08 +0000 (04:58 +0000)]
[ADT] Remove dead code.

Nothing is using DenseMapBase::swap.  Besides it does not compile in its
current form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233889 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[LoopAccesses] Remove unused global variables in tests
Adam Nemet [Thu, 2 Apr 2015 04:42:51 +0000 (04:42 +0000)]
[LoopAccesses] Remove unused global variables in tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233887 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Add support classes for inspecting and running C++ static ctor/dtors, and
Lang Hames [Thu, 2 Apr 2015 04:34:45 +0000 (04:34 +0000)]
[Orc] Add support classes for inspecting and running C++ static ctor/dtors, and
use these to add support for C++ static ctors/dtors to the Orc-lazy JIT in LLI.

Replace the trivial_retval_1 regression test - the new 'hello' test is covering
strictly more code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233885 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoDon't print an error message when looking up the scheduling model if user specified...
Craig Topper [Thu, 2 Apr 2015 04:27:50 +0000 (04:27 +0000)]
Don't print an error message when looking up the scheduling model if user specified -mcpu=help.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233884 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix a bug indicated by -fsanitize=shift-exponent.
Alexey Samsonov [Thu, 2 Apr 2015 01:30:10 +0000 (01:30 +0000)]
Fix a bug indicated by -fsanitize=shift-exponent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233881 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoMark this inline properly
Daniel Berlin [Thu, 2 Apr 2015 00:03:15 +0000 (00:03 +0000)]
Mark this inline properly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233870 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoReturn iterator from Instruction::eraseFromParent.
Daniel Berlin [Thu, 2 Apr 2015 00:03:07 +0000 (00:03 +0000)]
Return iterator from Instruction::eraseFromParent.

Summary:
This is necessary in order to make removal while using reverse iterators work.

(See http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-March/084122.html)

Updates to other eraseFromParent's to come in later patches.

Reviewers: chandlerc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233869 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTableGen: Generate more const goodness
Matthias Braun [Wed, 1 Apr 2015 22:09:55 +0000 (22:09 +0000)]
TableGen: Generate more const goodness

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233857 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix sanitizer-x86_64-linux-fast failure that was not deleting the bindtable.
Kevin Enderby [Wed, 1 Apr 2015 21:50:45 +0000 (21:50 +0000)]
Fix sanitizer-x86_64-linux-fast failure that was not deleting the bindtable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233856 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[fuzzer] document the -tokens flag. Also change the diagnostic output
Kostya Serebryany [Wed, 1 Apr 2015 21:33:20 +0000 (21:33 +0000)]
[fuzzer] document the -tokens flag. Also change the diagnostic output

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233842 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove declarations for nonexistent methods
Matthias Braun [Wed, 1 Apr 2015 21:16:02 +0000 (21:16 +0000)]
Remove declarations for nonexistent methods

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233841 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd the option -objc-meta-data to llvm-objdump used with -macho to
Kevin Enderby [Wed, 1 Apr 2015 20:57:01 +0000 (20:57 +0000)]
Add the option -objc-meta-data to llvm-objdump used with -macho to
print the Objective-C runtime meta data for Mach-O files.

There are three types of Objective-C runtime meta data, Objc2 64-bit,
Objc2 32-bit and Objc1 32-bit.  This prints the first of these types. The
changes to print the others will follow next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233840 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[X86] Don't accidentally select shll $1, %eax when shrinking an immediate.
Benjamin Kramer [Wed, 1 Apr 2015 19:01:09 +0000 (19:01 +0000)]
[X86] Don't accidentally select shll $1, %eax when shrinking an immediate.

addl has higher throughput and this was needlessly picking a suboptimal
encoding causing PR23098.

I wish there was a way of doing this without further duplicating tbl-
generated patterns, but so far I haven't found one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233832 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SCEV] Look at backedge dominating conditions (re-land r233447).
Sanjoy Das [Wed, 1 Apr 2015 18:24:06 +0000 (18:24 +0000)]
[SCEV] Look at backedge dominating conditions (re-land r233447).

Summary:
This change teaches ScalarEvolution::isLoopBackedgeGuardedByCond to look
at edges within the loop body that dominate the latch.  We don't do an
exhaustive search for all possible edges, but only a quick walk up the
dom tree.

This re-lands r233447.  r233447 was reverted because it caused massive
compile-time regressions.  This change has a fix for the same issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233829 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRemove 4,096 loop scale limitation.
Diego Novillo [Wed, 1 Apr 2015 17:42:27 +0000 (17:42 +0000)]
Remove 4,096 loop scale limitation.

Summary:
This is part 1 of fixes to address the problems described in
https://llvm.org/bugs/show_bug.cgi?id=22719.

The restriction to limit loop scales to 4,096 does not really prevent
overflows anymore, as the underlying algorithm has changed and does
not seem to suffer from this problem.

Additionally, artificially restricting loop scales to such a low number
skews frequency information, making loops of equal hotness appear to
have very different hotness properties.

The only loops that are artificially restricted to a scale of 4096 are
infinite loops (those loops with an exit mass of 0). This prevents
infinite loops from skewing the frequencies of other regions in the CFG.

At the end of propagation, frequencies are scaled to values that take no
more than 64 bits to represent. When the range of frequencies to be
represented fits within 61 bits, it pushes up the scaling factor to a
minimum of 8 to better distinguish small frequency values. Otherwise,
small frequency values are all saturated down at 1.

Tested on x86_64.

Reviewers: dexonsmith

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8718

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233826 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix WinEHPrepare bug with multiple catch handlers
Andrew Kaylor [Wed, 1 Apr 2015 17:21:25 +0000 (17:21 +0000)]
Fix WinEHPrepare bug with multiple catch handlers

Differential Revision: http://reviews.llvm.org/D8682

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233824 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ARM] Rename v8.1a from "extension" to "architecture"
Vladimir Sukharev [Wed, 1 Apr 2015 14:54:56 +0000 (14:54 +0000)]
[ARM] Rename v8.1a from "extension" to "architecture"

v8.1a is renamed to architecture, following current entity naming approach.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233811 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Rename v8.1a from "extension" to "architecture"
Vladimir Sukharev [Wed, 1 Apr 2015 14:49:29 +0000 (14:49 +0000)]
[AArch64] Rename v8.1a from "extension" to "architecture"

v8.1a is renamed to architecture, accordingly to approaches in ARM backend.

Excess generic cpu is removed. Intended use: "generic" cpu with "v8.1a" subtarget feature

Reviewers: jmolloy

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233810 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agogit-clang-format r233603.
Rafael Espindola [Wed, 1 Apr 2015 14:44:59 +0000 (14:44 +0000)]
git-clang-format r233603.

Thanks to Meador Inge for noticing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233808 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SystemZ] Support transactional execution on zEC12
Ulrich Weigand [Wed, 1 Apr 2015 12:51:43 +0000 (12:51 +0000)]
[SystemZ] Support transactional execution on zEC12

The zEC12 provides the transactional-execution facility.  This is exposed
to users via a set of builtin routines on other compilers.  This patch
adds LLVM support to enable those builtins.  In partciular, the patch:

- adds the transactional-execution and processor-assist facilities
- adds MC support for all instructions provided by those facilities
- adds LLVM intrinsics for those instructions and hooks them up for CodeGen
- adds CodeGen support to optimize CC return value checking

Since this is first use of target-specific intrinsics on the platform,
the patch creates the include/llvm/IR/IntrinsicsSystemZ.td file and
hooks it up in Intrinsics.td.  I've also changed Triple::getArchTypePrefix
to return "s390" instead of "systemz", since the naming convention for
GCC intrinsics uses "s390" on the platform, and it neemed more straight-
forward to use the same convention for LLVM IR intrinsics.

An associated clang patch makes the intrinsics (and command line switches)
available at the source-language level.

For reference, the transactional-execution instructions are documented
in the z/Architecture Principles of Operation for the zEC12:
http://publibfp.boulder.ibm.com/cgi-bin/bookmgr/download/DZ9ZR009.pdf
The associated builtins are documented in the GCC manual:
http://gcc.gnu.org/onlinedocs/gcc/S_002f390-System-z-Built-in-Functions.html

Index: llvm-head/lib/Target/SystemZ/SystemZOperators.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZOperators.td
+++ llvm-head/lib/Target/SystemZ/SystemZOperators.td
@@ -79,6 +79,9 @@ def SDT_ZI32Intrinsic       : SDTypeProf
 def SDT_ZPrefetch           : SDTypeProfile<0, 2,
                                             [SDTCisVT<0, i32>,
                                              SDTCisPtrTy<1>]>;
+def SDT_ZTBegin             : SDTypeProfile<0, 2,
+                                            [SDTCisPtrTy<0>,
+                                             SDTCisVT<1, i32>]>;

 //===----------------------------------------------------------------------===//
 // Node definitions
@@ -180,6 +183,15 @@ def z_prefetch          : SDNode<"System
                                  [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
                                   SDNPMemOperand]>;

+def z_tbegin            : SDNode<"SystemZISD::TBEGIN", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tbegin_nofloat    : SDNode<"SystemZISD::TBEGIN_NOFLOAT", SDT_ZTBegin,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPMayStore,
+                                  SDNPSideEffect]>;
+def z_tend              : SDNode<"SystemZISD::TEND", SDTNone,
+                                 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>;
+
 //===----------------------------------------------------------------------===//
 // Pattern fragments
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrFormats.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -473,6 +473,17 @@ class InstSS<bits<8> op, dag outs, dag i
   let Inst{15-0}  = BD2;
 }

+class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : InstSystemZ<4, outs, ins, asmstr, pattern> {
+  field bits<32> Inst;
+  field bits<32> SoftFail = 0;
+
+  bits<16> BD2;
+
+  let Inst{31-16} = op;
+  let Inst{15-0}  = BD2;
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
Index: llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZInstrInfo.td
+++ llvm-head/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -1362,6 +1362,60 @@ let Defs = [CC] in {
 }

 //===----------------------------------------------------------------------===//
+// Transactional execution
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureTransactionalExecution] in {
+  // Transaction Begin
+  let hasSideEffects = 1, mayStore = 1,
+      usesCustomInserter = 1, Defs = [CC] in {
+    def TBEGIN : InstSIL<0xE560,
+                         (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                         "tbegin\t$BD1, $I2",
+                         [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
+    def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                                [(z_tbegin_nofloat bdaddr12only:$BD1,
+                                                   imm32zx16:$I2)]>;
+    def TBEGINC : InstSIL<0xE561,
+                          (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
+                          "tbeginc\t$BD1, $I2",
+                          [(int_s390_tbeginc bdaddr12only:$BD1,
+                                             imm32zx16:$I2)]>;
+  }
+
+  // Transaction End
+  let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
+    def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
+
+  // Transaction Abort
+  let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
+    def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
+                       "tabort\t$BD2",
+                       [(int_s390_tabort bdaddr12only:$BD2)]>;
+
+  // Nontransactional Store
+  let hasSideEffects = 1 in
+    def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
+
+  // Extract Transaction Nesting Depth
+  let hasSideEffects = 1 in
+    def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
+}
+
+//===----------------------------------------------------------------------===//
+// Processor assist
+//===----------------------------------------------------------------------===//
+
+let Predicates = [FeatureProcessorAssist] in {
+  let hasSideEffects = 1, R4 = 0 in
+    def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
+                      "ppa\t$R1, $R2, $R3", []>;
+  def : Pat<(int_s390_ppa_txassist GR32:$src),
+            (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
+                 0, 1)>;
+}
+
+//===----------------------------------------------------------------------===//
 // Miscellaneous Instructions.
 //===----------------------------------------------------------------------===//

Index: llvm-head/lib/Target/SystemZ/SystemZProcessors.td
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZProcessors.td
+++ llvm-head/lib/Target/SystemZ/SystemZProcessors.td
@@ -60,6 +60,16 @@ def FeatureMiscellaneousExtensions : Sys
   "Assume that the miscellaneous-extensions facility is installed"
 >;

+def FeatureTransactionalExecution : SystemZFeature<
+  "transactional-execution", "TransactionalExecution",
+  "Assume that the transactional-execution facility is installed"
+>;
+
+def FeatureProcessorAssist : SystemZFeature<
+  "processor-assist", "ProcessorAssist",
+  "Assume that the processor-assist facility is installed"
+>;
+
 def : Processor<"generic", NoItineraries, []>;
 def : Processor<"z10", NoItineraries, []>;
 def : Processor<"z196", NoItineraries,
@@ -70,4 +80,5 @@ def : Processor<"zEC12", NoItineraries,
                 [FeatureDistinctOps, FeatureLoadStoreOnCond, FeatureHighWord,
                  FeatureFPExtension, FeaturePopulationCount,
                  FeatureFastSerialization, FeatureInterlockedAccess1,
-                 FeatureMiscellaneousExtensions]>;
+                 FeatureMiscellaneousExtensions,
+                 FeatureTransactionalExecution, FeatureProcessorAssist]>;
Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.cpp
@@ -40,6 +40,7 @@ SystemZSubtarget::SystemZSubtarget(const
       HasLoadStoreOnCond(false), HasHighWord(false), HasFPExtension(false),
       HasPopulationCount(false), HasFastSerialization(false),
       HasInterlockedAccess1(false), HasMiscellaneousExtensions(false),
+      HasTransactionalExecution(false), HasProcessorAssist(false),
       TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
       TLInfo(TM, *this), TSInfo(*TM.getDataLayout()), FrameLowering() {}

Index: llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZSubtarget.h
+++ llvm-head/lib/Target/SystemZ/SystemZSubtarget.h
@@ -42,6 +42,8 @@ protected:
   bool HasFastSerialization;
   bool HasInterlockedAccess1;
   bool HasMiscellaneousExtensions;
+  bool HasTransactionalExecution;
+  bool HasProcessorAssist;

 private:
   Triple TargetTriple;
@@ -102,6 +104,12 @@ public:
     return HasMiscellaneousExtensions;
   }

+  // Return true if the target has the transactional-execution facility.
+  bool hasTransactionalExecution() const { return HasTransactionalExecution; }
+
+  // Return true if the target has the processor-assist facility.
+  bool hasProcessorAssist() const { return HasProcessorAssist; }
+
   // Return true if GV can be accessed using LARL for reloc model RM
   // and code model CM.
   bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
Index: llvm-head/lib/Support/Triple.cpp
===================================================================
--- llvm-head.orig/lib/Support/Triple.cpp
+++ llvm-head/lib/Support/Triple.cpp
@@ -92,7 +92,7 @@ const char *Triple::getArchTypePrefix(Ar
   case sparcv9:
   case sparc:       return "sparc";

-  case systemz:     return "systemz";
+  case systemz:     return "s390";

   case x86:
   case x86_64:      return "x86";
Index: llvm-head/include/llvm/IR/Intrinsics.td
===================================================================
--- llvm-head.orig/include/llvm/IR/Intrinsics.td
+++ llvm-head/include/llvm/IR/Intrinsics.td
@@ -634,3 +634,4 @@ include "llvm/IR/IntrinsicsNVVM.td"
 include "llvm/IR/IntrinsicsMips.td"
 include "llvm/IR/IntrinsicsR600.td"
 include "llvm/IR/IntrinsicsBPF.td"
+include "llvm/IR/IntrinsicsSystemZ.td"
Index: llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
===================================================================
--- /dev/null
+++ llvm-head/include/llvm/IR/IntrinsicsSystemZ.td
@@ -0,0 +1,46 @@
+//===- IntrinsicsSystemZ.td - Defines SystemZ intrinsics ---*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the SystemZ-specific intrinsics.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//
+// Transactional-execution intrinsics
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "s390" in {
+  def int_s390_tbegin : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
+                                  [IntrNoDuplicate]>;
+
+  def int_s390_tbegin_nofloat : Intrinsic<[llvm_i32_ty],
+                                          [llvm_ptr_ty, llvm_i32_ty],
+                                          [IntrNoDuplicate]>;
+
+  def int_s390_tbeginc : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+                                   [IntrNoDuplicate]>;
+
+  def int_s390_tabort : Intrinsic<[], [llvm_i64_ty],
+                                  [IntrNoReturn, Throws]>;
+
+  def int_s390_tend : GCCBuiltin<"__builtin_tend">,
+                      Intrinsic<[llvm_i32_ty], []>;
+
+  def int_s390_etnd : GCCBuiltin<"__builtin_tx_nesting_depth">,
+                      Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+
+  def int_s390_ntstg : Intrinsic<[], [llvm_i64_ty, llvm_ptr64_ty],
+                                 [IntrReadWriteArgMem]>;
+
+  def int_s390_ppa_txassist : GCCBuiltin<"__builtin_tx_assist">,
+                              Intrinsic<[], [llvm_i32_ty]>;
+}
+
Index: llvm-head/lib/Target/SystemZ/SystemZ.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZ.h
+++ llvm-head/lib/Target/SystemZ/SystemZ.h
@@ -68,6 +68,18 @@ const unsigned CCMASK_TM_MSB_0       = C
 const unsigned CCMASK_TM_MSB_1       = CCMASK_2 | CCMASK_3;
 const unsigned CCMASK_TM             = CCMASK_ANY;

+// Condition-code mask assignments for TRANSACTION_BEGIN.
+const unsigned CCMASK_TBEGIN_STARTED       = CCMASK_0;
+const unsigned CCMASK_TBEGIN_INDETERMINATE = CCMASK_1;
+const unsigned CCMASK_TBEGIN_TRANSIENT     = CCMASK_2;
+const unsigned CCMASK_TBEGIN_PERSISTENT    = CCMASK_3;
+const unsigned CCMASK_TBEGIN               = CCMASK_ANY;
+
+// Condition-code mask assignments for TRANSACTION_END.
+const unsigned CCMASK_TEND_TX   = CCMASK_0;
+const unsigned CCMASK_TEND_NOTX = CCMASK_2;
+const unsigned CCMASK_TEND      = CCMASK_TEND_TX | CCMASK_TEND_NOTX;
+
 // The position of the low CC bit in an IPM result.
 const unsigned IPM_CC = 28;

Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.h
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.h
@@ -146,6 +146,15 @@ enum {
   // Perform a serialization operation.  (BCR 15,0 or BCR 14,0.)
   SERIALIZE,

+  // Transaction begin.  The first operand is the chain, the second
+  // the TDB pointer, and the third the immediate control field.
+  // Returns chain and glue.
+  TBEGIN,
+  TBEGIN_NOFLOAT,
+
+  // Transaction end.  Just the chain operand.  Returns chain and glue.
+  TEND,
+
   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
   // ATOMIC_LOAD_<op>.
   //
@@ -318,6 +327,7 @@ private:
   SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;

   // If the last instruction before MBBI in MBB was some form of COMPARE,
   // try to replace it with a COMPARE AND BRANCH just before MBBI.
@@ -355,6 +365,10 @@ private:
   MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
                                        MachineBasicBlock *BB,
                                        unsigned Opcode) const;
+  MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
+                                          MachineBasicBlock *MBB,
+                                          unsigned Opcode,
+                                          bool NoFloat) const;
 };
 } // end namespace llvm

Index: llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm-head.orig/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm-head/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -20,6 +20,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
+#include "llvm/IR/Intrinsics.h"
 #include <cctype>

 using namespace llvm;
@@ -304,6 +305,9 @@ SystemZTargetLowering::SystemZTargetLowe
   // Codes for which we want to perform some z-specific combinations.
   setTargetDAGCombine(ISD::SIGN_EXTEND);

+  // Handle intrinsics.
+  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
+
   // We want to use MVC in preference to even a single load/store pair.
   MaxStoresPerMemcpy = 0;
   MaxStoresPerMemcpyOptSize = 0;
@@ -1031,6 +1035,53 @@ prepareVolatileOrAtomicLoad(SDValue Chai
   return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
 }

+// Return true if Op is an intrinsic node with chain that returns the CC value
+// as its only (other) argument.  Provide the associated SystemZISD opcode and
+// the mask of valid CC values if so.
+static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
+                                      unsigned &CCValid) {
+  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  switch (Id) {
+  case Intrinsic::s390_tbegin:
+    Opcode = SystemZISD::TBEGIN;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tbegin_nofloat:
+    Opcode = SystemZISD::TBEGIN_NOFLOAT;
+    CCValid = SystemZ::CCMASK_TBEGIN;
+    return true;
+
+  case Intrinsic::s390_tend:
+    Opcode = SystemZISD::TEND;
+    CCValid = SystemZ::CCMASK_TEND;
+    return true;
+
+  default:
+    return false;
+  }
+}
+
+// Emit an intrinsic with chain with a glued value instead of its CC result.
+static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
+                                             unsigned Opcode) {
+  // Copy all operands except the intrinsic ID.
+  unsigned NumOps = Op.getNumOperands();
+  SmallVector<SDValue, 6> Ops;
+  Ops.reserve(NumOps - 1);
+  Ops.push_back(Op.getOperand(0));
+  for (unsigned I = 2; I < NumOps; ++I)
+    Ops.push_back(Op.getOperand(I));
+
+  assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+  SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
+  SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
+  SDValue OldChain = SDValue(Op.getNode(), 1);
+  SDValue NewChain = SDValue(Intr.getNode(), 0);
+  DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
+  return Intr;
+}
+
 // CC is a comparison that will be implemented using an integer or
 // floating-point comparison.  Return the condition code mask for
 // a branch on true.  In the integer case, CCMASK_CMP_UO is set for
@@ -1588,9 +1639,53 @@ static void adjustForTestUnderMask(Selec
   C.CCMask = NewCCMask;
 }

+// Return a Comparison that tests the condition-code result of intrinsic
+// node Call against constant integer CC using comparison code Cond.
+// Opcode is the opcode of the SystemZISD operation for the intrinsic
+// and CCValid is the set of possible condition-code results.
+static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
+                                  SDValue Call, unsigned CCValid, uint64_t CC,
+                                  ISD::CondCode Cond) {
+  Comparison C(Call, SDValue());
+  C.Opcode = Opcode;
+  C.CCValid = CCValid;
+  if (Cond == ISD::SETEQ)
+    // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
+    C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
+  else if (Cond == ISD::SETNE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
+  else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
+    // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (4 - CC) : -1;
+  else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (4 - CC)) : 0;
+  else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
+    // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
+    // always true for CC>3.
+    C.CCMask = CC < 4 ? -1 << (3 - CC) : -1;
+  else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
+    // ...and the inverse of that.
+    C.CCMask = CC < 4 ? ~(-1 << (3 - CC)) : 0;
+  else
+    llvm_unreachable("Unexpected integer comparison type");
+  C.CCMask &= CCValid;
+  return C;
+}
+
 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
                          ISD::CondCode Cond) {
+  if (CmpOp1.getOpcode() == ISD::Constant) {
+    uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
+    unsigned Opcode, CCValid;
+    if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
+        CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
+        isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
+      return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
+  }
   Comparison C(CmpOp0, CmpOp1);
   C.CCMask = CCMaskForCondCode(Cond);
   if (C.Op0.getValueType().isFloatingPoint()) {
@@ -1632,6 +1727,17 @@ static Comparison getCmp(SelectionDAG &D

 // Emit the comparison instruction described by C.
 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
+  if (!C.Op1.getNode()) {
+    SDValue Op;
+    switch (C.Op0.getOpcode()) {
+    case ISD::INTRINSIC_W_CHAIN:
+      Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
+      break;
+    default:
+      llvm_unreachable("Invalid comparison operands");
+    }
+    return SDValue(Op.getNode(), Op->getNumValues() - 1);
+  }
   if (C.Opcode == SystemZISD::ICMP)
     return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
                        DAG.getConstant(C.ICmpType, MVT::i32));
@@ -1713,7 +1819,6 @@ SDValue SystemZTargetLowering::lowerSETC
 }

 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
-  SDValue Chain    = Op.getOperand(0);
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
   SDValue CmpOp0   = Op.getOperand(2);
   SDValue CmpOp1   = Op.getOperand(3);
@@ -1723,7 +1828,7 @@ SDValue SystemZTargetLowering::lowerBR_C
   Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));
   SDValue Glue = emitCmp(DAG, DL, C);
   return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
-                     Chain, DAG.getConstant(C.CCValid, MVT::i32),
+                     Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),
                      DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);
 }

@@ -2561,6 +2666,30 @@ SDValue SystemZTargetLowering::lowerPREF
                                  Node->getMemoryVT(), Node->getMemOperand());
 }

+// Return an i32 that contains the value of CC immediately after After,
+// whose final operand must be MVT::Glue.
+static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
+  SDValue Glue = SDValue(After, After->getNumValues() - 1);
+  SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);
+  return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,
+                     DAG.getConstant(SystemZ::IPM_CC, MVT::i32));
+}
+
+SDValue
+SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
+                                              SelectionDAG &DAG) const {
+  unsigned Opcode, CCValid;
+  if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
+    assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
+    SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
+    SDValue CC = getCCResult(DAG, Glued.getNode());
+    DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
+    return SDValue();
+  }
+
+  return SDValue();
+}
+
 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
                                               SelectionDAG &DAG) const {
   switch (Op.getOpcode()) {
@@ -2634,6 +2763,8 @@ SDValue SystemZTargetLowering::LowerOper
     return lowerSTACKRESTORE(Op, DAG);
   case ISD::PREFETCH:
     return lowerPREFETCH(Op, DAG);
+  case ISD::INTRINSIC_W_CHAIN:
+    return lowerINTRINSIC_W_CHAIN(Op, DAG);
   default:
     llvm_unreachable("Unexpected node to lower");
   }
@@ -2674,6 +2805,9 @@ const char *SystemZTargetLowering::getTa
     OPCODE(SEARCH_STRING);
     OPCODE(IPM);
     OPCODE(SERIALIZE);
+    OPCODE(TBEGIN);
+    OPCODE(TBEGIN_NOFLOAT);
+    OPCODE(TEND);
     OPCODE(ATOMIC_SWAPW);
     OPCODE(ATOMIC_LOADW_ADD);
     OPCODE(ATOMIC_LOADW_SUB);
@@ -3501,6 +3635,50 @@ SystemZTargetLowering::emitStringWrapper
   return DoneMBB;
 }

+// Update TBEGIN instruction with final opcode and register clobbers.
+MachineBasicBlock *
+SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
+                                            MachineBasicBlock *MBB,
+                                            unsigned Opcode,
+                                            bool NoFloat) const {
+  MachineFunction &MF = *MBB->getParent();
+  const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
+  const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
+
+  // Update opcode.
+  MI->setDesc(TII->get(Opcode));
+
+  // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
+  // Make sure to add the corresponding GRSM bits if they are missing.
+  uint64_t Control = MI->getOperand(2).getImm();
+  static const unsigned GPRControlBit[16] = {
+    0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
+    0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
+  };
+  Control |= GPRControlBit[15];
+  if (TFI->hasFP(MF))
+    Control |= GPRControlBit[11];
+  MI->getOperand(2).setImm(Control);
+
+  // Add GPR clobbers.
+  for (int I = 0; I < 16; I++) {
+    if ((Control & GPRControlBit[I]) == 0) {
+      unsigned Reg = SystemZMC::GR64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  // Add FPR clobbers.
+  if (!NoFloat && (Control & 4) != 0) {
+    for (int I = 0; I < 16; I++) {
+      unsigned Reg = SystemZMC::FP64Regs[I];
+      MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
+    }
+  }
+
+  return MBB;
+}
+
 MachineBasicBlock *SystemZTargetLowering::
 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
   switch (MI->getOpcode()) {
@@ -3742,6 +3920,12 @@ EmitInstrWithCustomInserter(MachineInstr
     return emitStringWrapper(MI, MBB, SystemZ::MVST);
   case SystemZ::SRSTLoop:
     return emitStringWrapper(MI, MBB, SystemZ::SRST);
+  case SystemZ::TBEGIN:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
+  case SystemZ::TBEGIN_nofloat:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
+  case SystemZ::TBEGINC:
+    return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
   default:
     llvm_unreachable("Unexpected instr type to insert");
   }
Index: llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
===================================================================
--- /dev/null
+++ llvm-head/test/CodeGen/SystemZ/htm-intrinsics.ll
@@ -0,0 +1,352 @@
+; Test transactional-execution intrinsics.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
+
+declare i32 @llvm.s390.tbegin(i8 *, i32)
+declare i32 @llvm.s390.tbegin.nofloat(i8 *, i32)
+declare void @llvm.s390.tbeginc(i8 *, i32)
+declare i32 @llvm.s390.tend()
+declare void @llvm.s390.tabort(i64)
+declare void @llvm.s390.ntstg(i64, i64 *)
+declare i32 @llvm.s390.etnd()
+declare void @llvm.s390.ppa.txassist(i32)
+
+; TBEGIN.
+define void @test_tbegin() {
+; CHECK-LABEL: test_tbegin:
+; CHECK-NOT: stmg
+; CHECK: std %f8,
+; CHECK: std %f9,
+; CHECK: std %f10,
+; CHECK: std %f11,
+; CHECK: std %f12,
+; CHECK: std %f13,
+; CHECK: std %f14,
+; CHECK: std %f15,
+; CHECK: tbegin 0, 65292
+; CHECK: ld %f8,
+; CHECK: ld %f9,
+; CHECK: ld %f10,
+; CHECK: ld %f11,
+; CHECK: ld %f12,
+; CHECK: ld %f13,
+; CHECK: ld %f14,
+; CHECK: ld %f15,
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat).
+define void @test_tbegin_nofloat1() {
+; CHECK-LABEL: test_tbegin_nofloat1:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with integer CC return value.
+define i32 @test_tbegin_nofloat2() {
+; CHECK-LABEL: test_tbegin_nofloat2:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with implicit CC check.
+define void @test_tbegin_nofloat3(i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat3:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: jnh  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TBEGIN (nofloat) with dual CC use.
+define i32 @test_tbegin_nofloat4(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat4:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65292
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65292)
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TBEGIN (nofloat) with register.
+define void @test_tbegin_nofloat5(i8 *%ptr) {
+; CHECK-LABEL: test_tbegin_nofloat5:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0(%r2), 65292
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *%ptr, i32 65292)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0x0f00.
+define void @test_tbegin_nofloat6() {
+; CHECK-LABEL: test_tbegin_nofloat6:
+; CHECK: stmg %r6, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 3840
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 3840)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xf100.
+define void @test_tbegin_nofloat7() {
+; CHECK-LABEL: test_tbegin_nofloat7:
+; CHECK: stmg %r8, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 61696
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 61696)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfe00 -- stack pointer added automatically.
+define void @test_tbegin_nofloat8() {
+; CHECK-LABEL: test_tbegin_nofloat8:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 65024)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- no frame pointer needed.
+define void @test_tbegin_nofloat9() {
+; CHECK-LABEL: test_tbegin_nofloat9:
+; CHECK: stmg %r10, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 64256
+; CHECK: br %r14
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGIN (nofloat) with GRSM 0xfb00 -- frame pointer added automatically.
+define void @test_tbegin_nofloat10(i64 %n) {
+; CHECK-LABEL: test_tbegin_nofloat10:
+; CHECK: stmg %r11, %r15,
+; CHECK-NOT: std
+; CHECK: tbegin 0, 65280
+; CHECK: br %r14
+  %buf = alloca i8, i64 %n
+  call i32 @llvm.s390.tbegin.nofloat(i8 *null, i32 64256)
+  ret void
+}
+
+; TBEGINC.
+define void @test_tbeginc() {
+; CHECK-LABEL: test_tbeginc:
+; CHECK-NOT: stmg
+; CHECK-NOT: std
+; CHECK: tbeginc 0, 65288
+; CHECK: br %r14
+  call void @llvm.s390.tbeginc(i8 *null, i32 65288)
+  ret void
+}
+
+; TEND with integer CC return value.
+define i32 @test_tend1() {
+; CHECK-LABEL: test_tend1:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  ret i32 %res
+}
+
+; TEND with implicit CC check.
+define void @test_tend3(i32 *%ptr) {
+; CHECK-LABEL: test_tend3:
+; CHECK: tend
+; CHECK: je  {{\.L*}}
+; CHECK: mvhi 0(%r2), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret void
+}
+
+; TEND with dual CC use.
+define i32 @test_tend2(i32 %pad, i32 *%ptr) {
+; CHECK-LABEL: test_tend2:
+; CHECK: tend
+; CHECK: ipm %r2
+; CHECK: srl %r2, 28
+; CHECK: cijlh %r2, 2,  {{\.L*}}
+; CHECK: mvhi 0(%r3), 0
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.tend()
+  %cmp = icmp eq i32 %res, 2
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:                                          ; preds = %entry
+  store i32 0, i32* %ptr, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %if.then, %entry
+  ret i32 %res
+}
+
+; TABORT with register only.
+define void @test_tabort1(i64 %val) {
+; CHECK-LABEL: test_tabort1:
+; CHECK: tabort 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 %val)
+  ret void
+}
+
+; TABORT with immediate only.
+define void @test_tabort2(i64 %val) {
+; CHECK-LABEL: test_tabort2:
+; CHECK: tabort 1234
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 1234)
+  ret void
+}
+
+; TABORT with register + immediate.
+define void @test_tabort3(i64 %val) {
+; CHECK-LABEL: test_tabort3:
+; CHECK: tabort 1234(%r2)
+; CHECK: br %r14
+  %sum = add i64 %val, 1234
+  call void @llvm.s390.tabort(i64 %sum)
+  ret void
+}
+
+; TABORT with out-of-range immediate.
+define void @test_tabort4(i64 %val) {
+; CHECK-LABEL: test_tabort4:
+; CHECK: tabort 0({{%r[1-5]}})
+; CHECK: br %r14
+  call void @llvm.s390.tabort(i64 4096)
+  ret void
+}
+
+; NTSTG with base pointer only.
+define void @test_ntstg1(i64 *%ptr, i64 %val) {
+; CHECK-LABEL: test_ntstg1:
+; CHECK: ntstg %r3, 0(%r2)
+; CHECK: br %r14
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with base and index.
+; Check that VSTL doesn't allow an index.
+define void @test_ntstg2(i64 *%base, i64 %index, i64 %val) {
+; CHECK-LABEL: test_ntstg2:
+; CHECK: sllg [[REG:%r[1-5]]], %r3, 3
+; CHECK: ntstg %r4, 0([[REG]],%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 %index
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the highest in-range displacement.
+define void @test_ntstg3(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg3:
+; CHECK: ntstg %r3, 524280(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65535
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range positive displacement.
+define void @test_ntstg4(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg4:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with the lowest in-range displacement.
+define void @test_ntstg5(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg5:
+; CHECK: ntstg %r3, -524288(%r2)
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65536
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; NTSTG with an out-of-range negative displacement.
+define void @test_ntstg6(i64 *%base, i64 %val) {
+; CHECK-LABEL: test_ntstg6:
+; CHECK: ntstg %r3, 0({{%r[1-5]}})
+; CHECK: br %r14
+  %ptr = getelementptr i64, i64 *%base, i64 -65537
+  call void @llvm.s390.ntstg(i64 %val, i64 *%ptr)
+  ret void
+}
+
+; ETND.
+define i32 @test_etnd() {
+; CHECK-LABEL: test_etnd:
+; CHECK: etnd %r2
+; CHECK: br %r14
+  %res = call i32 @llvm.s390.etnd()
+  ret i32 %res
+}
+
+; PPA (Transaction-Abort Assist)
+define void @test_ppa_txassist(i32 %val) {
+; CHECK-LABEL: test_ppa_txassist:
+; CHECK: ppa %r2, 0, 1
+; CHECK: br %r14
+  call void @llvm.s390.ppa.txassist(i32 %val)
+  ret void
+}
+
Index: llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-bad-zEC12.s
@@ -3,6 +3,22 @@
 # RUN: FileCheck < %t %s

 #CHECK: error: invalid operand
+#CHECK: ntstg %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ntstg %r0, 524288
+
+ ntstg %r0, -524289
+ ntstg %r0, 524288
+
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, -1
+#CHECK: error: invalid operand
+#CHECK: ppa %r0, %r0, 16
+
+ ppa %r0, %r0, -1
+ ppa %r0, %r0, 16
+
+#CHECK: error: invalid operand
 #CHECK: risbgn %r0,%r0,0,0,-1
 #CHECK: error: invalid operand
 #CHECK: risbgn %r0,%r0,0,0,64
@@ -22,3 +38,47 @@
  risbgn %r0,%r0,-1,0,0
  risbgn %r0,%r0,256,0,0

+#CHECK: error: invalid operand
+#CHECK: tabort -1
+#CHECK: error: invalid operand
+#CHECK: tabort 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tabort 0(%r1,%r2)
+
+ tabort -1
+ tabort 4096
+ tabort 0(%r1,%r2)
+
+#CHECK: error: invalid operand
+#CHECK: tbegin -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbegin 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbegin 0, 65536
+
+ tbegin -1, 0
+ tbegin 4096, 0
+ tbegin 0(%r1,%r2), 0
+ tbegin 0, -1
+ tbegin 0, 65536
+
+#CHECK: error: invalid operand
+#CHECK: tbeginc -1, 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: tbeginc 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, -1
+#CHECK: error: invalid operand
+#CHECK: tbeginc 0, 65536
+
+ tbeginc -1, 0
+ tbeginc 4096, 0
+ tbeginc 0(%r1,%r2), 0
+ tbeginc 0, -1
+ tbeginc 0, 65536
Index: llvm-head/test/MC/SystemZ/insn-good-zEC12.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-good-zEC12.s
+++ llvm-head/test/MC/SystemZ/insn-good-zEC12.s
@@ -1,6 +1,48 @@
 # For zEC12 and above.
 # RUN: llvm-mc -triple s390x-linux-gnu -mcpu=zEC12 -show-encoding %s | FileCheck %s

+#CHECK: etnd %r0                     # encoding: [0xb2,0xec,0x00,0x00]
+#CHECK: etnd %r15                    # encoding: [0xb2,0xec,0x00,0xf0]
+#CHECK: etnd %r7                     # encoding: [0xb2,0xec,0x00,0x70]
+
+ etnd %r0
+ etnd %r15
+ etnd %r7
+
+#CHECK: ntstg %r0, -524288            # encoding: [0xe3,0x00,0x00,0x00,0x80,0x25]
+#CHECK: ntstg %r0, -1                 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x25]
+#CHECK: ntstg %r0, 0                  # encoding: [0xe3,0x00,0x00,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 1                  # encoding: [0xe3,0x00,0x00,0x01,0x00,0x25]
+#CHECK: ntstg %r0, 524287             # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 0(%r1)             # encoding: [0xe3,0x00,0x10,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 0(%r15)            # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x25]
+#CHECK: ntstg %r0, 524287(%r1,%r15)   # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x25]
+#CHECK: ntstg %r0, 524287(%r15,%r1)   # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x25]
+#CHECK: ntstg %r15, 0                 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x25]
+
+ ntstg %r0, -524288
+ ntstg %r0, -1
+ ntstg %r0, 0
+ ntstg %r0, 1
+ ntstg %r0, 524287
+ ntstg %r0, 0(%r1)
+ ntstg %r0, 0(%r15)
+ ntstg %r0, 524287(%r1,%r15)
+ ntstg %r0, 524287(%r15,%r1)
+ ntstg %r15, 0
+
+#CHECK: ppa %r0, %r0, 0             # encoding: [0xb2,0xe8,0x00,0x00]
+#CHECK: ppa %r0, %r0, 15            # encoding: [0xb2,0xe8,0xf0,0x00]
+#CHECK: ppa %r0, %r15, 0            # encoding: [0xb2,0xe8,0x00,0x0f]
+#CHECK: ppa %r4, %r6, 7             # encoding: [0xb2,0xe8,0x70,0x46]
+#CHECK: ppa %r15, %r0, 0            # encoding: [0xb2,0xe8,0x00,0xf0]
+
+ ppa %r0, %r0, 0
+ ppa %r0, %r0, 15
+ ppa %r0, %r15, 0
+ ppa %r4, %r6, 7
+ ppa %r15, %r0, 0
+
 #CHECK: risbgn %r0, %r0, 0, 0, 0       # encoding: [0xec,0x00,0x00,0x00,0x00,0x59]
 #CHECK: risbgn %r0, %r0, 0, 0, 63      # encoding: [0xec,0x00,0x00,0x00,0x3f,0x59]
 #CHECK: risbgn %r0, %r0, 0, 255, 0     # encoding: [0xec,0x00,0x00,0xff,0x00,0x59]
@@ -17,3 +59,68 @@
  risbgn %r15,%r0,0,0,0
  risbgn %r4,%r5,6,7,8

+#CHECK: tabort 0                       # encoding: [0xb2,0xfc,0x00,0x00]
+#CHECK: tabort 0(%r1)                  # encoding: [0xb2,0xfc,0x10,0x00]
+#CHECK: tabort 0(%r15)                 # encoding: [0xb2,0xfc,0xf0,0x00]
+#CHECK: tabort 4095                    # encoding: [0xb2,0xfc,0x0f,0xff]
+#CHECK: tabort 4095(%r1)               # encoding: [0xb2,0xfc,0x1f,0xff]
+#CHECK: tabort 4095(%r15)              # encoding: [0xb2,0xfc,0xff,0xff]
+
+ tabort 0
+ tabort 0(%r1)
+ tabort 0(%r15)
+ tabort 4095
+ tabort 4095(%r1)
+ tabort 4095(%r15)
+
+#CHECK: tbegin 0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 4095, 0                 # encoding: [0xe5,0x60,0x0f,0xff,0x00,0x00]
+#CHECK: tbegin 0, 0                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x00]
+#CHECK: tbegin 0, 1                    # encoding: [0xe5,0x60,0x00,0x00,0x00,0x01]
+#CHECK: tbegin 0, 32767                # encoding: [0xe5,0x60,0x00,0x00,0x7f,0xff]
+#CHECK: tbegin 0, 32768                # encoding: [0xe5,0x60,0x00,0x00,0x80,0x00]
+#CHECK: tbegin 0, 65535                # encoding: [0xe5,0x60,0x00,0x00,0xff,0xff]
+#CHECK: tbegin 0(%r1), 42              # encoding: [0xe5,0x60,0x10,0x00,0x00,0x2a]
+#CHECK: tbegin 0(%r15), 42             # encoding: [0xe5,0x60,0xf0,0x00,0x00,0x2a]
+#CHECK: tbegin 4095(%r1), 42           # encoding: [0xe5,0x60,0x1f,0xff,0x00,0x2a]
+#CHECK: tbegin 4095(%r15), 42          # encoding: [0xe5,0x60,0xff,0xff,0x00,0x2a]
+
+ tbegin 0, 0
+ tbegin 4095, 0
+ tbegin 0, 0
+ tbegin 0, 1
+ tbegin 0, 32767
+ tbegin 0, 32768
+ tbegin 0, 65535
+ tbegin 0(%r1), 42
+ tbegin 0(%r15), 42
+ tbegin 4095(%r1), 42
+ tbegin 4095(%r15), 42
+
+#CHECK: tbeginc 0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 4095, 0                 # encoding: [0xe5,0x61,0x0f,0xff,0x00,0x00]
+#CHECK: tbeginc 0, 0                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x00]
+#CHECK: tbeginc 0, 1                    # encoding: [0xe5,0x61,0x00,0x00,0x00,0x01]
+#CHECK: tbeginc 0, 32767                # encoding: [0xe5,0x61,0x00,0x00,0x7f,0xff]
+#CHECK: tbeginc 0, 32768                # encoding: [0xe5,0x61,0x00,0x00,0x80,0x00]
+#CHECK: tbeginc 0, 65535                # encoding: [0xe5,0x61,0x00,0x00,0xff,0xff]
+#CHECK: tbeginc 0(%r1), 42              # encoding: [0xe5,0x61,0x10,0x00,0x00,0x2a]
+#CHECK: tbeginc 0(%r15), 42             # encoding: [0xe5,0x61,0xf0,0x00,0x00,0x2a]
+#CHECK: tbeginc 4095(%r1), 42           # encoding: [0xe5,0x61,0x1f,0xff,0x00,0x2a]
+#CHECK: tbeginc 4095(%r15), 42          # encoding: [0xe5,0x61,0xff,0xff,0x00,0x2a]
+
+ tbeginc 0, 0
+ tbeginc 4095, 0
+ tbeginc 0, 0
+ tbeginc 0, 1
+ tbeginc 0, 32767
+ tbeginc 0, 32768
+ tbeginc 0, 65535
+ tbeginc 0(%r1), 42
+ tbeginc 0(%r15), 42
+ tbeginc 4095(%r1), 42
+ tbeginc 4095(%r15), 42
+
+#CHECK: tend                            # encoding: [0xb2,0xf8,0x00,0x00]
+
+ tend
Index: llvm-head/test/MC/SystemZ/insn-bad-z196.s
===================================================================
--- llvm-head.orig/test/MC/SystemZ/insn-bad-z196.s
+++ llvm-head/test/MC/SystemZ/insn-bad-z196.s
@@ -244,6 +244,11 @@
  cxlgbr %f0, 16, %r0, 0
  cxlgbr %f2, 0, %r0, 0

+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: etnd %r7
+
+ etnd %r7
+
 #CHECK: error: invalid operand
 #CHECK: fidbra %f0, 0, %f0, -1
 #CHECK: error: invalid operand
@@ -546,6 +551,16 @@
  locr %r0,%r0,-1
  locr %r0,%r0,16

+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: ntstg %r0, 524287(%r1,%r15)
+
+ ntstg %r0, 524287(%r1,%r15)
+
+#CHECK: error: {{(instruction requires: processor-assist)?}}
+#CHECK: ppa %r4, %r6, 7
+
+ ppa %r4, %r6, 7
+
 #CHECK: error: {{(instruction requires: miscellaneous-extensions)?}}
 #CHECK: risbgn %r1, %r2, 0, 0, 0

@@ -690,3 +705,24 @@
  stocg %r0,-524289,1
  stocg %r0,524288,1
  stocg %r0,0(%r1,%r2),1
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tabort 4095(%r1)
+
+ tabort 4095(%r1)
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbegin 4095(%r1), 42
+
+ tbegin 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tbeginc 4095(%r1), 42
+
+ tbeginc 4095(%r1), 42
+
+#CHECK: error: {{(instruction requires: transactional-execution)?}}
+#CHECK: tend
+
+ tend
+
Index: llvm-head/test/MC/Disassembler/SystemZ/insns.txt
===================================================================
--- llvm-head.orig/test/MC/Disassembler/SystemZ/insns.txt
+++ llvm-head/test/MC/Disassembler/SystemZ/insns.txt
@@ -2503,6 +2503,15 @@
 # CHECK: ear %r15, %a15
 0xb2 0x4f 0x00 0xff

+# CHECK: etnd %r0
+0xb2 0xec 0x00 0x00
+
+# CHECK: etnd %r15
+0xb2 0xec 0x00 0xf0
+
+# CHECK: etnd %r7
+0xb2 0xec 0x00 0x70
+
 # CHECK: fidbr %f0, 0, %f0
 0xb3 0x5f 0x00 0x00

@@ -6034,6 +6043,36 @@
 # CHECK: ny %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x54

+# CHECK: ntstg %r0, -524288
+0xe3 0x00 0x00 0x00 0x80 0x25
+
+# CHECK: ntstg %r0, -1
+0xe3 0x00 0x0f 0xff 0xff 0x25
+
+# CHECK: ntstg %r0, 0
+0xe3 0x00 0x00 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 1
+0xe3 0x00 0x00 0x01 0x00 0x25
+
+# CHECK: ntstg %r0, 524287
+0xe3 0x00 0x0f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 0(%r1)
+0xe3 0x00 0x10 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 0(%r15)
+0xe3 0x00 0xf0 0x00 0x00 0x25
+
+# CHECK: ntstg %r0, 524287(%r1,%r15)
+0xe3 0x01 0xff 0xff 0x7f 0x25
+
+# CHECK: ntstg %r0, 524287(%r15,%r1)
+0xe3 0x0f 0x1f 0xff 0x7f 0x25
+
+# CHECK: ntstg %r15, 0
+0xe3 0xf0 0x00 0x00 0x00 0x25
+
 # CHECK: oc 0(1), 0
 0xd6 0x00 0x00 0x00 0x00 0x00

@@ -6346,6 +6385,21 @@
 # CHECK: popcnt %r7, %r8
 0xb9 0xe1 0x00 0x78

+# CHECK: ppa %r0, %r0, 0
+0xb2 0xe8 0x00 0x00
+
+# CHECK: ppa %r0, %r0, 15
+0xb2 0xe8 0xf0 0x00
+
+# CHECK: ppa %r0, %r15, 0
+0xb2 0xe8 0x00 0x0f
+
+# CHECK: ppa %r4, %r6, 7
+0xb2 0xe8 0x70 0x46
+
+# CHECK: ppa %r15, %r0, 0
+0xb2 0xe8 0x00 0xf0
+
 # CHECK: risbg %r0, %r0, 0, 0, 0
 0xec 0x00 0x00 0x00 0x00 0x55

@@ -8062,6 +8116,93 @@
 # CHECK: sy %r15, 0
 0xe3 0xf0 0x00 0x00 0x00 0x5b

+# CHECK: tabort 0
+0xb2 0xfc 0x00 0x00
+
+# CHECK: tabort 0(%r1)
+0xb2 0xfc 0x10 0x00
+
+# CHECK: tabort 0(%r15)
+0xb2 0xfc 0xf0 0x00
+
+# CHECK: tabort 4095
+0xb2 0xfc 0x0f 0xff
+
+# CHECK: tabort 4095(%r1)
+0xb2 0xfc 0x1f 0xff
+
+# CHECK: tabort 4095(%r15)
+0xb2 0xfc 0xff 0xff
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 4095, 0
+0xe5 0x60 0x0f 0xff 0x00 0x00
+
+# CHECK: tbegin 0, 0
+0xe5 0x60 0x00 0x00 0x00 0x00
+
+# CHECK: tbegin 0, 1
+0xe5 0x60 0x00 0x00 0x00 0x01
+
+# CHECK: tbegin 0, 32767
+0xe5 0x60 0x00 0x00 0x7f 0xff
+
+# CHECK: tbegin 0, 32768
+0xe5 0x60 0x00 0x00 0x80 0x00
+
+# CHECK: tbegin 0, 65535
+0xe5 0x60 0x00 0x00 0xff 0xff
+
+# CHECK: tbegin 0(%r1), 42
+0xe5 0x60 0x10 0x00 0x00 0x2a
+
+# CHECK: tbegin 0(%r15), 42
+0xe5 0x60 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbegin 4095(%r1), 42
+0xe5 0x60 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbegin 4095(%r15), 42
+0xe5 0x60 0xff 0xff 0x00 0x2a
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 4095, 0
+0xe5 0x61 0x0f 0xff 0x00 0x00
+
+# CHECK: tbeginc 0, 0
+0xe5 0x61 0x00 0x00 0x00 0x00
+
+# CHECK: tbeginc 0, 1
+0xe5 0x61 0x00 0x00 0x00 0x01
+
+# CHECK: tbeginc 0, 32767
+0xe5 0x61 0x00 0x00 0x7f 0xff
+
+# CHECK: tbeginc 0, 32768
+0xe5 0x61 0x00 0x00 0x80 0x00
+
+# CHECK: tbeginc 0, 65535
+0xe5 0x61 0x00 0x00 0xff 0xff
+
+# CHECK: tbeginc 0(%r1), 42
+0xe5 0x61 0x10 0x00 0x00 0x2a
+
+# CHECK: tbeginc 0(%r15), 42
+0xe5 0x61 0xf0 0x00 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r1), 42
+0xe5 0x61 0x1f 0xff 0x00 0x2a
+
+# CHECK: tbeginc 4095(%r15), 42
+0xe5 0x61 0xff 0xff 0x00 0x2a
+
+# CHECK: tend
+0xb2 0xf8 0x00 0x00
+
 # CHECK: tm 0, 0
 0x91 0x00 0x00 0x00

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233803 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoTry to unbreak Clang build to export LLVM_ABI_BREAKING_CHECKS, fixup for r233310.
NAKAMURA Takumi [Wed, 1 Apr 2015 11:46:15 +0000 (11:46 +0000)]
Try to unbreak Clang build to export LLVM_ABI_BREAKING_CHECKS, fixup for r233310.

FIXME: Should ENABLE_ABI_BREAKING_CHECKS be tri-state, "ON/OFF/blank"?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233801 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoAdd -mcpu=native support to opt.
Craig Topper [Wed, 1 Apr 2015 05:32:04 +0000 (05:32 +0000)]
Add -mcpu=native support to opt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233789 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Implement support for catch-all
David Majnemer [Wed, 1 Apr 2015 05:20:42 +0000 (05:20 +0000)]
[WinEH] Implement support for catch-all

A catch (...) doesn't have a type descriptor.  Instead, the 'adjectives'
field has bit six set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233788 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[Orc] Reflect process symbols into the LLI Orc-lazy JIT.
Lang Hames [Wed, 1 Apr 2015 04:42:56 +0000 (04:42 +0000)]
[Orc] Reflect process symbols into the LLI Orc-lazy JIT.

This makes symbol resolution essentially identical between MCJIT and the LLI
Orc-lazy JIT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233786 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[CMake] Cache LLVM_ABI_BREAKING_CHECKS in LLVMConfig.cmake.
Sanjoy Das [Wed, 1 Apr 2015 03:16:10 +0000 (03:16 +0000)]
[CMake] Cache LLVM_ABI_BREAKING_CHECKS in LLVMConfig.cmake.

Not having this breaks clang builds that use an already-built LLVM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233784 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix PR23065. Avoid optimizing bitcast of build_vector with constant input to scalar_t...
Jiangning Liu [Wed, 1 Apr 2015 01:52:38 +0000 (01:52 +0000)]
Fix PR23065. Avoid optimizing bitcast of build_vector with constant input to scalar_to_vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233778 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SimplifyLibCalls] Ignore nobuiltin/unavailable fortified libcalls.
Ahmed Bougacha [Wed, 1 Apr 2015 00:45:09 +0000 (00:45 +0000)]
[SimplifyLibCalls] Ignore nobuiltin/unavailable fortified libcalls.

We used to do this before refactorings around r225640.
Some clang users checked for _chk libcall availability using:
  __has_builtin(__builtin___memcpy_chk)
When compiling with -fno-builtin, this is always true.
When passing -ffreestanding/-mkernel, which both imply -fno-builtin, we
end up with fortified libcalls, which isn't acceptable in a freestanding
environment which only provides their non-fortified counterparts.

Until we change clang and/or teach external users to check for availability
differently, disregard the "nobuiltin" attribute and TLI::has.

Workaround for PR23093.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233776 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] FastISel can't handle i1 return values when using CR bits
Hal Finkel [Wed, 1 Apr 2015 00:40:48 +0000 (00:40 +0000)]
[PowerPC] FastISel can't handle i1 return values when using CR bits

Under normal circumstances, use of CR bits is disabled when running at -O0, but
it is enabled by default otherwise, and if you have optnone functions, they'll
still generally be generated with crbits turned on (because nothing else turns
them off). FastISel can't handle most things dealing with i1 values when using
CR bits, and checks for that, but was not checking the return type on
functions; we can't fast-isel function calls with i1 return values either when
using CR bits for boolean values.

Fixes PR22664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233775 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[docs] Fix typo.
Sean Silva [Tue, 31 Mar 2015 22:48:45 +0000 (22:48 +0000)]
[docs] Fix typo.

Based on a patch by Stanislav Manilov!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233771 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] ExitingScope is vacuously true if !PoppedCatches.empty()
David Majnemer [Tue, 31 Mar 2015 22:43:56 +0000 (22:43 +0000)]
[WinEH] ExitingScope is vacuously true if !PoppedCatches.empty()

Remove a redundant condition, no functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233770 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[WinEH] Generate .xdata for catch handlers
David Majnemer [Tue, 31 Mar 2015 22:35:44 +0000 (22:35 +0000)]
[WinEH] Generate .xdata for catch handlers

This lets us catch exceptions in simple cases.

N.B. Things that do not work include (but are not limited to):
- Throwing from within a catch handler.
- Catching an object with a named catch parameter.
- 'CatchHigh' is fictitious, we aren't sure of its purpose.
- We aren't entirely efficient with regards to the number of EH states
  that we generate.
- IP-to-State tables are sensitive to the order of emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233767 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[fuzzer] more documentation
Kostya Serebryany [Tue, 31 Mar 2015 21:39:38 +0000 (21:39 +0000)]
[fuzzer] more documentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233763 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agotypo; NFC
Sanjay Patel [Tue, 31 Mar 2015 21:24:47 +0000 (21:24 +0000)]
typo; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233761 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Rename replaceWithUniqued() tests from r233751
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 21:05:06 +0000 (21:05 +0000)]
IR: Rename replaceWithUniqued() tests from r233751

replaceWithUniquedUnresolved
replaceWithUniquedUnresolvedChangedOperand
 =>
replaceWithUniquedResolvingOperand
replaceWithUniquedChangingOperand

I find the new names less confusing; they're also more accurate.  Sorry
for the churn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233759 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoVerifier: Add a testcase for verifying type refs
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 20:57:56 +0000 (20:57 +0000)]
Verifier: Add a testcase for verifying type refs

r233664 fixed the `Verifier` so that it doesn't crash on bad type refs.
This deserves a test!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233756 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[PowerPC] Don't use a vector preferred memory type at -O0
Hal Finkel [Tue, 31 Mar 2015 20:56:09 +0000 (20:56 +0000)]
[PowerPC] Don't use a vector preferred memory type at -O0

Even at -O0, we fall back to SDAG when we hit intrinsics, and if the intrinsic
is a memset/memcpy/etc. we might normally use vector types. At -O0, this is
probably not a good idea (because, if there is a bug in the lowering code,
there would be no good way to turn it off). At -O0, only use scalar preferred
types.

Related to PR22754.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233755 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[AArch64] Enable the codegenprepare optimization that promotes operation to form
Quentin Colombet [Tue, 31 Mar 2015 20:52:32 +0000 (20:52 +0000)]
[AArch64] Enable the codegenprepare optimization that promotes operation to form
extended loads.
Implement the related target lowering hook so that the optimization has a better
estimation of the cost of an extension.

rdar://problem/19267165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233753 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoFix AllocationPriority not getting set for derived register classes.
Matthias Braun [Tue, 31 Mar 2015 20:52:25 +0000 (20:52 +0000)]
Fix AllocationPriority not getting set for derived register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233752 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoIR: Enable uniquing callbacks during MDNode::replaceWithUniqued()
Duncan P. N. Exon Smith [Tue, 31 Mar 2015 20:50:50 +0000 (20:50 +0000)]
IR: Enable uniquing callbacks during MDNode::replaceWithUniqued()

Uniqued nodes have more complete registration with
`ReplaceableMetadataImpl` so that they can update themselves when
operands change.  Fix a bug where `MDNode::replaceWithUniqued()` wasn't
enabling these callbacks.

The two most obvious ways missing callbacks causes problems is that
auto-resolution fails and re-uniquing (on changed operands) just doesn't
happen.  I've added tests for both -- in both cases, I confirmed that
the final check was failing before the fix.

rdar://problem/20365935

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233751 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[MCJIT] Enable MCJIT regression tests on Darwin.
Lang Hames [Tue, 31 Mar 2015 20:48:52 +0000 (20:48 +0000)]
[MCJIT] Enable MCJIT regression tests on Darwin.

Commit r233747 fixed the issue that had been blocking this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233750 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[SDAG] Handle non-integer preferred memset types for non-constant values
Hal Finkel [Tue, 31 Mar 2015 20:35:26 +0000 (20:35 +0000)]
[SDAG] Handle non-integer preferred memset types for non-constant values

The existing code in getMemsetValue only handled integer-preferred types when
the fill value was not a constant. Make this more robust in two ways:

  1. If the preferred type is a floating-point value, do the mul-splat trick on
     the corresponding integer type and then bitcast.
  2. If the preferred type is a vector, do the mul-splat trick on one vector
     element, and then build a vector out of them.

Fixes PR22754 (although, we should also turn off use of vector types at -O0).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233749 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[ExecutionEngine] Fix MCJIT::addGlobalMapping.
Lang Hames [Tue, 31 Mar 2015 20:31:14 +0000 (20:31 +0000)]
[ExecutionEngine] Fix MCJIT::addGlobalMapping.

This patch fixes MCJIT::addGlobalMapping by changing the implementation of the
ExecutionEngineState class. The new implementation maintains a bidirectional
mapping between symbol names (std::strings) and addresses (uint64_ts), rather
than a mapping between Value*s and void*s.

This has fix has been made for backwards compatibility, however the strongly
preferred way to resolve unknown symbols is by writing a custom
RuntimeDyld::SymbolResolver (formerly RTDyldMemoryManager) and overriding the
findSymbol method. The addGlobalMapping method is a hangover from the legacy JIT
(which has was removed in 3.6), and may be deprecated in a future release as
part of a clean-up of the ExecutionEngine interface.

Patch by Murat Bolat. Thanks Murat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233747 91177308-0d34-0410-b5e6-96231b3b80d8

9 years ago[fuzzer] Add support for token-based fuzzing (e.g. for C++). Allow string flags.
Kostya Serebryany [Tue, 31 Mar 2015 20:13:20 +0000 (20:13 +0000)]
[fuzzer] Add support for token-based fuzzing (e.g. for C++). Allow string flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233745 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoClarify that higher priority means higher values.
Matthias Braun [Tue, 31 Mar 2015 20:04:46 +0000 (20:04 +0000)]
Clarify that higher priority means higher values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233744 91177308-0d34-0410-b5e6-96231b3b80d8

9 years agoRegAllocGreedy: Allow target to specify register class ordering.
Matthias Braun [Tue, 31 Mar 2015 19:57:53 +0000 (19:57 +0000)]
RegAllocGreedy: Allow target to specify register class ordering.

Specify an allocation order with a register class. This is used by register
allocators with a greedy heuristic. This is usefull as it is sometimes
beneficial to color more constrained classes first.

Differential Revision: http://reviews.llvm.org/D8626

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233743 91177308-0d34-0410-b5e6-96231b3b80d8