Add Debug+Asserts and Release+Asserts to svn:ignore properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107775 91177308-0d34-0410-b5e6-96231b3b80d8

typo in comment, regeneration not necessary

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107774 91177308-0d34-0410-b5e6-96231b3b80d8

conditionalize by CallInst::ArgOffset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107767 91177308-0d34-0410-b5e6-96231b3b80d8

conditionalize on CallInst::ArgOffset

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107766 91177308-0d34-0410-b5e6-96231b3b80d8

minor cosmetic changes that happened to sit in my tree

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107764 91177308-0d34-0410-b5e6-96231b3b80d8

Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"
builds to "Release".  The default build is unchanged (optimization on,
assertions on), however it is now called Release+Asserts.  The intent
is that future LLVM releases released via llvm.org will be Release builds
in the new sense, i.e. will have assertions disabled (currently they have
assertions enabled, for a more than 20% slowdown).  This will bring them
in line with MacOS releases, which ship with assertions disabled.  It also
means that "Release" now means the same things in make and cmake builds:
cmake already disables assertions for "Release" builds AFAICS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107758 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.2 instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107752 91177308-0d34-0410-b5e6-96231b3b80d8

Use only one multiclass to pinsrq instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107750 91177308-0d34-0410-b5e6-96231b3b80d8

Now that almost all SSE4.1 AVX instructions are added, move code around to more appropriate sections. No functionality changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107749 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 insertps, ptest and movntdqa instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107747 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 extractps and pinsr instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107746 91177308-0d34-0410-b5e6-96231b3b80d8

Revert "Remove references to INSERT_SUBREG after de-SSA" r107725.

Buildbot breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107744 91177308-0d34-0410-b5e6-96231b3b80d8

Also use REG_SEQUENCE for VTBX instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8

Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's where
they've been tested to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 Extract Integer instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107740 91177308-0d34-0410-b5e6-96231b3b80d8

By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing rather
than assuming a target will custom lower them. Targets which do so should
exlicitly mark them as having custom lowerings. PR7454.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8

Remove references to INSERT_SUBREG after de-SSA

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107732 91177308-0d34-0410-b5e6-96231b3b80d8

Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
allocated to consecutive registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8

Accept RIP-relative symbols with 'i' constraint, and
print the (%rip) only if the 'a' modifier is present.
PR 7528.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8

Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.

INSERT_SUBREG will now only appear in SSA machine instructions.

Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant
since partial redef COPY instructions appear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107726 91177308-0d34-0410-b5e6-96231b3b80d8

Track defs for all aliases in NEONMoveFix.

This means that an instruction defining an S register will affect the domain of
the parent D register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8

Add the rest of AVX SSE4.1 packed move with sign/zero extend instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8

Make test not hang waiting for input.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107721 91177308-0d34-0410-b5e6-96231b3b80d8

Add part of AVX SSE4.1 packed move with sign/zero extend instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8

Fix comment from previous patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX vblendvpd, vblendvps and vpblendvb instructions
Update VEX encoding to support those new instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8

CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.

SelectBasicBlock doesn't needs its BasicBlock argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107712 91177308-0d34-0410-b5e6-96231b3b80d8

Propagate debug loc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8

Represent NEON load/store alignments in bytes, not bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8

One more case assuming that subregs have live ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107700 91177308-0d34-0410-b5e6-96231b3b80d8

Closing tags start with slashes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107699 91177308-0d34-0410-b5e6-96231b3b80d8

Fix buildbot breakage where a def is missing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107698 91177308-0d34-0410-b5e6-96231b3b80d8

Add fixme.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107697 91177308-0d34-0410-b5e6-96231b3b80d8

minor typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107696 91177308-0d34-0410-b5e6-96231b3b80d8

Be more forgiving when calculating alias interference for physreg coalescing.

It is OK for an alias live range to overlap if there is a copy to or from the
physical register. CoalescerPair can work out if the copy is coalescable
independently of the alias.

This means that we can join with the actual destination interval instead of
using the getOrigDstReg() hack. It is no longer necessary to merge clobber
ranges into subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107695 91177308-0d34-0410-b5e6-96231b3b80d8

Reapply r107655 with fixes; insert the pseudo instruction into
the block before calling the expansion hook. And don't
put EFLAGS in a mbb's live-in list twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8

Add X86_64 ELF relocation values and ELF64 relocation classes.

Patch from Roman Divacky.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107688 91177308-0d34-0410-b5e6-96231b3b80d8

Add some more ELF OSABI values as found in the System V Application
Binary Interface specification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107685 91177308-0d34-0410-b5e6-96231b3b80d8

Fix to 80-col.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107684 91177308-0d34-0410-b5e6-96231b3b80d8

Provide IRBuilder conveniences for creating integer constants at common widths,
and give a more precise return type for some of the type-creation methods.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107683 91177308-0d34-0410-b5e6-96231b3b80d8

Alphabetize the list of function parameters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107680 91177308-0d34-0410-b5e6-96231b3b80d8

Fix PR7545 crash.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107678 91177308-0d34-0410-b5e6-96231b3b80d8

Provide an abstraction to save and restore the current insertion point of
an IRBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107677 91177308-0d34-0410-b5e6-96231b3b80d8

Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion
if profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8

tighten up this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107670 91177308-0d34-0410-b5e6-96231b3b80d8

Bring the list of passes and their descriptions up to date.
Patch by Kenneth Hoste.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107669 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r107655.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8

second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.

I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107667 91177308-0d34-0410-b5e6-96231b3b80d8

Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands
which do not depend on SelectionDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107666 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new CCValAssign LocInfo value, and a comment explaining what it
should be used for.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107661 91177308-0d34-0410-b5e6-96231b3b80d8

Make getMinimalPhysRegClass' comment mention what makes it different
from getPhysicalRegisterRegClass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107660 91177308-0d34-0410-b5e6-96231b3b80d8

Note the relationship between C99 restrict and LLVM noalias, and
clarify a few other things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107659 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a major regression on COFF targets introduced by r103267: 'discardable' section means that it is used only during the program load and can be discarded afterwards.
This way *only* debug sections can be discarded, but not the opposite. Seems like the copy-and-pasto from ELF code, since there it contains the reverse flag ('alloc').

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107658 91177308-0d34-0410-b5e6-96231b3b80d8

Add some more TODO comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107657 91177308-0d34-0410-b5e6-96231b3b80d8

Add a comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107656 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a bunch of custom-inserter functions to handle the case where
the pseudo instruction is not at the end of the block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8

Remove mistakenly added test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107641 91177308-0d34-0410-b5e6-96231b3b80d8

Fix up -fstack-protector on linux to use the segment
registers.  Split out testcases per architecture and os
now.

Patch from Nelson Elhage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8

Detabify this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107637 91177308-0d34-0410-b5e6-96231b3b80d8

Add default value to setIsNoInline for parity with the other methods of its
kind.

Also fold some functions that fit on a line to a single line.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107636 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo 'getter' where 'setter' was intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107635 91177308-0d34-0410-b5e6-96231b3b80d8

Have the X86 backend use Triple instead of a string and some enums.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8

Remove some unused/redundant code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107622 91177308-0d34-0410-b5e6-96231b3b80d8

more tidying.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107615 91177308-0d34-0410-b5e6-96231b3b80d8

another v2f32 case, in this case showing poor codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107614 91177308-0d34-0410-b5e6-96231b3b80d8

some notes about suboptimal insertps's

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107613 91177308-0d34-0410-b5e6-96231b3b80d8

random tidying

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107612 91177308-0d34-0410-b5e6-96231b3b80d8

rip out even more sporadic v2f32 support.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8

rip out the various v2f32 "mmx" handling logic, now that
v2f32 is illegal on x86.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107609 91177308-0d34-0410-b5e6-96231b3b80d8

fix test on non-x86 hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107608 91177308-0d34-0410-b5e6-96231b3b80d8

Print symbolic subreg indices on REG_SEQUENCE and INSERT_SUBREG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107602 91177308-0d34-0410-b5e6-96231b3b80d8

Just rip v2f32 support completely out of the X86 backend.  In
the example in the testcase, we now generate:

_test1:                                 ## @test1
movss 4(%esp), %xmm0
addss 8(%esp), %xmm0
movl 12(%esp), %eax
movss %xmm0, (%eax)
ret

instead of:

_test1:                                                     ## @test1
subl $20, %esp
movl 24(%esp), %eax
movq %mm0, (%esp)
movq %mm0, 8(%esp)
movss (%esp), %xmm0
addss 12(%esp), %xmm0
movss %xmm0, (%eax)
addl $20, %esp
ret

v2f32 support did not work reliably because most of the X86
backend didn't know it was legal.  It was apparently only added
to support returning source-level v2f32 values in MMX registers
in x86-32 mode.  If ABI compatibility is important on this
GCC-extended-vector type for some reason, then the frontend
should generate IR that returns v2i32 instead of v2f32.  However,
we generally don't try very hard to be abi compatible on gcc
extended vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8

fix PR7518 - terrible codegen of <2 x float>, by only marking
v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8

indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8

Infer alignments of fixed frame objects when they are constructed. This ensures remat'ed loads from fixed slots have the right alignments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107591 91177308-0d34-0410-b5e6-96231b3b80d8

indmemrem and lowerallocs are gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107587 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r107583. I no longer think that this is the way to solve the problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107585 91177308-0d34-0410-b5e6-96231b3b80d8

Mark sse_load_f32 and sse_load_f64 as having memory operands
(SDNPMemOperand). This way when they're morphed the memory operands will be
copied as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107583 91177308-0d34-0410-b5e6-96231b3b80d8

back out r107580, I have seen what I wanted

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107582 91177308-0d34-0410-b5e6-96231b3b80d8

Proper indentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107581 91177308-0d34-0410-b5e6-96231b3b80d8

[another test commit, just to tickle the selfhost buildbots; I'll back out in a few minutes]

second round of low-level interface squeeze-out:
making all of CallInst's low-level operand accessors
private

If you get compile errors I strongly urge you to
update your code.

I tried to write the necessary clues into the
header where the compiler may point to, but no
guarantees. It works for my GCC.

You have several options to update your code:

- you can use the v2.8 ArgOperand accessors
- you can go via a temporary CallSite
- you can upcast to, say, User and call its
  low-level accessors if your code is definitely
  operand-order agnostic.

If you run into serious problems, please
comment in below thread (and back out this
revision only if absolutely necessary):

<http://groups.google.com/group/llvm-dev/browse_thread/thread/64650cf343b28271>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107580 91177308-0d34-0410-b5e6-96231b3b80d8

Minor amendment to switch-lowering improvement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107569 91177308-0d34-0410-b5e6-96231b3b80d8

Note switch-lowering inefficiency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107565 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 blend, mpsadbw and vdp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8

Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107556 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 Horizontal Minimum and Position instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8

Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill slots so it's always false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8

Add AVX SSE4.1 round instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8

Detect and handle COPY in many places.

This code is transitional, it will soon be possible to eliminate
isExtractSubreg, isInsertSubreg, and isMoveInstr in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107547 91177308-0d34-0410-b5e6-96231b3b80d8

Document that BasicAA respects noalias, while InterproceduralBasicAA
does not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107546 91177308-0d34-0410-b5e6-96231b3b80d8

Describe which dependencies are relevant to noalias, and document how
AliasAnalyses have the choice to respect noalias.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107544 91177308-0d34-0410-b5e6-96231b3b80d8

Simple refactoring of SSE4.1 instructions, making room for the AVX forms

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8

Add some html anchors, to allow attributes to be linked to directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107538 91177308-0d34-0410-b5e6-96231b3b80d8

80-col fixup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107537 91177308-0d34-0410-b5e6-96231b3b80d8

Add a new target independent COPY instruction and code to lower it.

The COPY instruction is intended to replace the target specific copy
instructions for virtual registers as well as the EXTRACT_SUBREG and
INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection
DAG.

COPY is lowered to native register copies by LowerSubregs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8

- Add support for the rest of AVX SSE3 instructions
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8

Clean up TargetOpcodes.h a bit, and limit the number of places where the full
list of predefined instructions appear. Add some consistency checks.

Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it
is hardly worth the effort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8

Custom inserters (e.g., conditional moves in Thumb1 can introduce
new basic blocks, and if used as a function argument, that can cause call frame
setup / destroy pairs to be split across a basic block boundary. That prevents
us from doing a simple assertion to check that the pairs match and alloc/
dealloc the same amount of space. Modify the assertion to only check the
amount allocated when there are matching pairs in the same basic block.

rdar://8022442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107517 91177308-0d34-0410-b5e6-96231b3b80d8

MDString is already checked earlier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107516 91177308-0d34-0410-b5e6-96231b3b80d8