7 years ago[X86] Mark the AAD and AAM aliases as not valid in 64-bit mode.
Craig Topper [Tue, 13 Oct 2015 05:12:07 +0000 (05:12 +0000)]
[X86] Mark the AAD and AAM aliases as not valid in 64-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250148 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Change all the i8imm operands in XOP instructions to u8imm so the parser will...
Craig Topper [Tue, 13 Oct 2015 05:06:25 +0000 (05:06 +0000)]
[X86] Change all the i8imm operands in XOP instructions to u8imm so the parser will check the size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250147 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert 250089 due to bot failure. It failed when building clang itself with PGO.
Manman Ren [Tue, 13 Oct 2015 03:38:02 +0000 (03:38 +0000)]
Revert 250089 due to bot failure. It failed when building clang itself with PGO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250145 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcodeWriter: Stop using implicit ilist iterator conversion, NFC
Duncan P. N. Exon Smith [Tue, 13 Oct 2015 03:26:19 +0000 (03:26 +0000)]
BitcodeWriter: Stop using implicit ilist iterator conversion, NFC

Now LLVMBitWriter compiles without implicit ilist iterator conversions.

In these cases, the cleanest thing was to switch to range-based for
loops.  Since there wasn't much noise I converted sub-loops and parent
loops as a drive-by.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250144 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SCEV] Put some utilites in the ScalarEvolution class
Sanjoy Das [Tue, 13 Oct 2015 02:53:27 +0000 (02:53 +0000)]
[SCEV] Put some utilites in the ScalarEvolution class

In a later commit, `SplitBinaryAdd` will be used outside `IsConstDiff`,
so lift that out.  And lift out `IsConstDiff` as
`computeConstantDifference` to keep things clean and to avoid playing
C++ access specifier games.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250143 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTransformUtils: Remove implicit ilist iterator conversions, NFC
Duncan P. N. Exon Smith [Tue, 13 Oct 2015 02:39:05 +0000 (02:39 +0000)]
TransformUtils: Remove implicit ilist iterator conversions, NFC

Continuing the work from last week to remove implicit ilist iterator
conversions.  First related commit was probably r249767, with some more
motivation in r249925.  This edition gets LLVMTransformUtils compiling
without the implicit conversions.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250142 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLooks like malformed-machos 00000031.a test is just getting a different error
Kevin Enderby [Tue, 13 Oct 2015 01:27:28 +0000 (01:27 +0000)]
Looks like malformed-machos 00000031.a test is just getting a different error
on some of the bots.  I’ll remove this test for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250141 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDAGCombiner: Don't stop finding better chain on 2 aliases
Matt Arsenault [Tue, 13 Oct 2015 00:49:00 +0000 (00:49 +0000)]
DAGCombiner: Don't stop finding better chain on 2 aliases

The comment says this was stopped because it was unlikely to be
profitable. This is not true if you want to combine vector loads
with multiple components.

For a simple case that looks like

t0 = load t0 ...
t1 = load t0 ...
t2 = load t0 ...
t3 = load t0 ...

t4 = store t0:1, t0:1
  t5 = store t4, t1:0
    t6 = store t5, t2:0
  t7 = store t6, t3:0

We want to get all of these stores onto a chain
that is a TokenFactor of these N loads. This mostly
solves the AMDGPU merge-stores.ll regressions
with -combiner-alias-analysis for merging vector
stores of vector loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250138 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox86: preserve flags when folding atomic operations
JF Bastien [Tue, 13 Oct 2015 00:28:47 +0000 (00:28 +0000)]
x86: preserve flags when folding atomic operations

D4796 taught LLVM to fold some atomic integer operations into a single
instruction. The pattern was unaware that the instructions clobbered

This patch adds the missing EFLAGS definition.

Floating point operations don't set flags, the subsequent fadd
optimization is therefore correct. The same applies for surrounding
load/store optimizations.

Reviewers: rsmith, rtrieu

Subscribers: llvm-commits, reames, morisset

Differential Revision: http://reviews.llvm.org/D13680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250135 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Refactor isVGPRToSGPRCopy
Matt Arsenault [Tue, 13 Oct 2015 00:07:54 +0000 (00:07 +0000)]

It should now correctly handle physical registers and make
it easier to identify the other direction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250132 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove the correct unstable malformed-machos test mem-crup-0261.macho and
Kevin Enderby [Tue, 13 Oct 2015 00:05:17 +0000 (00:05 +0000)]
Remove the correct unstable malformed-machos test mem-crup-0261.macho and
restore the malformed-machos 00000031.a test.  Hopefully this will get all the
build bots happy again.  I’ll again keep an eye on them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250130 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDAGCombiner: Combine extract_vector_elt from build_vector
Matt Arsenault [Mon, 12 Oct 2015 23:59:50 +0000 (23:59 +0000)]
DAGCombiner: Combine extract_vector_elt from build_vector

This basic combine was surprisingly missing.
AMDGPU legalizes many operations in terms of 32-bit vector components,
so not doing this results in many extra copies and subregister extracts
that need to be cleaned up later.

InstCombine already does this for the hasOneUse case. The target hook
is to fix a handful of tests which break (e.g. ARM/vmov.ll) which turn
from a vector materialize repeated immediate instruction to a constant
vector load with more scalar copies from it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250129 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Tidied up SSE4A tests.
Simon Pilgrim [Mon, 12 Oct 2015 23:07:06 +0000 (23:07 +0000)]
[InstCombine] Tidied up SSE4A tests.

First stage of bugfix discussed in D13348

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250121 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTemporarily remove the test added in r250117 while I investigate why two
Kevin Enderby [Mon, 12 Oct 2015 23:03:43 +0000 (23:03 +0000)]
Temporarily remove the test added in r250117 while I investigate why two
of the build bots get a different error on that malformed file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250120 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAssign correct edge weights to unwind destinations when lowering invoke statement.
Cong Hou [Mon, 12 Oct 2015 23:02:58 +0000 (23:02 +0000)]
Assign correct edge weights to unwind destinations when lowering invoke statement.

When lowering invoke statement, all unwind destinations are directly added as successors of call site block, and the weight of those new edges are not assigned properly. Actually, default weight 16 are used for those edges. This patch calculates the proper edge weights for those edges when collecting all unwind destinations.

Differential revision: http://reviews.llvm.org/D13354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250119 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SelectionDAG] Add common vector constant folding helper function
Simon Pilgrim [Mon, 12 Oct 2015 23:00:11 +0000 (23:00 +0000)]
[SelectionDAG] Add common vector constant folding helper function

We have a number of functions that implement constant folding of vectors (unary and binary ops) in near identical manners (and the differences don't appear to be critical).

This patch introduces a common implementation (SelectionDAG::FoldConstantVectorArithmetic) and calls this in both the unary and binary op cases.

After this initial patch I intend to begin enabling vector constant folding for a wider number of opcodes in SelectionDAG::getNode().

Differential Revision: http://reviews.llvm.org/D13665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250118 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFixed bugs in llvm-obdump while parsing Mach-O files from malformed archives
Kevin Enderby [Mon, 12 Oct 2015 22:04:54 +0000 (22:04 +0000)]
Fixed bugs in llvm-obdump while parsing Mach-O files from malformed archives
that caused aborts.  This was because of the characters of the ‘Size’ field in
the archive header did not contain decimal characters.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250117 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Adding support for passing in profiling data.
Chris Bieneman [Mon, 12 Oct 2015 21:13:20 +0000 (21:13 +0000)]
[CMake] Adding support for passing in profiling data.

Adds LLVM_PROFDATA_FILE option to allow specifying a profile data file to be used during compilation of LLVM and subprojects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250108 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate the branch weight metadata in JumpThreading pass.
Cong Hou [Mon, 12 Oct 2015 19:44:08 +0000 (19:44 +0000)]
Update the branch weight metadata in JumpThreading pass.

In JumpThreading pass, the branch weight metadata is not updated after CFG modification. Consider the jump threading on PredBB, BB, and SuccBB. After jump threading, the weight on BB->SuccBB should be adjusted as some of it is contributed by the edge PredBB->BB, which doesn't exist anymore. This patch tries to update the edge weight in metadata on BB->SuccBB by scaling it by 1 - Freq(PredBB->BB) / Freq(BB->SuccBB).

Differential revision: http://reviews.llvm.org/D10979

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250089 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMake Win64 localescape offsets FP relative instead of SP relative
Reid Kleckner [Mon, 12 Oct 2015 19:43:34 +0000 (19:43 +0000)]
Make Win64 localescape offsets FP relative instead of SP relative

We made them SP relative back in March (r233137) because that's the
value the runtime passes to EH functions. With the new cleanuppad IR,
funclets adjust their frame argument from SP to FP, so our offsets
should now be FP-relative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250088 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-symbolizer] Add -print-address option
Hemant Kulkarni [Mon, 12 Oct 2015 19:26:44 +0000 (19:26 +0000)]
[llvm-symbolizer] Add -print-address option

Differential Revision: http://reviews.llvm.org/D13518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix wrong lowering of vsetcc nodes (PR25080).
Andrea Di Biagio [Mon, 12 Oct 2015 19:22:30 +0000 (19:22 +0000)]
[x86] Fix wrong lowering of vsetcc nodes (PR25080).

Function LowerVSETCC (in X86ISelLowering.cpp) worked under the wrong
assumption that for non-AVX512 targets, the source type and destination type
of a type-legalized setcc node were always the same type.

This assumption was unfortunately incorrect; the type legalizer is not always
able to promote the return type of a setcc to the same type as the first
operand of a setcc.

In the case of a vsetcc node, the legalizer firstly checks if the first input
operand has a legal type. If so, then it promotes the return type of the vsetcc
to that same type. Otherwise, the return type is promoted to the 'next legal
type', which, for vectors of MVT::i1 is always a 128-bit integer vector type.

Example (-mattr=+avx):

  %0 = trunc <8 x i32> %a to <8 x i23>
  %1 = icmp eq <8 x i23> %0, zeroinitializer

The initial selection dag for the code above is:

v8i1 = setcc t5, t7, seteq:ch
  t5: v8i23 = truncate t2
    t2: v8i32,ch = CopyFromReg t0, Register:v8i32 %vreg1
    t7: v8i32 = build_vector of all zeroes.

The type legalizer would firstly check if 't5' has a legal type. If so, then it
would reuse that same type to promote the return type of the setcc node.
Unfortunately 't5' is of illegal type v8i23, and therefore it cannot be used to
promote the return type of the setcc node. Consequently, the setcc return type
is promoted to v8i16. Later on, 't5' is promoted to v8i32 thus leading to the
following dag node:
  v8i16 = setcc t32, t25, seteq:ch

  where t32 and t25 are now values of type v8i32.

Before this patch, function LowerVSETCC would have wrongly expanded the setcc
to a single X86ISD::PCMPEQ. Surprisingly, ISel was still able to match an
instruction. In our case, ISel would have matched a VPCMPEQWrr:
  t37: v8i16 = X86ISD::VPCMPEQWrr t36, t25

However, t36 and t25 are both VR256, while the result type is instead of class
VR128. This inconsistency ended up causing the insertion of COPY instructions
like this:
  %vreg7<def> = COPY %vreg3; VR128:%vreg7 VR256:%vreg3

Which is an invalid full copy (not a sub register copy).
Eventually, the backend would have hit an UNREACHABLE "Cannot emit physreg copy
instruction" in the attempt to expand the malformed pseudo COPY instructions.

This patch fixes the problem adding the missing logic in LowerVSETCC to handle
the corner case of a setcc with 128-bit return type and 256-bit operand type.

This problem was originally reported by Dimitry as PR25080. It has been latent
for a very long time. I have added the minimal reproducible from that bugzilla
as test setcc-lowering.ll.

Differential Revision: http://reviews.llvm.org/D13660

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250085 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd - and -= operators to BlockFrequency using saturating arithmetic.
Cong Hou [Mon, 12 Oct 2015 18:34:00 +0000 (18:34 +0000)]
Add - and -= operators to BlockFrequency using saturating arithmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250077 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] mention more trophies and improve the link formatting
Kostya Serebryany [Mon, 12 Oct 2015 18:15:42 +0000 (18:15 +0000)]
[libFuzzer] mention more trophies and improve the link formatting

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250076 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agocombine predicates; NFCI
Sanjay Patel [Mon, 12 Oct 2015 18:15:08 +0000 (18:15 +0000)]
combine predicates; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250075 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTurn const/const& into value type for BlockFrequency in functions of this class....
Cong Hou [Mon, 12 Oct 2015 18:14:15 +0000 (18:14 +0000)]
Turn const/const& into value type for BlockFrequency in functions of this class. Also fix a naming issue. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250074 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-symbolizer] Reverting r250067
Colin LeMahieu [Mon, 12 Oct 2015 17:57:02 +0000 (17:57 +0000)]
[llvm-symbolizer] Reverting r250067

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250072 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Register some more passes so -print-before works
Matt Arsenault [Mon, 12 Oct 2015 17:43:59 +0000 (17:43 +0000)]
AMDGPU: Register some more passes so -print-before works

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250071 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEnable verifier after PeepholeOptimizer
Matt Arsenault [Mon, 12 Oct 2015 17:43:56 +0000 (17:43 +0000)]
Enable verifier after PeepholeOptimizer

No tests fail with this enabled so I assume it was an accident
that it isn't enabled now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250070 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't call PrepareEHLandingPad on non EH pads
Reid Kleckner [Mon, 12 Oct 2015 17:42:32 +0000 (17:42 +0000)]
Don't call PrepareEHLandingPad on non EH pads

This was a minor bug in r249492. Calling PrepareEHLandingPad on a
non-landingpad was a no-op, but it attempted to get the generic pointer
register class, which apparently doesn't exist for some targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250068 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-symbolizer] Add -print-address option
Hemant Kulkarni [Mon, 12 Oct 2015 17:31:22 +0000 (17:31 +0000)]
[llvm-symbolizer] Add -print-address option

Differential Revision  http://reviews.llvm.org/D13518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250067 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Remove CatchObjRecoverIdx
David Majnemer [Mon, 12 Oct 2015 16:44:22 +0000 (16:44 +0000)]
[WinEH] Remove CatchObjRecoverIdx

CatchObjRecoverIdx was used for the old scheme, it is no longer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250065 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix typos; NFC
Sanjay Patel [Mon, 12 Oct 2015 16:09:59 +0000 (16:09 +0000)]
fix typos; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250059 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb impleme...
Zoran Jovanovic [Mon, 12 Oct 2015 16:07:25 +0000 (16:07 +0000)]
[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
Differential Revision: http://reviews.llvm.org/D12798

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250058 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Debug] Look through bitcasts to find argument registers
Oliver Stannard [Mon, 12 Oct 2015 15:52:36 +0000 (15:52 +0000)]
[Debug] Look through bitcasts to find argument registers

On targets where f32 is not legal, we have to look through a BITCAST SDNode to
find the register that an argument is stored in when emitting debug info, or we
will not be able to emit a DW_AT_location for it.

Differential Revision: http://reviews.llvm.org/D13005

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250056 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][FastISel] Clang-format switch statement. NFC.
Vasileios Kalintiris [Mon, 12 Oct 2015 15:39:41 +0000 (15:39 +0000)]
[mips][FastISel] Clang-format switch statement. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250053 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64]Fix bug in function names in test case
Jun Bum Lim [Mon, 12 Oct 2015 15:34:52 +0000 (15:34 +0000)]
[AArch64]Fix bug in function names in test case

Functions in this test case need to be renamed as its names are the same
as the instructions we are comparing with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250052 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix capitalization; NFC
Sanjay Patel [Mon, 12 Oct 2015 15:24:01 +0000 (15:24 +0000)]
fix capitalization; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250049 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix rename() sometimes failing if another process uses openFileForRead()
Greg Bedwell [Mon, 12 Oct 2015 15:11:47 +0000 (15:11 +0000)]
Fix rename() sometimes failing if another process uses openFileForRead()

On Windows, fs::rename() could fail is another process was reading the
file at the same time using fs::openFileForRead().  In most cases the user
wouldn't notice as fs::rename() will continue to retry for 2000ms.  Typically
this is enough for the read to complete and a retry to succeed, but if the
disk is being it too hard then the response time might be longer than the
retry time and the rename would fail with a permission error.

Add FILE_SHARE_DELETE to the sharing flags for CreateFileW() in
fs::openFileForRead() and try ReplaceFileW() prior to MoveFileExW()
in fs::rename().

Based on an initial patch by Edd Dawson!

Differential Revision: http://reviews.llvm.org/D13647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250046 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][ias] Implement macro expansion when bcc has an immediate where a register...
Daniel Sanders [Mon, 12 Oct 2015 14:24:05 +0000 (14:24 +0000)]
[mips][ias] Implement macro expansion when bcc has an immediate where a register belongs.

Summary: Fixes PR24915.

Reviewers: vkalintiris

Subscribers: emaste, seanbruno, llvm-commits

Differential Revision: http://reviews.llvm.org/D13533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250042 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Whitespace cleanup in MIPS16 tests to reduce noise in following changes. NFC.
Daniel Sanders [Mon, 12 Oct 2015 14:16:52 +0000 (14:16 +0000)]
[mips] Whitespace cleanup in MIPS16 tests to reduce noise in following changes. NFC.

Mostly tabs -> spaces and double spacing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250041 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Clean up most macro expansions to use the emit*() functions.
Daniel Sanders [Mon, 12 Oct 2015 14:09:12 +0000 (14:09 +0000)]
[mips] Clean up most macro expansions to use the emit*() functions.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250040 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Handle undef when extracting subregs from FP64 registers.
Daniel Sanders [Mon, 12 Oct 2015 13:55:44 +0000 (13:55 +0000)]
[mips] Handle undef when extracting subregs from FP64 registers.

This removes unnecessary instructions when extracting from an undefined register
and also fixes a crash for O32 when passing undef to a double argument in
held in integer registers.

Reviewers: vkalintiris

Subscribers: llvm-commits, zoran.jovanovic, petarj

Differential Revision: http://reviews.llvm.org/D13467

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250039 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGlobalOpt does not treat externally_initialized globals correctly
Oliver Stannard [Mon, 12 Oct 2015 13:20:52 +0000 (13:20 +0000)]
GlobalOpt does not treat externally_initialized globals correctly

GlobalOpt currently merges stores into the initialisers of internal,
externally_initialized globals, but should not do so as the value of the global
may change between the initialiser and any code in the module being run.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250035 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] Mark Swift MISched model as incomplete
James Molloy [Mon, 12 Oct 2015 12:49:59 +0000 (12:49 +0000)]
[ARM] Mark Swift MISched model as incomplete

The Swift Machine Scheduler Model is incomplete. There are instructions
missing which can trigger the "incomplete machine model" abort. This was
observed when a downstream SchedMachineModel was added to the ARM

Patch by Christof Douma!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250033 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopVectorize] Shrink integer operations into the smallest type possible
James Molloy [Mon, 12 Oct 2015 12:34:45 +0000 (12:34 +0000)]
[LoopVectorize] Shrink integer operations into the smallest type possible

C semantics force sub-int-sized values (e.g. i8, i16) to be promoted to int
type (e.g. i32) whenever arithmetic is performed on them.

For targets with native i8 or i16 operations, usually InstCombine can shrink
the arithmetic type down again. However InstCombine refuses to create illegal
types, so for targets without i8 or i16 registers, the lengthening and
shrinking remains.

Most SIMD ISAs (e.g. NEON) however support vectors of i8 or i16 even when
their scalar equivalents do not, so during vectorization it is important to
remove these lengthens and truncates when deciding the profitability of

The algorithm this uses starts at truncs and icmps, trawling their use-def
chains until they terminate or instructions outside the loop are found (or
unsafe instructions like inttoptr casts are found). If the use-def chains
starting from different root instructions (truncs/icmps) meet, they are
unioned. The demanded bits of each node in the graph are ORed together to form
an overall mask of the demanded bits in the entire graph. The minimum bitwidth
that graph can be truncated to is the bitwidth minus the number of leading
zeroes in the overall mask.

The intention is that this algorithm should "first do no harm", so it will
never insert extra cast instructions. This is why the use-def graphs are
unioned, so that subgraphs with different minimum bitwidths do not need casts
inserted between them.

This algorithm works hard to reduce compile time impact. DemandedBits are only
queried if there are extends of illegal types and if a truncate to an illegal
type is seen. In the general case, this results in a simple linear scan of the
instructions in the loop.

No non-noise compile time impact was seen on a clang bootstrap build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250032 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add XSAVE intrinsic family
Amjad Aboud [Mon, 12 Oct 2015 11:47:46 +0000 (11:47 +0000)]
[X86] Add XSAVE intrinsic family

Add intrinsics for the
  XSAVEC instructions (XSAVEC/XSAVEC64)

Differential Revision: http://reviews.llvm.org/D13012

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250029 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] PR24562: fix incorrect folding of PSHUFB nodes with a mask where all indices...
Andrea Di Biagio [Mon, 12 Oct 2015 11:25:41 +0000 (11:25 +0000)]
[x86] PR24562: fix incorrect folding of PSHUFB nodes with a mask where all indices have the most significant bit set.

This patch fixes a problem in function 'combineX86ShuffleChain' that causes a
chain of shuffles to be wrongly folded away when the combined shuffle mask has
only one element.

We may end up with a combined shuffle mask of one element as a result of
multiple calls to function 'canWidenShuffleElements()'.
Function canWidenShuffleElements attempts to simplify a shuffle mask by widening
the size of the elements being shuffled.
For every pair of shuffle indices, function canWidenShuffleElements checks if
indices refer to adjacent elements. If all pairs refer to "adjacent" elements
then the shuffle mask is safely widened. As a consequence of widening, we end up
with a new shuffle mask which is half the size of the original shuffle mask.

The byte shuffle (pshufb) from test pr24562.ll has a mask of all SM_SentinelZero
indices. Function canWidenShuffleElements would combine each pair of
SM_SentinelZero indices into a single SM_SentinelZero index. So, in a
logarithmic number of steps (4 in this case), the pshufb mask is simplified to
a mask with only one index which is equal to SM_SentinelZero.

Before this patch, function combineX86ShuffleChain wrongly assumed that a mask
of size one is always equivalent to an identity mask. So, the entire shuffle
chain was just folded away as the combined shuffle mask was treated as a no-op

With this patch we know check if the only element of a combined shuffle mask is
SM_SentinelZero. In case, we propagate a zero vector.

Differential Revision: http://reviews.llvm.org/D13364

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250027 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTest commit
Zlatko Buljan [Mon, 12 Oct 2015 11:19:40 +0000 (11:19 +0000)]
Test commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250026 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agocmake: Avoid leading space in LLVM_DEFINITIONS.
Pawel Bylica [Mon, 12 Oct 2015 10:42:03 +0000 (10:42 +0000)]
cmake: Avoid leading space in LLVM_DEFINITIONS.

Summary: Unnecessary space at the beginning of LLVM_DEFINITIONS in cmake shared files can break projects that use the variable.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13432

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250025 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] testcase MC/SystemZ/insn-good-z13.s extended.
Jonas Paulsson [Mon, 12 Oct 2015 10:13:57 +0000 (10:13 +0000)]
[SystemZ] testcase MC/SystemZ/insn-good-z13.s extended.

New instructions using floating point registers have been added, to check
that AsmParser can deal with fp regs in vector instructions.

This tests r249810.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250023 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MISched] Python script to check coverage of misched info
James Molloy [Mon, 12 Oct 2015 08:50:47 +0000 (08:50 +0000)]
[MISched] Python script to check coverage of misched info

This script prints a CSV of all misched models of a target when given the output of the debug output of subtarget using:

    llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter ...

With thanks to Dave Estes for mentioning the idea at the 2014 LLVM Developers' Meeting.

Patch by Christof Douma!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250020 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSCEV: Allow simple AddRec * Parameter products in delinearization
Tobias Grosser [Mon, 12 Oct 2015 08:02:00 +0000 (08:02 +0000)]
SCEV: Allow simple AddRec * Parameter products in delinearization

This patch also allows the -delinearize pass to delinearize expressions that do
not have an outermost SCEVAddRec expression. The SCEV::delinearize
infrastructure allowed this since r240952, but the -delinearize pass was not
updated yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250018 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Use u8imm for the immediate type for all shift and rotate instructions. This...
Craig Topper [Mon, 12 Oct 2015 06:23:10 +0000 (06:23 +0000)]
[X86] Use u8imm for the immediate type for all shift and rotate instructions. This way the assembler will perform range checking. Believe this matches gas behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250016 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add support to assembler and MCInst lowering to use the other vmovq %xmmX,...
Craig Topper [Mon, 12 Oct 2015 04:57:59 +0000 (04:57 +0000)]
[X86] Add support to assembler and MCInst lowering to use the other vmovq %xmmX, %xmmX encoding if it would be a shorter VEX encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250014 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Cleanup formatting a bit. NFC
Craig Topper [Mon, 12 Oct 2015 04:27:17 +0000 (04:27 +0000)]
[X86] Cleanup formatting a bit. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250013 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser...
Craig Topper [Mon, 12 Oct 2015 04:17:55 +0000 (04:17 +0000)]
[X86] Change the immediate for IN/OUT instructions to u8imm so the assembly parser will check the size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250012 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add some instruction aliases to get the assembly parser table to favor arithmet...
Craig Topper [Mon, 12 Oct 2015 03:39:57 +0000 (03:39 +0000)]
[X86] Add some instruction aliases to get the assembly parser table to favor arithmetic instructions with 8-bit immediates over the forms that implicitly use the ax/eax/rax.

This allows us to remove the explicit code for working around the existing priority

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250011 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-rtdyld] General modernization/cleanup in preparation for (bigger) changes.
Davide Italiano [Mon, 12 Oct 2015 00:57:29 +0000 (00:57 +0000)]
[llvm-rtdyld] General modernization/cleanup in preparation for (bigger) changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250004 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Bugpoint] Get rid of dead code. No functional change.
Davide Italiano [Sun, 11 Oct 2015 21:36:11 +0000 (21:36 +0000)]
[Bugpoint] Get rid of dead code. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249999 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fix CMP and TEST with al/ax/eax/rax to not mark EFLAGS as a use or al/ax/eax...
Craig Topper [Sun, 11 Oct 2015 19:54:02 +0000 (19:54 +0000)]
[X86] Fix CMP and TEST with al/ax/eax/rax to not mark EFLAGS as a use or al/ax/eax/rax as a def. Probably doesn't have a functional affect since these aren't used in isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249994 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Improved FMA combine support for vectors
Simon Pilgrim [Sun, 11 Oct 2015 19:48:12 +0000 (19:48 +0000)]
[DAGCombiner] Improved FMA combine support for vectors

Enabled constant canonicalization for all constants.

Improved combining of constant vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249993 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Completed SHL cost model tests
Simon Pilgrim [Sun, 11 Oct 2015 18:33:48 +0000 (18:33 +0000)]
[X86] Completed SHL cost model tests

As discussed in D8690.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249990 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Remove special validation for INT immediate operand from AsmParser. Instead...
Craig Topper [Sun, 11 Oct 2015 18:27:24 +0000 (18:27 +0000)]
[X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.

This also fixes a bug where negative immediates below -128 were not being reported as errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249989 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Renamed SHL cost model tests
Simon Pilgrim [Sun, 11 Oct 2015 17:34:32 +0000 (17:34 +0000)]
[X86] Renamed SHL cost model tests

Matches naming conventions for ASHR/LSHR cost tests

As discussed in D8690.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249984 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Added LSHR cost model tests
Simon Pilgrim [Sun, 11 Oct 2015 17:29:26 +0000 (17:29 +0000)]
[X86] Added LSHR cost model tests

There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing.

As discussed in D8690.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249983 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Added ASHR cost model tests
Simon Pilgrim [Sun, 11 Oct 2015 17:08:05 +0000 (17:08 +0000)]
[X86] Added ASHR cost model tests

There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing.

As discussed in D8690.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TableGen] Add a space between type and '*' in front of a variable name in output...
Craig Topper [Sun, 11 Oct 2015 16:59:29 +0000 (16:59 +0000)]
[TableGen] Add a space between type and '*' in front of a variable name in output file. While there replace type with 'auto' since there's a cast on the right side of the assignment. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249980 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Simplify immediate range checking code.
Craig Topper [Sun, 11 Oct 2015 16:38:14 +0000 (16:38 +0000)]
[X86] Simplify immediate range checking code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249979 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Tidyup FMINNUM/FMAXNUM constant folding
Simon Pilgrim [Sun, 11 Oct 2015 16:02:28 +0000 (16:02 +0000)]
[DAGCombiner] Tidyup FMINNUM/FMAXNUM constant folding

Enable constant folding for vector splats as well as scalars.

Enable constant canonicalization for all scalar and vector constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249978 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine][X86][XOP] Combine XOP integer vector comparisons to native IR
Simon Pilgrim [Sun, 11 Oct 2015 14:38:34 +0000 (14:38 +0000)]
[InstCombine][X86][XOP] Combine XOP integer vector comparisons to native IR

We now have lowering support for XOP PCOM/PCOMU instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249977 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][XOP] Added support for the lowering of 128-bit vector integer comparisons to...
Simon Pilgrim [Sun, 11 Oct 2015 14:15:17 +0000 (14:15 +0000)]
[X86][XOP] Added support for the lowering of 128-bit vector integer comparisons to XOP PCOM/PCOMU instructions.

The XOP vector integer comparisons can deal with all signed/unsigned comparison cases directly and can be easily commuted as well (D7646).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249976 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ProfileData] Test commit for slingn
Nathan Slingerland [Sun, 11 Oct 2015 13:30:56 +0000 (13:30 +0000)]
[ProfileData] Test commit for slingn

This is a test of the LLVM commit system. In the event of a real commit there would be some useful code changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Vector signed/unsigned integer compare tests.
Simon Pilgrim [Sat, 10 Oct 2015 22:21:05 +0000 (22:21 +0000)]
[X86][SSE] Vector signed/unsigned integer compare tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249954 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange isUIntN/isIntN calls with constant N to use the template version. NFC
Craig Topper [Sat, 10 Oct 2015 20:17:07 +0000 (20:17 +0000)]
Change isUIntN/isIntN calls with constant N to use the template version. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249952 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoIn isUIntN, make sure N is less than 64 before using in a shift to avoid undefined...
Craig Topper [Sat, 10 Oct 2015 18:54:26 +0000 (18:54 +0000)]
In isUIntN, make sure N is less than 64 before using in a shift to avoid undefined behavior. Also change it to use the same formula as the template version which I think results in less math in compiled code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249951 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix PR25101 - Handle anonymous functions without VST entries
Teresa Johnson [Sat, 10 Oct 2015 14:18:36 +0000 (14:18 +0000)]
Fix PR25101 - Handle anonymous functions without VST entries

The change to use the VST function entries for lazy deserialization did
not handle the case of anonymous functions without aliases. In that case
we must fall back to scanning the function blocks as there is no VST

Reviewers: dexonsmith, joker.eph, davidxl

Subscribers: tstellarAMD, llvm-commits

Differential Revision: http://reviews.llvm.org/D13596

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249947 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs
Jonas Paulsson [Sat, 10 Oct 2015 07:20:23 +0000 (07:20 +0000)]
[SystemZ] CodeGen/SystemZ/asm-18.ll run with -verify-machineinstrs

Relates to the fixes of r249811.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249946 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Fixes in the backend I/R.
Jonas Paulsson [Sat, 10 Oct 2015 07:14:24 +0000 (07:14 +0000)]
[SystemZ] Fixes in the backend I/R.

STX -> 2 * STD: The first STD should not have the kill flag set for the address.

BRC -> BRCT conversion: Don't forget to remove the CC<use,kill> operand.

Needed to make SystemZ/asm-17.ll pass with -verify-machineinstrs, which
now runs with this flag.

Reviewed by Ulrich Weigand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249945 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IndVars] Use `auto`; NFC
Sanjoy Das [Sat, 10 Oct 2015 06:33:33 +0000 (06:33 +0000)]
[IndVars] Use `auto`; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249944 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse range-based for loops. NFC
Craig Topper [Sat, 10 Oct 2015 05:38:14 +0000 (05:38 +0000)]
Use range-based for loops. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249943 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RuntimeDyld] Fix performance problem in resolveRelocations with many sections
Keno Fischer [Sat, 10 Oct 2015 05:37:02 +0000 (05:37 +0000)]
[RuntimeDyld] Fix performance problem in resolveRelocations with many sections

Rather than just iterating over all sections and checking whether we have relocations for them, iterate over the relocation map instead. This showed up heavily in an artificial julia benchmark that does lots of compilation. On that particular benchmark, this patch gives
~15% performance improvements. As far as I can tell the primary reason why the original
loop was so expensive is that Relocations[i] actually constructs a relocationList (allocating memory & doing lots of other unnecessary computing) if none is found.

Reviewers: lhames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D13545

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249942 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse range-based for loops. NFC.
Craig Topper [Sat, 10 Oct 2015 05:25:06 +0000 (05:25 +0000)]
Use range-based for loops. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249941 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse emplace_back instead of a constructor call and push_back. NFC
Craig Topper [Sat, 10 Oct 2015 05:25:02 +0000 (05:25 +0000)]
Use emplace_back instead of a constructor call and push_back. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249940 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSuppress LLVM::tools/llvm-symbolizer/coff-dwarf.test for mingw, for now.
NAKAMURA Takumi [Sat, 10 Oct 2015 02:57:02 +0000 (02:57 +0000)]
Suppress LLVM::tools/llvm-symbolizer/coff-dwarf.test for mingw, for now.

FIXME: Improve llvm-symbolizer, or rename the feature "system-windows".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249937 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] document more trophies
Kostya Serebryany [Sat, 10 Oct 2015 02:14:18 +0000 (02:14 +0000)]
[libFuzzer] document more trophies

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249933 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove llvm-objdump malformed Mach-O tests to X86 test directory.
Kevin Enderby [Sat, 10 Oct 2015 01:06:20 +0000 (01:06 +0000)]
Move llvm-objdump malformed Mach-O tests to X86 test directory.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249927 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAnalysis: Remove implicit ilist iterator conversions
Duncan P. N. Exon Smith [Sat, 10 Oct 2015 00:53:03 +0000 (00:53 +0000)]
Analysis: Remove implicit ilist iterator conversions

Remove implicit ilist iterator conversions from LLVMAnalysis.

I came across something really scary in `llvm::isKnownNotFullPoison()`
which relied on `Instruction::getNextNode()` being completely broken
(not surprising, but scary nevertheless).  This function is documented
(and coded to) return `nullptr` when it gets to the sentinel, but with
an `ilist_half_node` as a sentinel, the sentinel check looks into some
other memory and we don't recognize we've hit the end.

Rooting out these scary cases is the reason I'm removing the implicit
conversions before doing anything else with `ilist`; I'm not at all
surprised that clients rely on badness.

I found another scary case -- this time, not relying on badness, just
bad (but I guess getting lucky so far) -- in
`ObjectSizeOffsetEvaluator::compute_()`.  Here, we save out the
insertion point, do some things, and then restore it.  Previously, we
let the iterator auto-convert to `Instruction*`, and then set it back
using the `Instruction*` version:

    Instruction *PrevInsertPoint = Builder.GetInsertPoint();

    /* Logic that may change insert point */

    if (PrevInsertPoint)

The check for `PrevInsertPoint` doesn't protect correctly against bad
accesses.  If the insertion point has been set to the end of a basic
block (i.e., `SetInsertPoint(SomeBB)`), then `GetInsertPoint()` returns
an iterator pointing at the list sentinel.  The version of
`SetInsertPoint()` that's getting called will then call
`PrevInsertPoint->getParent()`, which explodes horribly.  The only
reason this hasn't blown up is that it's fairly unlikely the builder is
adding to the end of the block; usually, we're adding instructions
somewhere before the terminator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249925 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-rtdyld] Use range-based loop. NFC.
Davide Italiano [Sat, 10 Oct 2015 00:45:24 +0000 (00:45 +0000)]
[llvm-rtdyld] Use range-based loop. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMC: Remove implicit ilist iterator conversions, NFC
Duncan P. N. Exon Smith [Sat, 10 Oct 2015 00:13:11 +0000 (00:13 +0000)]
MC: Remove implicit ilist iterator conversions, NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249922 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a bugs in the Mach-O disassembler when disassembling from a
Kevin Enderby [Sat, 10 Oct 2015 00:05:01 +0000 (00:05 +0000)]
Fix a bugs in the Mach-O disassembler when disassembling from a
malformed Mach-O file that caused a crash.  This was because of an
assert where the code was incorrectly attempting to parse relocation
entries off of the sections and the filetype was not an MH_OBJECT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249921 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Remove more dead code
David Majnemer [Sat, 10 Oct 2015 00:04:29 +0000 (00:04 +0000)]
[WinEH] Remove more dead code

wineh-parent is dead, so is ValueOrMBB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249920 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Delete the old landingpad implementation of Windows EH
Reid Kleckner [Fri, 9 Oct 2015 23:34:53 +0000 (23:34 +0000)]
[WinEH] Delete the old landingpad implementation of Windows EH

The new implementation works at least as well as the old implementation

Also delete the associated preparation tests. They don't exercise
interesting corner cases of the new implementation. All the codegen
tests of the EH tables have already been ported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249918 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SEH] Update SEH codegen tests to use the new IR
Reid Kleckner [Fri, 9 Oct 2015 23:05:54 +0000 (23:05 +0000)]
[SEH] Update SEH codegen tests to use the new IR

Also Fix a buglet where SEH tables had ranges that spanned funclets.

The remaining tests using the old landingpad IR are preparation tests,
and will be deleted along with the old preparation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249917 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCodeGen: Remove implicit ilist iterator conversions, NFC
Duncan P. N. Exon Smith [Fri, 9 Oct 2015 22:56:24 +0000 (22:56 +0000)]
CodeGen: Remove implicit ilist iterator conversions, NFC

Finish removing implicit ilist iterator conversions from LLVMCodeGen.
I'm sure there are lots more of these in lib/CodeGen/*/.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249915 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Parallel make breaks on native tablegen
Chris Bieneman [Fri, 9 Oct 2015 22:26:04 +0000 (22:26 +0000)]
[CMake] Parallel make breaks on native tablegen

Patch by Alex Wang

This patch resolves a parallelization issue that occurs when native tablegen targets are built at the same time. They both try to build libSupport and clobber each other causing the builds to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249911 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Insert the catchpad return before CSR restoration
David Majnemer [Fri, 9 Oct 2015 22:18:45 +0000 (22:18 +0000)]
[WinEH] Insert the catchpad return before CSR restoration

x64 catchpads use rax to inform the unwinder where control should go
next.  However, we must initialize rax before the epilogue sequence so
as to not perturb the unwinder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249910 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix use of uninitialized bool, found by ubsan in portion of
Richard Smith [Fri, 9 Oct 2015 22:09:56 +0000 (22:09 +0000)]
Fix use of uninitialized bool, found by ubsan in portion of
test/tools/llvm-objdump/malformed-machos.test added in r249845.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249909 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix assert when emitting llvm.pow.f86.
James Y Knight [Fri, 9 Oct 2015 21:36:19 +0000 (21:36 +0000)]
Fix assert when emitting llvm.pow.f86.

This occurred due to introducing the invalid i64 type after type
legalization had already finished, in an attempt to workaround bitcast
f64 -> v2i32 not doing constant folding.

The *right* thing is to actually fix bitcast, but that has other
complications. So, for now, just get rid of the broken workaround, and
check in a test-case showing that it doesn't crash, with TODOs for
emitting proper code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249908 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove unused function in sample profile writer API - NFC.
Diego Novillo [Fri, 9 Oct 2015 21:33:13 +0000 (21:33 +0000)]
Remove unused function in sample profile writer API - NFC.

These functions are not needed and are getting in the way of changes
for implementing a table of contents for the binary format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249907 91177308-0d34-0410-b5e6-96231b3b80d8