7 years ago[ADT] Apply a large hammer to StringRef functions: attribute always_inline.
Chandler Carruth [Thu, 10 Sep 2015 08:29:35 +0000 (08:29 +0000)]
[ADT] Apply a large hammer to StringRef functions: attribute always_inline.

The logic of this follows something Howard does in libc++ and something
I discussed with Chris eons ago -- for a lot of functions, there is
really no benefit to preserving "debug information" by leaving the
out-of-line even in debug builds. This is especially true as we now do
a very good job of preserving most debug information even in the face of
inlining. There are a bunch of methods in StringRef that we are paying
a completely unacceptable amount for with every debug build of every
LLVM developer.

Some day, we should fix Clang/LLVM so that developers can reasonable
use a default of something other than '-O0' and not waste their lives
waiting on *completely* unoptimized code to execute. We should have
a default that doesn't impede debugging while providing at least
plausable performance.

But today is not that day.

So today, I'm applying always_inline to the functions that are really
hurting the critical path for stuff like 'check_llvm'. I'm being very
cautious here, but there are a few other APIs that we really should do
this for as a matter of pragmatism. Hopefully we can rip this out some

With this change, TripleTest.Normalization runtime decreases by over
10%, and the total 'check-llvm' time on my 48-core box goes from 38s to
just under 37s.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247253 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Support] Fix the always_inline attribute macro to not include the
Chandler Carruth [Thu, 10 Sep 2015 08:29:30 +0000 (08:29 +0000)]
[Support] Fix the always_inline attribute macro to not include the
'inline' specifier. That specifier may or may not be valid for a given
function, or it may be required for correct linkage even when the
compiler doesn't support the always_inline attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247252 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Micro-optimize the Triple constructor by doing a single split and
Chandler Carruth [Thu, 10 Sep 2015 07:51:43 +0000 (07:51 +0000)]
[ADT] Micro-optimize the Triple constructor by doing a single split and
re-using the resulting components rather than repeatedly splitting and
re-splitting to compute each component as part of the initializer list.

This is more work on PR23676. Sadly, it doesn't help much. It removes
the constructor from my profile, but doesn't make a sufficient dent in
the total time. But it should play together nicely with subsequent

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247250 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Fix a confusing interface spec and some annoying peculiarities
Chandler Carruth [Thu, 10 Sep 2015 07:51:37 +0000 (07:51 +0000)]
[ADT] Fix a confusing interface spec and some annoying peculiarities
with the StringRef::split method when used with a MaxSplit argument
other than '-1' (which nobody really does today, but which should
actually work).

The spec claimed both to split up to MaxSplit times, but also to append
<= MaxSplit strings to the vector. One of these doesn't make sense.
Given the name "MaxSplit", let's go with it being a max over how many
*splits* occur, which means the max on how many strings get appended is
MaxSplit+1. I'm not actually sure the implementation correctly provided
this logic either, as it used a really opaque loop structure.

The implementation was also playing weird games with nullptr in the data
field to try to rely on a totally opaque hidden property of the split
method that returns a pair. Nasty IMO.

Replace all of this with what is (IMO) simpler code that doesn't use the
pair returning split method, and instead just finds each separator and
appends directly. I think this is a lot easier to read, and it most
definitely matches the spec. Added some tests that exercise the corner
cases around StringRef() and StringRef("") that all now pass.

I'll start using this in code in the next commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247249 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGlobalsAAResult(&&): Move every members.
NAKAMURA Takumi [Thu, 10 Sep 2015 07:16:42 +0000 (07:16 +0000)]
GlobalsAAResult(&&): Move every members.

Or, one of MSVC builders failed with unexpected behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247247 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded isUndef() interface for SDNode
Elena Demikhovsky [Thu, 10 Sep 2015 06:33:13 +0000 (06:33 +0000)]
Added isUndef() interface for SDNode

Differential Revision: http://reviews.llvm.org/D12720

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247246 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Switch a bunch of places in LLVM that were doing single-character
Chandler Carruth [Thu, 10 Sep 2015 06:12:31 +0000 (06:12 +0000)]
[ADT] Switch a bunch of places in LLVM that were doing single-character
splits to actually use the single character split routine which does
less work, and in a debug build is *substantially* faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247245 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ADT] Add a single-character version of the small vector split routine
Chandler Carruth [Thu, 10 Sep 2015 06:07:03 +0000 (06:07 +0000)]
[ADT] Add a single-character version of the small vector split routine
on StringRef. Finding and splitting on a single character is
substantially faster than doing it on even a single character StringRef
-- we immediately get to a *very* tuned memchr call this way.

Even nicer, we get to this even in a debug build, shaving 18% off the
runtime of TripleTest.Normalization, helping PR23676 some more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247244 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a way to skip the Go bindings tests even when Go is configured in
Chandler Carruth [Thu, 10 Sep 2015 05:47:43 +0000 (05:47 +0000)]
Add a way to skip the Go bindings tests even when Go is configured in

The Go bindings tests in an unoptimized build take over 30 seconds for
me, making it the slowest test in 'check-llvm' by a factor of two.

I've only rigged this up fully to the CMake build. If someone is
interested in rigging it up to the autoconf build, they're welcome to do

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247243 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ScalarEvolution] Fix PR24757.
Sanjoy Das [Thu, 10 Sep 2015 05:27:38 +0000 (05:27 +0000)]
[ScalarEvolution] Fix PR24757.

PR24757 was caused by some incorect math in
`ScalarEvolution::HowFarToZero` -- the smallest unsigned solution for X

  2^N * A = 2^N * X

is not necessarily A.

Reviewers: atrick, majnemer, meheff

Subscribers: llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D12721

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247242 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LPM] Simplify this code and fix a compile error for compilers that
Chandler Carruth [Thu, 10 Sep 2015 04:22:36 +0000 (04:22 +0000)]
[LPM] Simplify this code and fix a compile error for compilers that
don't correctly implement the scoping rules of C++11 range based for
loops. This kind of aliasing isn't a good idea anyways (and wasn't
really intended).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247241 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LPM] Use a map from analysis ID to immutable passes in the legacy pass
Chandler Carruth [Thu, 10 Sep 2015 02:31:42 +0000 (02:31 +0000)]
[LPM] Use a map from analysis ID to immutable passes in the legacy pass
manager to avoid a slow linear scan of every immutable pass and on every
attempt to find an analysis pass.

This speeds up 'check-llvm' on an unoptimized build for me by 15%, YMMV.
It should also help (a tiny bit) other folks that are really
bottlenecked on repeated runs of tiny pass pipelines across small IR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247240 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEnable the shrink wrapping optimization for PPC64.
Kit Barton [Thu, 10 Sep 2015 01:55:44 +0000 (01:55 +0000)]
Enable the shrink wrapping optimization for PPC64.

The changes in this patch are as follows:
  1. Modify the emitPrologue and emitEpilogue methods to work properly when the prologue and epilogue blocks are not the first/last blocks in the function
  2. Fix a bug in PPCEarlyReturn optimization caused by an empty entry block in the function
  3. Override the runShrinkWrap PredicateFtor (defined in TargetMachine) to check whether shrink wrapping should run:
      Shrink wrapping will run on PPC64 (Little Endian and Big Endian) unless -enable-shrink-wrap=false is specified on command line

A new test case, ppc-shrink-wrapping.ll was created based on the existing shrink wrapping tests for x86, arm, and arm64.

Phabricator review: http://reviews.llvm.org/D11817

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247237 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Match FI+offset in STNP addressing mode.
Ahmed Bougacha [Thu, 10 Sep 2015 01:54:43 +0000 (01:54 +0000)]
[AArch64] Match FI+offset in STNP addressing mode.

First, we need to teach isFrameOffsetLegal about STNP.
It already knew about the STP/LDP variants, but those were probably
never exercised, because it's only the load/store optimizer that
generates STP/LDP, and the only user of the method is frame lowering,
which runs earlier.
The STP/LDP cases were wrong: they didn't take into account the fact
that they return two results, not one, so the immediate offset will be
the 4th operand, not the 3rd.

Follow-up to r247234.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247236 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MC] Convert all the remaining tests from macho-dump to llvm-readobj.
Davide Italiano [Thu, 10 Sep 2015 01:50:00 +0000 (01:50 +0000)]
[MC] Convert all the remaining tests from macho-dump to llvm-readobj.

This sort-of deprecates macho-dump. It may take still a little while
to garbage collect it, but at least there's no real usage of it in
the tree anymore. New tests should always rely on llvm-readobj or

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247235 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Match base+offset in STNP addressing mode.
Ahmed Bougacha [Thu, 10 Sep 2015 01:48:29 +0000 (01:48 +0000)]
[AArch64] Match base+offset in STNP addressing mode.

Followup to r247231.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247234 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMakes EmitRecord() accepting ArrayRef and raw array (NFC)
Mehdi Amini [Thu, 10 Sep 2015 01:45:55 +0000 (01:45 +0000)]
Makes EmitRecord() accepting ArrayRef and raw array (NFC)

After r247186, a vector is no longer needed as the push_front for
the code is removed.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247232 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Support selecting STNP.
Ahmed Bougacha [Thu, 10 Sep 2015 01:42:28 +0000 (01:42 +0000)]
[AArch64] Support selecting STNP.

We could go through the load/store optimizer and match STNP where
we would have matched a nontemporal-annotated STP, but that's not
reliable enough, as an opportunistic optimization.
Insetad, we can guarantee emitting STNP, by matching them at ISel.
Since there are no single-input nontemporal stores, we have to
resort to some high-bits-extracting trickery to generate an STNP
from a plain store.

Also, we need to support another, LDP/STP-specific addressing mode,
base + signed scaled 7-bit immediate offset.
For now, only match the base. Let's make it smart separately.

Part of PR24086.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247231 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix more cases of losing exec operands
Matt Arsenault [Thu, 10 Sep 2015 01:23:28 +0000 (01:23 +0000)]
AMDGPU/SI: Fix more cases of losing exec operands

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247230 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix creating v_mov_b32s without exec uses
Matt Arsenault [Thu, 10 Sep 2015 01:06:06 +0000 (01:06 +0000)]
AMDGPU/SI: Fix creating v_mov_b32s without exec uses

This will be caught by existing tests with a
verifier check to be added in a future commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247229 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"
Hans Wennborg [Thu, 10 Sep 2015 00:57:26 +0000 (00:57 +0000)]
Revert r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes"

This caused build breakges, e.g.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247226 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Make x86 nontemporal store patfrags generic. NFC.
Ahmed Bougacha [Thu, 10 Sep 2015 00:53:15 +0000 (00:53 +0000)]
[CodeGen] Make x86 nontemporal store patfrags generic. NFC.

To be used by other targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247225 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Minor refactor to use shared implementation [NFC]
Philip Reames [Thu, 10 Sep 2015 00:44:10 +0000 (00:44 +0000)]
[RewriteStatepointsForGC] Minor refactor to use shared implementation [NFC]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247223 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Strengthen a confusingly weak assertion [NFC]
Philip Reames [Thu, 10 Sep 2015 00:32:56 +0000 (00:32 +0000)]
[RewriteStatepointsForGC] Strengthen a confusingly weak assertion [NFC]

The assertion was weaker than it should be and gave the impression we're growing the number of base defining values being considered during the fixed point interation.  That's not true.  The tighter form of the assert is useful documentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247221 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] One last bit of naming [NFCI]
Philip Reames [Thu, 10 Sep 2015 00:27:50 +0000 (00:27 +0000)]
[RewriteStatepointsForGC] One last bit of naming [NFCI]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247220 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Add codegen support for cleanuppad and cleanupret
Reid Kleckner [Thu, 10 Sep 2015 00:25:23 +0000 (00:25 +0000)]
[WinEH] Add codegen support for cleanuppad and cleanupret

All of the complexity is in cleanupret, and it mostly follows the same
codepaths as catchret, except it doesn't take a return value in RAX.

This small example now compiles and executes successfully on win32:
  extern "C" int printf(const char *, ...) noexcept;
  struct Dtor {
    ~Dtor() { printf("~Dtor\n"); }
  void has_cleanup() {
    Dtor o;
    throw 42;
  int main() {
    try {
    } catch (int) {
      printf("caught it\n");

Don't try to put the cleanup in the same function as the catch, or Bad
Things will happen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247219 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Further style/naming fixup [NFCI]
Philip Reames [Thu, 10 Sep 2015 00:22:49 +0000 (00:22 +0000)]
[RewriteStatepointsForGC] Further style/naming fixup [NFCI]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247217 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Clang-tidy misc-use-override warnings, other minor fixes
Hans Wennborg [Thu, 10 Sep 2015 00:12:56 +0000 (00:12 +0000)]
Fix Clang-tidy misc-use-override warnings, other minor fixes

Patch by Eugene Zelenko!

Differential Revision: http://reviews.llvm.org/D12740

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247216 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)
Mehdi Amini [Thu, 10 Sep 2015 00:05:09 +0000 (00:05 +0000)]
Bitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)

This reapply commit r247178 after post-commit review from D.Blaikie
in a way that makes it compatible with the existing API.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247215 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd makeArrayRef() overload for ArrayRef input (no-op/identity) NFC
Mehdi Amini [Thu, 10 Sep 2015 00:05:04 +0000 (00:05 +0000)]
Add makeArrayRef() overload for ArrayRef input (no-op/identity) NFC

The purpose is to allow templated wrapper to work with either
ArrayRef or any convertible operation:

template<typename Container>
void wrapper(const Container &Arr) {

with Container being a std::vector, a SmallVector, or an ArrayRef.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247214 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] More naming cleanup [NFCI]
Philip Reames [Thu, 10 Sep 2015 00:01:53 +0000 (00:01 +0000)]
[RewriteStatepointsForGC] More naming cleanup [NFCI]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247213 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Code cleanup [NFC]
Philip Reames [Wed, 9 Sep 2015 23:57:18 +0000 (23:57 +0000)]
[RewriteStatepointsForGC] Code cleanup [NFC]

Factor out common code related to naming values, fix a small style issue.  More to follow in separate changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247211 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Extend base pointer inference to handle insertelement
Philip Reames [Wed, 9 Sep 2015 23:40:12 +0000 (23:40 +0000)]
[RewriteStatepointsForGC] Extend base pointer inference to handle insertelement

This change is simply enhancing the existing inference algorithm to handle insertelement instructions by conservatively inserting a new instruction to propagate the vector of associated base pointers. In the process, I'm ripping out the peephole optimizations which mostly helped cover the fact this hadn't been done.

Note that most of the newly inserted nodes will be nearly immediately removed by the post insertion optimization pass introduced in 246718. Arguably, we should be trying harder to avoid the malloc traffic here, but I'd rather get the code correct, then worry about compile time.

Unlike previous extensions of the algorithm to handle more case, I discovered the existing code was causing miscompiles in some cases. In particular, we had an implicit assumption that the peephole covered *all* insert element instructions, so if we had a value directly based on a insert element the peephole didn't cover, we proceeded as if it were a base anyways. Not good. I believe we had the same issue with shufflevector which is why I adjusted the predicate for them as well.

Differential Revision: http://reviews.llvm.org/D12583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247210 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RewriteStatepointsForGC] Make base pointer inference deterministic
Philip Reames [Wed, 9 Sep 2015 23:26:08 +0000 (23:26 +0000)]
[RewriteStatepointsForGC] Make base pointer inference deterministic

Previously, the base pointer algorithm wasn't deterministic. The core fixed point was (of course), but we were inserting new nodes and optimizing them in an order which was unspecified and variable. We'd somewhat hacked around this for testing by sorting by value name, but that doesn't solve the general determinism problem.

Instead, we can use the order of traversal over the def/use graph to give us a single consistent ordering. Today, this is a DFS order, but the exact order doesn't mater provided it's deterministic for a given input.

(Q: It is safe to rely on a deterministic order of operands right?)

Note that this only fixes the determinism within a single inference step. The inference step is currently invoked many times in a non-deterministic order. That's a future change in the sequence. :)

Differential Revision: http://reviews.llvm.org/D12640

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247208 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerBitSets: Fix non-determinism bug.
Peter Collingbourne [Wed, 9 Sep 2015 22:30:32 +0000 (22:30 +0000)]
LowerBitSets: Fix non-determinism bug.

Visit disjoint sets in a deterministic order based on the maximum BitSetNM
index, otherwise the order in which we visit them will depend on pointer
comparisons. This was being exposed by MSan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247201 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SEH] Emit 32-bit SEH tables for the new EH IR
Reid Kleckner [Wed, 9 Sep 2015 21:10:03 +0000 (21:10 +0000)]
[SEH] Emit 32-bit SEH tables for the new EH IR

The 32-bit tables don't actually contain PC range data, so emitting them
is incredibly simple.

The 64-bit tables, on the other hand, use the same table for state
numbering as well as label ranges. This makes things more difficult, so
it will be implemented later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247192 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Update target datalayout strings.
Dan Gohman [Wed, 9 Sep 2015 20:54:31 +0000 (20:54 +0000)]
[WebAssembly] Update target datalayout strings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247187 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange EmitRecordWithAbbrevImpl to take Optional record code. NFC.
Teresa Johnson [Wed, 9 Sep 2015 20:53:31 +0000 (20:53 +0000)]
Change EmitRecordWithAbbrevImpl to take Optional record code. NFC.

This change enables EmitRecord to pass the supplied record Code to
EmitRecordWithAbbrevImpl, rather than insert it into the Vals array.
It is an enabler for changing EmitRecord to take an ArrayRef<uintty> instead
of a SmallVectorImpl<uintty>&

Patch suggested by Duncan P. N. Exon Smith, modified by myself a bit to get
correct assertion checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247186 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoScalarEvolution assume hanging bugfix
Piotr Padlewski [Wed, 9 Sep 2015 20:47:30 +0000 (20:47 +0000)]
ScalarEvolution assume hanging bugfix


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247184 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Bitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector...
Mehdi Amini [Wed, 9 Sep 2015 20:35:15 +0000 (20:35 +0000)]
Revert "Bitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)"

This reverts commit r247178.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247182 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert trunc(lshr (sext A), Cst) to ashr A, Cst
David Majnemer [Wed, 9 Sep 2015 20:20:08 +0000 (20:20 +0000)]
Revert trunc(lshr (sext A), Cst) to ashr A, Cst

This reverts commit r246997, it introduced a regression (PR24763).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247180 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)
Mehdi Amini [Wed, 9 Sep 2015 20:08:39 +0000 (20:08 +0000)]
Bitcode Writer: EmitRecordWith* takes an ArrayRef instead of a SmallVector (NFC)

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247178 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "AVX512: Implemented encoding and intrinsics for vextracti64x4 ,vextracti64x...
Renato Golin [Wed, 9 Sep 2015 19:44:40 +0000 (19:44 +0000)]
Revert "AVX512: Implemented encoding and intrinsics for   vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."

This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247177 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoallow unpredictable metadata on switch statements
Sanjay Patel [Wed, 9 Sep 2015 18:38:30 +0000 (18:38 +0000)]
allow unpredictable metadata on switch statements

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247174 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSave LaneMask with livein registers
Matthias Braun [Wed, 9 Sep 2015 18:08:03 +0000 (18:08 +0000)]
Save LaneMask with livein registers

With subregister liveness enabled we can detect the case where only
parts of a register are live in, this is expressed as a 32bit lanemask.
The current code only keeps registers in the live-in list and therefore
enumerated all subregisters affected by the lanemask. This turned out to
be too conservative as the subregister may also cover additional parts
of the lanemask which are not live. Expressing a given lanemask by
enumerating a minimum set of subregisters is computationally expensive
so the best solution is to simply change the live-in list to store the
lanemasks as well. This will reduce memory usage for targets using
subregister liveness and slightly increase it for other targets

Differential Revision: http://reviews.llvm.org/D12442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247171 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVirtRegMap: Improve addMBBLiveIns() using SlotIndex::MBBIndexIterator; NFC
Matthias Braun [Wed, 9 Sep 2015 18:07:54 +0000 (18:07 +0000)]
VirtRegMap: Improve addMBBLiveIns() using SlotIndex::MBBIndexIterator; NFC

Now that we have an explicit iterator over the idx2MBBMap in SlotIndices
we can use the fact that segments and the idx2MBBMap is sorted by
SlotIndex position so can advance both simultaneously instead of
starting from the beginning for each segment.

This complicates the code for the subregister case somewhat but should
be more efficient and has the advantage that we get the final lanemask
for each block immediately which will be important for a subsequent

Removes the now unused SlotIndexes::findMBBLiveIns function.

Differential Revision: http://reviews.llvm.org/D12443

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247170 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
Chandler Carruth [Wed, 9 Sep 2015 17:55:00 +0000 (17:55 +0000)]
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.

This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:

- FunctionAAResults is a type-erasing alias analysis results aggregation
  interface to walk a single query across a range of results from
  different alias analyses. Currently this is function-specific as we
  always assume that aliasing queries are *within* a function.

- AAResultBase is a CRTP utility providing stub implementations of
  various parts of the alias analysis result concept, notably in several
  cases in terms of other more general parts of the interface. This can
  be used to implement only a narrow part of the interface rather than
  the entire interface. This isn't really ideal, this logic should be
  hoisted into FunctionAAResults as currently it will cause
  a significant amount of redundant work, but it faithfully models the
  behavior of the prior infrastructure.

- All the alias analysis passes are ported to be wrapper passes for the
  legacy PM and new-style analysis passes for the new PM with a shared
  result object. In some cases (most notably CFL), this is an extremely
  naive approach that we should revisit when we can specialize for the
  new pass manager.

- BasicAA has been restructured to reflect that it is much more
  fundamentally a function analysis because it uses dominator trees and
  loop info that need to be constructed for each function.

All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.

The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.

This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.

Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.

One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.

Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.

Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.

Differential Revision: http://reviews.llvm.org/D12080

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247167 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineVerifier: Check that SlotIndex MBBIndexList is sorted.
Matthias Braun [Wed, 9 Sep 2015 17:49:46 +0000 (17:49 +0000)]
MachineVerifier: Check that SlotIndex MBBIndexList is sorted.

This introduces a check that the MBBIndexList is sorted as proposed in
http://reviews.llvm.org/D12443 but split up into a separate commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247166 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Extract full 64-bit subregister and use subregs
Matt Arsenault [Wed, 9 Sep 2015 17:03:29 +0000 (17:03 +0000)]
AMDGPU: Extract full 64-bit subregister and use subregs

Instead of extracting both 32-bit components from the 128-bit
register. This produces fewer copies and is easier for
the copy peephole optimizer to understand and see the actual uses
as extracts from a reg_sequence.

This avoids needing to handle subregister composing in the
PeepholeOptimizer's ValueTracker for this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247162 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Remove unused multiclass argument
Matt Arsenault [Wed, 9 Sep 2015 17:03:18 +0000 (17:03 +0000)]
AMDGPU: Remove unused multiclass argument

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247161 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agollvm-config: Add --build-system option
Tom Stellard [Wed, 9 Sep 2015 16:39:30 +0000 (16:39 +0000)]
llvm-config: Add --build-system option

This can be used for distinguishing between cmake and autoconf builds.
Users may need this in order to handle inconsistencies between the
outputs of the two build systems.

Reviewers: echristo, chandlerc, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11838

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247159 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Implement calls with void return types.
Dan Gohman [Wed, 9 Sep 2015 16:13:47 +0000 (16:13 +0000)]
[WebAssembly] Implement calls with void return types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247158 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fold operands through REG_SEQUENCE instructions
Tom Stellard [Wed, 9 Sep 2015 15:43:26 +0000 (15:43 +0000)]
AMDGPU/SI: Fold operands through REG_SEQUENCE instructions

This helps mostly when we use add instructions for address calculations
that contain immediates.

Reviewers: arsenm

Subscribers: arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247157 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CostModel][AArch64] Remove amortization factor for some of the vector select instruc...
Silviu Baranga [Wed, 9 Sep 2015 15:35:02 +0000 (15:35 +0000)]
[CostModel][AArch64] Remove amortization factor for some of the vector select instructions

We are not scalarizing the wide selects in codegen for i16 and i32 and
therefore we can remove the amortization factor. We still have issues
with i64 vectors in codegen though.

Reviewers: mcrosier

Subscribers: mcrosier, aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D12724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247156 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodon't repeat function names in comments; NFC
Sanjay Patel [Wed, 9 Sep 2015 15:24:36 +0000 (15:24 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247154 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Tidy up some unneeded newline characters.
Dan Gohman [Wed, 9 Sep 2015 15:13:36 +0000 (15:13 +0000)]
[WebAssembly] Tidy up some unneeded newline characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247152 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Flag recursive cmake invocations for cross-compile
Joseph Tremoulet [Wed, 9 Sep 2015 14:57:06 +0000 (14:57 +0000)]
[CMake] Flag recursive cmake invocations for cross-compile

Cross-compilation uses recursive cmake invocations to build native host
tools.  These recursive invocations only forward a fixed set of
variables/options, since the native environment is generally the default.
This change adds -DLLVM_TARGET_IS_CROSSCOMPILE_HOST=TRUE to the recursive
cmake invocations, so that cmake files can distinguish these recursive
invocations from top-level ones, which can explain why expected options
are unset.

LLILC will use this to avoid trying to generate its build rules in the
crosscompile native host target (where it is not needed), which would fail
if attempted because LLILC requires a cmake variable passed on the command
line, which is not forwarded in the recursive invocation.

Reviewers: rnk, beanz

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12679

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247151 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofunction names start with a lower case letter; NFC
Sanjay Patel [Wed, 9 Sep 2015 14:54:29 +0000 (14:54 +0000)]
function names start with a lower case letter; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247150 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX512: Implemented encoding and intrinsics for
Igor Breger [Wed, 9 Sep 2015 14:35:09 +0000 (14:35 +0000)]
AVX512: Implemented encoding and intrinsics for
  vextracti64x4 ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247149 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agodon't repeat function names in comments; NFC
Sanjay Patel [Wed, 9 Sep 2015 14:34:26 +0000 (14:34 +0000)]
don't repeat function names in comments; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247148 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instr...
Zoran Jovanovic [Wed, 9 Sep 2015 13:55:45 +0000 (13:55 +0000)]
[mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions
Differential Revision: http://reviews.llvm.org/D11178

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247146 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix PR 24633 - Handle undef values when parsing standalone constants.
Alex Lorenz [Wed, 9 Sep 2015 13:44:33 +0000 (13:44 +0000)]
Fix PR 24633 - Handle undef values when parsing standalone constants.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247145 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename ExitCount to BackedgeTakenCount, because that's what it is.
James Molloy [Wed, 9 Sep 2015 12:51:10 +0000 (12:51 +0000)]
Rename ExitCount to BackedgeTakenCount, because that's what it is.

We called a variable ExitCount, stored the backedge count in it, then redefined it to be the exit count again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247140 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDelay predication of stores until near the end of vector code generation
James Molloy [Wed, 9 Sep 2015 12:51:06 +0000 (12:51 +0000)]
Delay predication of stores until near the end of vector code generation

Predicating stores requires creating extra blocks. It's much cleaner if we do this in one pass instead of mutating the CFG while writing vector instructions.

Besides which we can make use of helper functions to update domtree for us, reducing the work we need to do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247139 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Alexandros Lamprineas [Wed, 9 Sep 2015 11:20:48 +0000 (11:20 +0000)]
LLVM does not distinguish Cortex-M4 from Cortex-M4F neither Cortex-R5 from R5F.
Removed "cortex-r5f" and "cortex-m4f" from Target Parser, sinced they are
unknown cpu names for llvm and clang. Also updated default FPUs for R5 and M4

Differential Revision: http://reviews.llvm.org/D12692

Change-Id: Ib81c7216521a361d8ee1296e4b6a2aa00bd479c5

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247136 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix vector splitting for extract_vector_elt and vector elements of <8-bits.
Daniel Sanders [Wed, 9 Sep 2015 09:53:20 +0000 (09:53 +0000)]
Fix vector splitting for extract_vector_elt and vector elements of <8-bits.

One of the vector splitting paths for extract_vector_elt tries to lower:
    define i1 @via_stack_bug(i8 signext %idx) {
      %1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
      ret i1 %1
    define i1 @via_stack_bug(i8 signext %idx) {
      %base = alloca <2 x i1>
      store <2 x i1> <i1 false, i1 true>, <2 x i1>* %base
      %2 = getelementptr <2 x i1>, <2 x i1>* %base, i32 %idx
      %3 = load i1, i1* %2
      ret i1 %3
However, the elements of <2 x i1> are not byte-addressible. The result of this
is that the getelementptr expands to '%base + %idx * (1 / 8)' which simplifies
to '%base + %idx * 0', and then simply '%base' causing all values of %idx to
extract element zero.

This commit fixes this by promoting the vector elements of <8-bits to i8 before
splitting the vector.

This fixes a number of test failures in pocl.

Reviewers: pekka.jaaskelainen

Subscribers: pekka.jaaskelainen, llvm-commits

Differential Revision: http://reviews.llvm.org/D12591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247128 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a typo I spotted when hacking on SROA. Somewhat alarming that
Chandler Carruth [Wed, 9 Sep 2015 09:46:16 +0000 (09:46 +0000)]
Fix a typo I spotted when hacking on SROA. Somewhat alarming that
nothing broke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247127 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][microMIPS] Implement CACHEE and PREFE instructions
Zoran Jovanovic [Wed, 9 Sep 2015 09:10:46 +0000 (09:10 +0000)]
[mips][microMIPS] Implement CACHEE and PREFE instructions
Differential Revision: http://reviews.llvm.org/D11628

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247125 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix not encoding src2 of VOP3b instructions
Matt Arsenault [Wed, 9 Sep 2015 08:39:49 +0000 (08:39 +0000)]
AMDGPU: Fix not encoding src2 of VOP3b instructions

Broken by r247074. Should include an assembler test,
but the assembler is currently broken for VOP3b apparently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247123 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IRCE] Add INITIALIZE_PASS_DEPENDENCY invocations.
Sanjoy Das [Wed, 9 Sep 2015 03:47:18 +0000 (03:47 +0000)]

IRCE was just using INITIALIZE_PASS(), which is incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247122 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.
Lang Hames [Wed, 9 Sep 2015 03:14:29 +0000 (03:14 +0000)]
[RuntimeDyld] Add support for MachO x86_64 SUBTRACTOR relocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247119 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Fix lowering of calls with more than one argument.
Dan Gohman [Wed, 9 Sep 2015 01:52:45 +0000 (01:52 +0000)]
[WebAssembly] Fix lowering of calls with more than one argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247118 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSelectionDAG: Support Expand of f16 extloads
Matt Arsenault [Wed, 9 Sep 2015 01:12:27 +0000 (01:12 +0000)]
SelectionDAG: Support Expand of f16 extloads

Currently this hits an assert that extload should
always be supported, which assumes integer extloads.

This moves a hack out of SI's argument lowering and
is covered by existing tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247113 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg
Dan Gohman [Wed, 9 Sep 2015 00:52:47 +0000 (00:52 +0000)]
[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247110 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typos / grammar
Matt Arsenault [Wed, 9 Sep 2015 00:38:33 +0000 (00:38 +0000)]
Fix typos / grammar

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247109 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"
Duncan P. N. Exon Smith [Wed, 9 Sep 2015 00:37:52 +0000 (00:37 +0000)]
Revert "Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC"

This reverts commit r247107.  Turns out clang calls these functions
directly, and `ArrayRef<T>` doesn't have a working implicit conversion
from `SmallVector<T>`.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247108 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC
Duncan P. N. Exon Smith [Wed, 9 Sep 2015 00:34:25 +0000 (00:34 +0000)]
Bitcode: ArrayRef-ize EmitRecordWithAbbrev(), NFC

Change `EmitRecordWithAbbrev()` and friends to take an `ArrayRef<T>`
instead of requiring a `SmallVectorImpl<T>`.  No functionality change

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247107 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[llvm-readobj] MachO -- dump LinkerOptions load command.
Davide Italiano [Wed, 9 Sep 2015 00:21:18 +0000 (00:21 +0000)]
[llvm-readobj] MachO -- dump LinkerOptions load command.

Example output:

Linker Options {
  Size: 32
  Count: 2
  Strings [
    Value: -framework
    Value: Cocoa

There were only two tests using this -- so I converted them as part of
this commit rather than separately.

Differential Revision:  http://reviews.llvm.org/D12702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247106 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Avoid creating MBBs for LLVM BBs that cannot contain code
Reid Kleckner [Tue, 8 Sep 2015 23:28:38 +0000 (23:28 +0000)]
[WinEH] Avoid creating MBBs for LLVM BBs that cannot contain code

Typically these are catchpads, which hold data used to decide whether to
catch the exception or continue unwinding. We also shouldn't create MBBs
for catchendpads, cleanupendpads, or terminatepads, since no real code
can live in them.

This fixes a problem where MI passes (like the register allocator) would
try to put code into catchpad blocks, which are not executed by the
runtime. In the new world, blocks ending in invokes now have many
possible successors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247102 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-apply r247080 with order of evaluation fix.
Peter Collingbourne [Tue, 8 Sep 2015 22:49:35 +0000 (22:49 +0000)]
Re-apply r247080 with order of evaluation fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247095 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Emit prologues and epilogues for funclets
Reid Kleckner [Tue, 8 Sep 2015 22:44:41 +0000 (22:44 +0000)]
[WinEH] Emit prologues and epilogues for funclets

32-bit funclets have short prologues that allocate enough stack for the
largest call in the whole function. The runtime saves CSRs for the
funclet. It doesn't restore CSRs after we finally transfer control back
to the parent funciton via a CATCHRET, but that's a separate issue.
32-bit funclets also have to adjust the incoming EBP value, which is
what llvm.x86.seh.recoverframe does in the old model.

64-bit funclets need to spill CSRs as normal. For simplicity, this just
spills the same set of CSRs as the parent function, rather than trying
to compute different CSR sets for the parent function and each funclet.
64-bit funclets also allocate enough stack space for the largest
outgoing call frame, like 32-bit.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247092 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r247080, "LowerBitSets: Extend pass to support functions as bitset
Peter Collingbourne [Tue, 8 Sep 2015 22:33:23 +0000 (22:33 +0000)]
Revert r247080, "LowerBitSets: Extend pass to support functions as bitset
members." as it causes test failures on a number of bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247088 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Bitcode] Add compatibility tests for new instructions
Vedant Kumar [Tue, 8 Sep 2015 22:33:23 +0000 (22:33 +0000)]
[Bitcode] Add compatibility tests for new instructions

Adds basic compatibility tests for the following instructions:

  catchpad, catchendpad, cleanuppad, cleanupendpad, terminatepad,
  cleanupret, catchret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247087 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Fix typo in catchret example
Vedant Kumar [Tue, 8 Sep 2015 22:28:38 +0000 (22:28 +0000)]
[docs] Fix typo in catchret example

An example usage of catchret omitted the "to" in "to label" in

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the PPC CTR Loop pass to look for calls to the intrinsics that
Eric Christopher [Tue, 8 Sep 2015 22:14:58 +0000 (22:14 +0000)]
Fix the PPC CTR Loop pass to look for calls to the intrinsics that
read CTR and count them as reading the CTR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247083 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLowerBitSets: Extend pass to support functions as bitset members.
Peter Collingbourne [Tue, 8 Sep 2015 21:57:45 +0000 (21:57 +0000)]
LowerBitSets: Extend pass to support functions as bitset members.

This change extends the bitset lowering pass to support bitsets that may
contain either functions or global variables. A function bitset is lowered to
a jump table that is laid out before one of the functions in the bitset.

Also add support for non-string bitset identifier names. This allows for
distinct metadata nodes to stand in for names with internal linkage,
as done in D11857.

Differential Revision: http://reviews.llvm.org/D11856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247080 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer]Add a test for defeating a hash sum.
Ivan Krasin [Tue, 8 Sep 2015 21:22:52 +0000 (21:22 +0000)]
[libFuzzer]Add a test for defeating a hash sum.

Add a test for a data followed by 4-byte hash value.
I use a slightly modified Jenkins hash function,
as described in https://en.wikipedia.org/wiki/Jenkins_hash_function

The modification is to ensure that hash(zeros) != 0.

Reviewers: kcc

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247076 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix input vcc operand for VOP2b instructions
Matt Arsenault [Tue, 8 Sep 2015 21:15:00 +0000 (21:15 +0000)]
AMDGPU/SI: Fix input vcc operand for VOP2b instructions

Adds vcc to output string input for e32. Allows option
of using e64 encoding with assembler.

Also fixes these instructions not implicitly reading exec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247074 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[NVPTX] Added run NVVMReflect pass to NVPTX back-end.
Artem Belevich [Tue, 8 Sep 2015 21:04:55 +0000 (21:04 +0000)]
[NVPTX] Added run NVVMReflect pass to NVPTX back-end.

The pass is needed to remove __nvvm_reflect calls when we link in
libdevice bitcode that comes with CUDA.

Differential Revision: http://reviews.llvm.org/D11663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247072 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix comments and RUN line in x86-64 stdarg test leftover from last commit
Derek Schuff [Tue, 8 Sep 2015 20:58:41 +0000 (20:58 +0000)]
Fix comments and RUN line in x86-64 stdarg test leftover from last commit

From http://reviews.llvm.org/D12346

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247070 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes a bug in how struct va_list is initialized in x32
Derek Schuff [Tue, 8 Sep 2015 20:51:31 +0000 (20:51 +0000)]
x32. Fixes a bug in how struct va_list is initialized in x32

Summary: This patch modifies X86TargetLowering::LowerVASTART so that
struct va_list is initialized with 32 bit pointers in x32. It also
includes tests that call @llvm.va_start() for x32.

Patch by João Porto

Subscribers: llvm-commits, hjl.tools
Differential Revision: http://reviews.llvm.org/D12346

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247069 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] remove a piece of stale code
Kostya Serebryany [Tue, 8 Sep 2015 20:40:10 +0000 (20:40 +0000)]
[libFuzzer] remove a piece of stale code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247067 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[libFuzzer] be more robust when dealing with files on disk (e.g. don't crash if a...
Kostya Serebryany [Tue, 8 Sep 2015 20:36:33 +0000 (20:36 +0000)]
[libFuzzer] be more robust when dealing with files on disk (e.g. don't crash if a file was there but disappeared)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247066 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WebAssembly] Support running without a register allocator in the default CodeGen...
Dan Gohman [Tue, 8 Sep 2015 20:36:33 +0000 (20:36 +0000)]
[WebAssembly] Support running without a register allocator in the default CodeGen passes

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247065 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd const overload of findRegisterUseOperand
Matt Arsenault [Tue, 8 Sep 2015 20:21:29 +0000 (20:21 +0000)]
Add const overload of findRegisterUseOperand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247063 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[docs] Update documentation for the landingpad instruction
Vedant Kumar [Tue, 8 Sep 2015 20:16:35 +0000 (20:16 +0000)]
[docs] Update documentation for the landingpad instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247062 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agorefactor matches for De Morgan's Laws; NFCI
Sanjay Patel [Tue, 8 Sep 2015 20:14:13 +0000 (20:14 +0000)]
refactor matches for De Morgan's Laws; NFCI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247061 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Mark s_barrier as a high latency instruction
Matt Arsenault [Tue, 8 Sep 2015 19:54:32 +0000 (19:54 +0000)]
AMDGPU: Mark s_barrier as a high latency instruction

These were marked as WriteSALU, which is low latency.
I'm guessing at the value to use, but it should probably
be considered the highest latency instruction.

I'm not sure this has any actual effect since hasSideEffects
probably is preventing any moving of these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247060 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Fix s_barrier flags
Matt Arsenault [Tue, 8 Sep 2015 19:54:25 +0000 (19:54 +0000)]
AMDGPU: Fix s_barrier flags

This should be convergent. This is not a
barrier in the isBarrier sense, nor

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247059 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agox32. Fixes a bug in i8mem_NOREX declaration.
Derek Schuff [Tue, 8 Sep 2015 19:47:15 +0000 (19:47 +0000)]
x32. Fixes a bug in i8mem_NOREX declaration.

The old implementation assumed LP64 which is broken for x32.  Specifically, the
MOVE8rm_NOREX and MOVE8mr_NOREX, when selected, would cause a 'Cannot emit
physreg copy instruction' error message to be reported.

This patch also enable the h-register*ll tests for x32.

Differential Revision: http://reviews.llvm.org/D12336

Patch by João Porto

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247058 91177308-0d34-0410-b5e6-96231b3b80d8