oota-llvm.git
7 years agoTest commit.
Cong Hou [Wed, 15 Jul 2015 17:58:15 +0000 (17:58 +0000)]
Test commit.

This is a test commit (one blank line deleted).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242308 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDelete declared but not implemented functions.
Rafael Espindola [Wed, 15 Jul 2015 17:19:39 +0000 (17:19 +0000)]
Delete declared but not implemented functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242304 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebug Info: Add basic support for external types references.
Adrian Prantl [Wed, 15 Jul 2015 17:01:41 +0000 (17:01 +0000)]
Debug Info: Add basic support for external types references.
This is a necessary prerequisite for bootstrapping the emission
of debug info inside modules.

- Adds a FlagExternalTypeRef to DICompositeType.
  External types must have a unique identifier.
- External type references are emitted using a forward declaration
  with a DW_AT_signature([DW_FORM_ref_sig8]) based on the UID.

http://reviews.llvm.org/D9612

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242302 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd missing load/store flags to thumb2 instructions.
Pete Cooper [Wed, 15 Jul 2015 16:36:38 +0000 (16:36 +0000)]
Add missing load/store flags to thumb2 instructions.

These were the cause of a verifier error when building 7zip with
-verify-machineinstrs.  Running 'make check' with the verifier
triggered the same error on the test here so i've updated the test
to run the verifier on one of its runs instead of adding a new one.

While looking at this code, there was a stale comment that these
instructions were only used for disassembly.  This probably used to
be the case, but they are now used in the 'ARM load / store optimization pass' too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242300 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PPC64LE] Fix vec_sld semantics for little endian
Bill Schmidt [Wed, 15 Jul 2015 15:45:30 +0000 (15:45 +0000)]
[PPC64LE] Fix vec_sld semantics for little endian

The vec_sld interface provides access to the vsldoi instruction.
Unlike most of the vec_* interfaces, we do not attempt to change the
generated code for vec_sld based on the endian mode.  It is too
difficult to correctly infer the desired semantics because of
different element types, and the corrected instruction sequence is
expensive, involving loading a permute control vector and performing a
generalized permute.

For GCC, this was implemented as "Don't touch the vec_sld"
implementation.  When it came time for the LLVM implementation, I did
the same thing.  However, this was hasty and incorrect.  In LLVM's
version of altivec.h, vec_sld was previously defined in terms of the
vec_perm interface.  Because vec_perm semantics are adjusted for
little endian, this means that leaving vec_sld untouched causes it to
generate something different for LE than for BE.  Not good.

This back-end patch accompanies the changes to altivec.h that change
vec_sld's behavior for little endian.  Those changes mean that we see
slightly different code in the back end when trying to recognize a
VSLDOI instruction in isVSLDOIShuffleMask.  In particular, a
ShuffleKind of 1 (where the two inputs are identical) must now be
treated the same way as a ShuffleKind of 2 (little endian with
different inputs) when little endian mode is in force.  This is
because ShuffleKind of 1 is defined using big-endian numbering.

This has a ripple effect on LowerBUILD_VECTOR, where we create our own
internal VSLDOI instructions.  Because these are a ShuffleKind of 1,
they will now have their shift amounts subtracted from 16 when
recognizing the shuffle mask.  To avoid problems we have to subtract
them from 16 again before creating the VSLDOI instructions.

There are a couple of other uses of BuildVSLDOI, but these do not need
to be modified because the shift amount is 8, which is unchanged when
subtracted from 16.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242296 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLook through PHIs to find additional register sources
Bruno Cardoso Lopes [Wed, 15 Jul 2015 15:35:23 +0000 (15:35 +0000)]
Look through PHIs to find additional register sources

- Teaches the ValueTracker in the PeepholeOptimizer to look through PHI
instructions.
- Add findNextSourceAndRewritePHI method to lookup into multiple sources
returnted by the ValueTracker and rewrite PHIs with new sources.

With these changes we can find more register sources and rewrite more
copies to allow coaslescing of bitcast instructions. Hence, we eliminate
unnecessary VR64 <-> GR64 copies in x86, but it could be extended to
other archs by marking "isBitcast" on target specific instructions. The
x86 example follows:

A:
  psllq %mm1, %mm0
  movd  %mm0, %r9
  jmp C

B:
  por %mm1, %mm0
  movd  %mm0, %r9
  jmp C

C:
  movd  %r9, %mm0
  pshufw  $238, %mm0, %mm0

Becomes:

A:
  psllq %mm1, %mm0
  jmp C

B:
  por %mm1, %mm0
  jmp C

C:
  pshufw  $238, %mm0, %mm0

Differential Revision: http://reviews.llvm.org/D11197

rdar://problem/20404526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242295 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor optimizeUncoalescable logic
Bruno Cardoso Lopes [Wed, 15 Jul 2015 15:35:09 +0000 (15:35 +0000)]
Refactor optimizeUncoalescable logic

- Create a new CopyRewriter for Uncoalescable copy-like instructions
- Change the ValueTracker to return a ValueTrackerResult

This makes optimizeUncoalescable looks more like optimizeCoalescable and
use the CopyRewritter infrastructure.

This is also the preparation for looking up into PHI nodes in the
ValueTracker.

Differential Revision: http://reviews.llvm.org/D11195

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242294 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoExpose setPersonalityFn to Go
Andrew Wilkins [Wed, 15 Jul 2015 13:03:08 +0000 (13:03 +0000)]
Expose setPersonalityFn to Go

Summary:
Add Value.SetPersonality to the Go bindings. The Go
bindings' Builder.CreateLandingPad has been updated,
removing the obsolete personality argument.

Background

The personality attribute was removed from LandingPadInst
in r239940, and llvm::Function::setPersonalityFn introduced.

There was no corresponding change to either the C API or
Go bindings. The Go bindings were broken until r239940, but
that change was just to ignore the personality argument.
This broke llgo.

Reviewers: majnemer, pcc

Subscribers: deadalnix, llvm-commits, axw

Differential Revision: http://reviews.llvm.org/D11116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242289 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PPC] Disassemble little endian ppc instructions in the right byte order
Benjamin Kramer [Wed, 15 Jul 2015 12:56:19 +0000 (12:56 +0000)]
[PPC] Disassemble little endian ppc instructions in the right byte order

PR24122. The test is simply a byte swapped version of ppc64-encoding.txt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242288 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago-Added API for retrieving the default FPU of a CPU from TargetParser.
Alexandros Lamprineas [Wed, 15 Jul 2015 10:46:21 +0000 (10:46 +0000)]
-Added API for retrieving the default FPU of a CPU from TargetParser.
-Implemented as a table lookup.

Change-Id: Iaad0eaf4b29b06827e6700269496dc1ba20e9018
Phabricator: http://reviews.llvm.org/D11100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242284 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/AA] Fix *numerous* serious bugs in GlobalsModRef found by
Chandler Carruth [Wed, 15 Jul 2015 08:53:29 +0000 (08:53 +0000)]
[PM/AA] Fix *numerous* serious bugs in GlobalsModRef found by
inspection.

While we want to handle calls specially in this code because they should
have been modeled by the call graph analysis that precedes it, we should
*not* be re-implementing the predicates for whether an instruction reads
or writes memory. Those are well defined already. Notably, at least the
following issues seem to be clearly missed before:
- Ordered atomic loads can "write" to memory by causing writes from other
  threads to become visible. Similarly for ordered atomic stores.
- AtomicRMW instructions quite obviously both read and write to memory.
- AtomicCmpXchg instructions also read and write to memory.
- Fences read and write to memory.
- Invokes of intrinsics or memory allocation functions.

I don't have any test cases, and I suspect this has never really come up
in the real world. But there is no reason why it wouldn't, and it makes
the code simpler to do this the right way.

While here, I've tried to make the loops significantly simpler as well
and added helpful comments as to what is going on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242281 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)
Alexey Bataev [Wed, 15 Jul 2015 08:39:35 +0000 (08:39 +0000)]
[SDAG] Optimize unordered comparison in soft-float mode (patch by Anton Nadolskiy)

Current implementation handles unordered comparison poorly in soft-float mode.
Consider (a ULE b) which is a <= b. It is lowered to (ledf2(a, b) <= 0 || unorddf2(a, b) != 0) (in general). We can do better job by lowering it to (__gtdf2(a, b) <= 0).
Such replacement is true for other CMP's (ult, ugt, uge). In general, we just call same function as for ordered case but negate comparison against zero.
Differential Revision: http://reviews.llvm.org/D10804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242280 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Use the MachineCombiner to reassociate fadd/fmul
Hal Finkel [Wed, 15 Jul 2015 08:23:05 +0000 (08:23 +0000)]
[PowerPC] Use the MachineCombiner to reassociate fadd/fmul

This is a direct port of the code from the X86 backend (r239486/r240361), which
uses the MachineCombiner to reassociate (floating-point) adds/muls to increase
ILP, to the PowerPC backend. The rationale is the same.

There is a lot of copy-and-paste here between the X86 code and the PowerPC
code, and we should extract at least some of this into CodeGen somewhere.
However, I don't want to do that until this code is enhanced to handle FMAs as
well. After that, we'll be in a better position to extract the common parts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242279 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Extend physical register live range in PPCVSXFMAMutate
Hal Finkel [Wed, 15 Jul 2015 08:23:03 +0000 (08:23 +0000)]
[PowerPC] Extend physical register live range in PPCVSXFMAMutate

If the source of the copy that defines the addend is a physical register, then
its existing live range may not extend to the FMA being mutated. Make sure we
extend the live range of the register to meet the FMA because it will become
its operand in this case.

I don't have an independent test case, but it will be exposed by change to be
committed shortly enabling the use of the machine combiner to do fadd/fmul
reassociation, and will be covered by one of the associated regression tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242278 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MachineCombiner] Work with itineraries
Hal Finkel [Wed, 15 Jul 2015 08:22:23 +0000 (08:22 +0000)]
[MachineCombiner] Work with itineraries

MachineCombiner predicated its use of scheduling-based metrics on
hasInstrSchedModel(), but useful conclusions can be drawn from pipeline
itineraries as well. Almost all of the logic (except for resource tracking in
preservesResourceLen) can be used if we have an itinerary, so enable it in that
case as well.

This will be used by the PowerPC backend in an upcoming commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242277 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Fix problems in decoding generic MSR instructions
Petr Pavlu [Wed, 15 Jul 2015 08:10:30 +0000 (08:10 +0000)]
[AArch64] Fix problems in decoding generic MSR instructions

Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/AA] Cleanup some loops to be range-based. NFC.
Chandler Carruth [Wed, 15 Jul 2015 08:09:23 +0000 (08:09 +0000)]
[PM/AA] Cleanup some loops to be range-based. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242275 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TableGen] Improve decoding options for non-orthogonal instructions
Petr Pavlu [Wed, 15 Jul 2015 08:04:27 +0000 (08:04 +0000)]
[TableGen] Improve decoding options for non-orthogonal instructions

When FixedLenDecoder matches an input bitpattern of form [01]+ with an
instruction bitpattern of form [01?]+ (where 0/1 are static bits and ? are
mixed/variable bits) it passes the input bitpattern to a specific instruction
decoder method which then makes a final decision whether the bitpattern is a
valid instruction or not. This means the decoder must handle all possible
values of the variable bits which sometimes leads to opcode rewrites in the
decoder method when the instructions are not fully orthogonal.

The patch provides a way for the decoder method to say that when it returns
Fail it does not necessarily mean the bitpattern is invalid, but rather that
the bitpattern is definitely not an instruction that is recognized by the
decoder method. The decoder can then try to match the input bitpattern with
other possible instruction bitpatterns.

For example, this allows to solve a situation on AArch64 where the `MSR
(immediate)` instruction has form:
1101 0101 0000 0??? 0100 ???? ???1 1111
but not all values of the ? bits are allowed. The rejected values should be
handled by the `extended MSR (register)` instruction:
1101 0101 000? ???? ???? ???? ???? ????

The decoder will first try to decode an input bitpattern that matches both
bitpatterns as `MSR (immediate)` but currently this puts the decoder method of
`MSR (immediate)` into a situation when it must be able to decode all possible
values of the ? bits, i.e. it would need to rewrite the instruction to `MSR
(register)` when it is not `MSR (immediate)`.

The patch allows to specify that the decoder method cannot determine if the
instruction is valid for all variable values. The decoder method can simply
return Fail when it knows it is definitely not `MSR (immediate)`. The decoder
will then backtrack the decoding and find that it can match the input
bitpattern with the more generic `MSR (register)` bitpattern too.

Differential Revision: http://reviews.llvm.org/D7174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242274 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SSE] Added i686/SSE2 vector shift tests.
Simon Pilgrim [Wed, 15 Jul 2015 08:04:07 +0000 (08:04 +0000)]
[X86][SSE] Added i686/SSE2 vector shift tests.

We were only testing on x86-64, but we should be ensuring decent code gen of i64 shifts on 32-bit targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242273 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only...
Igor Breger [Wed, 15 Jul 2015 07:08:10 +0000 (07:08 +0000)]
AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present.
Tests added.

Differential Revision: http://reviews.llvm.org/D11122

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242270 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInitial support for writing thin archives.
Rafael Espindola [Wed, 15 Jul 2015 05:47:46 +0000 (05:47 +0000)]
Initial support for writing thin archives.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242269 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTidy-up test case from r242257.
Michael Zolotukhin [Wed, 15 Jul 2015 01:51:51 +0000 (01:51 +0000)]
Tidy-up test case from r242257.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242268 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[vim] Update the syntax to mark REQUIRES lines and not talk about
Chandler Carruth [Wed, 15 Jul 2015 01:48:40 +0000 (01:48 +0000)]
[vim] Update the syntax to mark REQUIRES lines and not talk about
dejagnu.

I wonder if it would be useful to handle FileCheck prefixes specially?
Especially if we could get some error checking. Suggestions welcome.
Patches more welcome as I have no idea what I'm doing with vim
script....

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242267 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[vim] Add the IR's comment prefix to the comments list. This allows vim
Chandler Carruth [Wed, 15 Jul 2015 01:36:50 +0000 (01:36 +0000)]
[vim] Add the IR's comment prefix to the comments list. This allows vim
to intelligently wrap prose written in IR comment blocks. This has
bothered me for roughly ever, and my fellow IRC denziens convinced me to
fix it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242266 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse enum instead of unsigned. NFC.
Pete Cooper [Wed, 15 Jul 2015 01:31:26 +0000 (01:31 +0000)]
Use enum instead of unsigned.  NFC.

The unsigned opcode argument here was the result of BinaryOperator->getOpcode().
That returns a BinaryOps enum which is more accurate than passing around an
unsigned.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242265 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse cast<> instead of dyn_cast to remove llvm_unreachable. NFC.
Pete Cooper [Wed, 15 Jul 2015 01:31:23 +0000 (01:31 +0000)]
Use cast<> instead of dyn_cast to remove llvm_unreachable.  NFC.

This code was checking if we are an ICmpInst or FCmpInst then throwing
unreachable if we are neither.  We must be one or the other, so use a
cast on the FCmpInst case to ensure that we are that case.  Then we can
avoid having an unreachable but still catch an error if we ever had another
subclass of CmpInst.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242264 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse another foreach loop. NFC
Pete Cooper [Wed, 15 Jul 2015 01:31:20 +0000 (01:31 +0000)]
Use another foreach loop.  NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242263 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse getAnyExtOrTrunc helper instead of manually doing ext/trunc check. NFC.
Pete Cooper [Wed, 15 Jul 2015 00:43:57 +0000 (00:43 +0000)]
Use getAnyExtOrTrunc helper instead of manually doing ext/trunc check.  NFC.

The code here was doing exactly what is already in getAnyExtOrTrunc().
Just use that method instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242261 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse getZExtOrTrunc helper instead of manually doing zext/trunc check. NFC.
Pete Cooper [Wed, 15 Jul 2015 00:43:54 +0000 (00:43 +0000)]
Use getZExtOrTrunc helper instead of manually doing zext/trunc check.  NFC.

The code here was doing exactly what is already in getZExtOrTrunc().
Just use that method instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242260 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LoopUnrolling] Handle cast instructions.
Michael Zolotukhin [Wed, 15 Jul 2015 00:19:51 +0000 (00:19 +0000)]
[LoopUnrolling] Handle cast instructions.

During estimation of unrolling effect we should be able to propagate
constants through casts.

Differential Revision: http://reviews.llvm.org/D10207

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242257 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange conditional to assert. NFC.
Pete Cooper [Wed, 15 Jul 2015 00:07:57 +0000 (00:07 +0000)]
Change conditional to assert.  NFC.

This code was breaking from the case statement if the getStoreSizeInBits()
value was not a multiple of 0.  Given that the implementation returns
getStoreSize() * 8, it can only be a multiple of 8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242255 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse getStoreSize() instead of getStoreSizeInBits()/8. NFC.
Pete Cooper [Wed, 15 Jul 2015 00:07:55 +0000 (00:07 +0000)]
Use getStoreSize() instead of getStoreSizeInBits()/8.  NFC.

The calls here were both to getStoreSizeInBits() which multiplies by 8.
We then immediately divided by 8.  Calling getStoreSize() returns the
values we need without the extra arithmetic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242254 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse a range loop.
Rafael Espindola [Tue, 14 Jul 2015 23:51:01 +0000 (23:51 +0000)]
Use a range loop.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242250 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse more foreach loops in SelectionDAG. NFC
Pete Cooper [Tue, 14 Jul 2015 23:43:29 +0000 (23:43 +0000)]
Use more foreach loops in SelectionDAG.  NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242249 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCreate a wrapper pass for BlockFrequencyInfo.
Wei Mi [Tue, 14 Jul 2015 23:40:50 +0000 (23:40 +0000)]
Create a wrapper pass for BlockFrequencyInfo.

This is useful when we want to do block frequency analysis
conditionally (e.g. only in PGO mode) but don't want to add
one more pass dependence.

Patch by congh.
Approved by dexonsmith.
Differential Revision: http://reviews.llvm.org/D11196

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242248 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Sphinx error about duplicate label in CommandLine.rst:1560 and CoverageMappingFor...
Hans Wennborg [Tue, 14 Jul 2015 23:29:53 +0000 (23:29 +0000)]
Fix Sphinx error about duplicate label in CommandLine.rst:1560 and CoverageMappingFormat.rst

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242245 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: fix build breakage.
JF Bastien [Tue, 14 Jul 2015 23:06:07 +0000 (23:06 +0000)]
WebAssembly: fix build breakage.

Summary:
processFunctionBeforeCalleeSavedScan was renamed to determineCalleeSaves and now takes a BitVector parameter as of rL242165, reviewed in http://reviews.llvm.org/D10909

WebAssembly is still marked as experimental and therefore doesn't build by default. It does, however, grep by default! I notice that processFunctionBeforeCalleeSavedScan is still mentioned in a few comments and error messages, which I also fixed.

Reviewers: qcolombet, sunfish

Subscribers: jfb, dsanders, hfinkel, MatzeB, llvm-commits

Differential Revision: http://reviews.llvm.org/D11199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242242 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Support symbolic targets in patchpoints
Hal Finkel [Tue, 14 Jul 2015 22:53:11 +0000 (22:53 +0000)]
[PowerPC] Support symbolic targets in patchpoints

Follow-up r235483, with the corresponding support in PPC. We use a regular call
for symbolic targets (because they're much cheaper than indirect calls).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242239 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReleaseNotes.rst: Bump version to 3.8
Hans Wennborg [Tue, 14 Jul 2015 22:49:27 +0000 (22:49 +0000)]
ReleaseNotes.rst: Bump version to 3.8

The notes for 3.7 are on the 3.7 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242237 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAccept lower case to handle windows error messages.
Rafael Espindola [Tue, 14 Jul 2015 22:42:21 +0000 (22:42 +0000)]
Accept lower case to handle windows error messages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242236 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[InstCombine] Generalize sub of selects optimization to all BinaryOperators
David Majnemer [Tue, 14 Jul 2015 22:39:23 +0000 (22:39 +0000)]
[InstCombine] Generalize sub of selects optimization to all BinaryOperators

This exposes further optimization opportunities if the selects are
correlated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242235 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate the trunk version to 3.8.0svn.
Hans Wennborg [Tue, 14 Jul 2015 22:35:57 +0000 (22:35 +0000)]
Update the trunk version to 3.8.0svn.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242222 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LAA] Turn RuntimePointerChecking into a class, start hiding things, NFC
Adam Nemet [Tue, 14 Jul 2015 22:32:52 +0000 (22:32 +0000)]
[LAA] Turn RuntimePointerChecking into a class, start hiding things, NFC

The goal is to start hiding internal APIs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242220 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LAA] Introduce RuntimePointerChecking::PointerInfo, NFC
Adam Nemet [Tue, 14 Jul 2015 22:32:50 +0000 (22:32 +0000)]
[LAA] Introduce RuntimePointerChecking::PointerInfo, NFC

Turn this structure-of-arrays (i.e. the various pointer attributes) into
array-of-structures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242219 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LAA] Lift RuntimePointerCheck out of LoopAccessInfo, NFC
Adam Nemet [Tue, 14 Jul 2015 22:32:44 +0000 (22:32 +0000)]
[LAA] Lift RuntimePointerCheck out of LoopAccessInfo, NFC

I am planning to add more nested classes inside RuntimePointerCheck so
all these triple-nesting would be hard to follow.

Also rename it to RuntimePointerChecking (i.e. append 'ing').

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242218 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Use the ABI indirect-call protocol for patchpoints
Hal Finkel [Tue, 14 Jul 2015 22:26:06 +0000 (22:26 +0000)]
[PowerPC] Use the ABI indirect-call protocol for patchpoints

We used to take the address specified as the direct target of the patchpoint
and did no TOC-pointer handling.  This, however, as not all that useful,
because MCJIT tends to create a lot of modules, and they have their own TOC
sections. Thus, to call from the generated code to other generated code, you
really need to switch TOC pointers. Make this work as expected, and under
ELFv1, tread the address as the function descriptor address so that the correct
TOC pointer can be loaded.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242217 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for reading members out of thin archives.
Rafael Espindola [Tue, 14 Jul 2015 22:18:43 +0000 (22:18 +0000)]
Add support for reading members out of thin archives.

For now the Archive owns the buffers of the thin archive members.
This makes for a simple API, but all the buffers are destructed
only when the archive is destructed. This should be fine since we
close the files after mmap so we should not hit an open file
limit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242215 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ExecutionEngine] Re-apply r241962 with fixes for ARM.
Lang Hames [Tue, 14 Jul 2015 22:11:10 +0000 (22:11 +0000)]
[ExecutionEngine] Re-apply r241962 with fixes for ARM.

Patch by Pierre-Andre Saulais. Thanks Pierre-Andre!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242213 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd allnodes() iterator range to SelectionDAG. NFC.
Pete Cooper [Tue, 14 Jul 2015 22:10:54 +0000 (22:10 +0000)]
Add allnodes() iterator range to SelectionDAG.  NFC.

SelectionDAG already had begin/end methods for iterating over all
the nodes, but didn't define an iterator_range for us in foreach
loops.

This adds such a method and uses it in some of the eligible places
throughout the backends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242212 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMove SDNode::IROrder in to padding to save space. NFC.
Pete Cooper [Tue, 14 Jul 2015 21:54:55 +0000 (21:54 +0000)]
Move SDNode::IROrder in to padding to save space.  NFC.

There was a 32-bit padding gap between 'unsigned short NumOperands, NumValues;' and 'DebugLoc debugLoc.  Move 'unsigned IROrder' in to that gap.

This trims the size of SDNode's from 76 bytes (really 80 due to alignment) to 72 bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242211 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoConstify parameters in SelectionDAG methods. NFC
Pete Cooper [Tue, 14 Jul 2015 21:54:52 +0000 (21:54 +0000)]
Constify parameters in SelectionDAG methods.  NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242210 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove unnecessary .getNode() in SelectionDAG. NFC.
Pete Cooper [Tue, 14 Jul 2015 21:54:48 +0000 (21:54 +0000)]
Remove unnecessary .getNode() in SelectionDAG.  NFC.

The simplify_type specialisation allows us to cast directly from
SDValue to an SDNode* subclass so we don't need to pass a SDNode*
to cast<>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242209 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse more foreach loops in SelectionDAG. NFC
Pete Cooper [Tue, 14 Jul 2015 21:54:45 +0000 (21:54 +0000)]
Use more foreach loops in SelectionDAG.  NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242208 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Serialization: Serialize the machine basic block live in registers.
Alex Lorenz [Tue, 14 Jul 2015 21:24:41 +0000 (21:24 +0000)]
MIR Serialization: Serialize the machine basic block live in registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242204 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMIR Printer: move the function 'printReg'. NFC.
Alex Lorenz [Tue, 14 Jul 2015 21:18:25 +0000 (21:18 +0000)]
MIR Printer: move the function 'printReg'. NFC.

This commit moves the function 'printReg' towards the start of the file so that
it can be used by the conversion methods in MIRPrinter and not just the printing
methods in MIPrinter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242203 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGVN: use a static array instead of regenerating it each time. NFC.
Tim Northover [Tue, 14 Jul 2015 21:14:58 +0000 (21:14 +0000)]
GVN: use a static array instead of regenerating it each time. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242202 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWebAssembly: add basic int/fp instruction codegen.
JF Bastien [Tue, 14 Jul 2015 21:13:29 +0000 (21:13 +0000)]
WebAssembly: add basic int/fp instruction codegen.

Summary: This patch has the most basic instruction codegen for 32 and 64 bit int/fp.

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11193

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242201 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix NDEBUG build warning
Krzysztof Parzyszek [Tue, 14 Jul 2015 21:03:24 +0000 (21:03 +0000)]
Fix NDEBUG build warning

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242200 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGVN: tolerate an instruction being replaced without existing in the leaderboard
Tim Northover [Tue, 14 Jul 2015 21:03:18 +0000 (21:03 +0000)]
GVN: tolerate an instruction being replaced without existing in the leaderboard

Sometimes an incidentally created instruction can duplicate a Value used
elsewhere. It then often doesn't end up in the leader table. If it's later
removed, we attempt to remove it from the leader table and segfault.

Instead we should just ignore the removal request, which won't cause any
problems. The reverse situation, where the original instruction is replaced by
the new one (which you might think could leave the leader table empty) cannot
occur, because the incidental instruction will never be found in the first
place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242199 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agotest-release.sh: Remove the InstallDir parameter from configure_llvmCore
Hans Wennborg [Tue, 14 Jul 2015 20:15:15 +0000 (20:15 +0000)]
test-release.sh: Remove the InstallDir parameter from configure_llvmCore

After r242187, it's never set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242194 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Windows build: replace __func__ with LLVM_FUNCTION_NAME
Krzysztof Parzyszek [Tue, 14 Jul 2015 20:11:28 +0000 (20:11 +0000)]
Fix Windows build: replace __func__ with LLVM_FUNCTION_NAME

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242192 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MMX] Use the appropriate instructions for GR64 <-> VR64 copies.
Bruno Cardoso Lopes [Tue, 14 Jul 2015 20:09:34 +0000 (20:09 +0000)]
[MMX] Use the appropriate instructions for GR64 <-> VR64 copies.

MOVSDto64rr and MOV64toSDrr are defined to convert between FR64 (%xmm)
<-> GR64 registers, not VR64 (%mm) <-> GR64. This is wrong.

I found this by inspection and could not find a suitable testcase for it
since (1) we don't handle MMX bitcasts in Peephole optimizer as to
generate COPYs that (2) could be expanded back to the appropriate x86
instruction in ExpandPostRA.

Switch to use the appropriate instructions: MMX_MOVD64from64rr and
MMX_MOVD64to64rr here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242191 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation
Hal Finkel [Tue, 14 Jul 2015 20:02:02 +0000 (20:02 +0000)]
[PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation

PowerPC uses itineraries to describe processor pipelines (and dispatch-group
restrictions for P7/P8 cores). Unfortunately, the target-independent
implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that
looks for the largest cycle count in the pipeline for any given instruction.
This, however, yields the wrong answer for the PPC itineraries, because we
don't encode the full pipeline. Because the functional units are fully
pipelined, we only model the initial stages (there are no relevant hazards in
the later stages to model), and so the technique employed by getStageLatency
does not really work. Instead, we should take the maximum output operand
latency, and that's what PPCInstrInfo::getInstrLatency now does.

This caused some test-case churn, including two unfortunate side effects.
First, the new arrangement of copies we get from function parameters now
sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the
test cases), and we have one significant test-suite regression:

SingleSource/Benchmarks/BenchmarkGame/spectral-norm
56.4185% +/- 18.9398%

In this benchmark we have a loop with a vectorized FP divide, and it with the
new scheduling both divides end up in the same dispatch group (which in this
case seems to cause a problem, although why is not exactly clear). The grouping
structure is hard to predict from the bottom of the loop, and there may not be
much we can do to fix this.

Very few other test-suite performance effects were really significant, but
almost all weakly favor this change. However, in light of the issues
highlighted above, I've left the old behavior available via a
command-line flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242188 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix several issues with the test-release.sh script
Dan Liew [Tue, 14 Jul 2015 19:46:19 +0000 (19:46 +0000)]
Fix several issues with the test-release.sh script

* Use the default install prefix (/usr/local) and use DESTDIR instead to
  set a temporary install location for tarballing. This is the correct
  way to package binary releases (otherwise the temporary install path
  ends up in files in the binary release).
* Remove ``-disable-clang`` option. It did not work correctly
  (tarballing assumed phase 3 was run) and when doing a release
  we should always be doing a three-phased build and test.

Note: Technically we should only be using DESTDIR for the third phase
and use --prefix for the first and second phase because we run the built
clang from phase 1 and 2 (and in general an application's behaviour
may depend on the install prefix). However in the case of clang it
seems to not care what the install prefix was so to simplify the script
we use DESTDIR for all three stages.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242187 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Generate instructions for operations on predicate registers
Krzysztof Parzyszek [Tue, 14 Jul 2015 19:30:21 +0000 (19:30 +0000)]
[Hexagon] Generate instructions for operations on predicate registers

Convert logical operations on general-purpose registers to the correspon-
ding operations on predicate registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242186 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CodeGen] Force emission of personality directive if explicitly specified
Keno Fischer [Tue, 14 Jul 2015 19:22:51 +0000 (19:22 +0000)]
[CodeGen] Force emission of personality directive if explicitly specified

Summary:
Before this change, personality directives were not emitted
if there was no invoke left in the function (of course until
recently this also meant that we couldn't know what
the personality actually was). This patch forces personality directives
to still be emitted, unless it is known to be a noop in the absence of
invokes, or the user explicitly specified `nounwind` (and not
`uwtable`) on the function.

Reviewers: majnemer, rnk

Subscribers: rnk, llvm-commits

Differential Revision: http://reviews.llvm.org/D10884

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242185 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd support for on-disk hash table lookup with a known hash, for situations where...
Richard Smith [Tue, 14 Jul 2015 18:40:59 +0000 (18:40 +0000)]
Add support for on-disk hash table lookup with a known hash, for situations where the same key will be looked up in multiple tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242179 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTeach config.guess that MSYS exists.
Yaron Keren [Tue, 14 Jul 2015 18:33:55 +0000 (18:33 +0000)]
Teach config.guess that MSYS exists.

We might not want to upgrade config.guess to the current
version due to the license change from GPL2 to GPL3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242178 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
Matt Arsenault [Tue, 14 Jul 2015 18:20:33 +0000 (18:20 +0000)]
AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)

This can be done only with moves which theoretically
will optimize better later.

Although this transform increases the instruction count,
it should be code size / cycle count neutral in the worst
VALU case. It also seems to slightly improve a couple
of testcases due to other DAG combines this exposes.

This is probably slightly worse for the SALU case, so
it might be better to handle this during moveToVALU,
although then you lose some simplifications like
the load width reducing in the simple testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242177 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Fix read2 merging into a super register.
Matt Arsenault [Tue, 14 Jul 2015 17:57:36 +0000 (17:57 +0000)]
AMDGPU/SI: Fix read2 merging into a super register.

If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242174 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMachineRegisterInfo: Remove UsedPhysReg infrastructure
Matthias Braun [Tue, 14 Jul 2015 17:52:07 +0000 (17:52 +0000)]
MachineRegisterInfo: Remove UsedPhysReg infrastructure

We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional bitset of which ones are used.

Removing it frees us from extra book keeping. This simplifies
VirtRegMap.

Differential Revision: http://reviews.llvm.org/D10911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242173 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAvoid MSVC-incompatible use of init list.
David Blaikie [Tue, 14 Jul 2015 17:40:53 +0000 (17:40 +0000)]
Avoid MSVC-incompatible use of init list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242170 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRAGreedy: Keep track of allocated PhysRegs internally
Matthias Braun [Tue, 14 Jul 2015 17:38:17 +0000 (17:38 +0000)]
RAGreedy: Keep track of allocated PhysRegs internally

Do not use MachineRegisterInfo::setPhysRegUsed()/isPhysRegUsed()
anymore. This bitset changes function-global state and is set by the
VirtRegRewriter anyway.
Simply use a bitvector private to RAGreedy.

Differential Revision: http://reviews.llvm.org/D10910

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242169 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd missing builtins to the PPC back end for ABI compliance (vol. 4)
Nemanja Ivanovic [Tue, 14 Jul 2015 17:25:20 +0000 (17:25 +0000)]
Add missing builtins to the PPC back end for ABI compliance (vol. 4)

This patch corresponds to review:
http://reviews.llvm.org/D11183

Back end portion of the fourth round of additions to altivec.h.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242167 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: add at least one real test for r242123.
Tim Northover [Tue, 14 Jul 2015 17:23:55 +0000 (17:23 +0000)]
ARM: add at least one real test for r242123.

The ones committed were orthogonal to the change and would have passed before
that revision. What it *did* do was prevent an assertion failure when
generating object files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242166 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPrologEpilogInserter: Rewrite API to determine callee save regsiters.
Matthias Braun [Tue, 14 Jul 2015 17:17:13 +0000 (17:17 +0000)]
PrologEpilogInserter: Rewrite API to determine callee save regsiters.

This changes TargetFrameLowering::processFunctionBeforeCalleeSavedScan():

- Rename the function to determineCalleeSaves()
- Pass a bitset of callee saved registers by reference, thus avoiding
  the function-global PhysRegUsed bitset in MachineRegisterInfo.
- Without PhysRegUsed the implementation is fine tuned to not save
  physcial registers which are only read but never modified.

Related to rdar://21539507

Differential Revision: http://reviews.llvm.org/D10909

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242165 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAArch64: add rev64 alias for 64-bit rev instruction.
Tim Northover [Tue, 14 Jul 2015 17:07:29 +0000 (17:07 +0000)]
AArch64: add rev64 alias for 64-bit rev instruction.

It could be useful to assembly programmers and makes the permitted variants a
little more uniform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242164 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Hexagon] Generate "extract" instructions more aggressively
Krzysztof Parzyszek [Tue, 14 Jul 2015 17:07:24 +0000 (17:07 +0000)]
[Hexagon] Generate "extract" instructions more aggressively

Generate extract instructions (via intrinsics) before the DAG combiner
folds shifts into unrecognizable forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242163 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agollvm-ar: Don't try to extract from thin archives.
Rafael Espindola [Tue, 14 Jul 2015 16:55:13 +0000 (16:55 +0000)]
llvm-ar: Don't try to extract from thin archives.

This matches the gnu ar behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242162 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARMAsmParser: Take MCInst param by const-ref
Hans Wennborg [Tue, 14 Jul 2015 16:39:01 +0000 (16:39 +0000)]
ARMAsmParser: Take MCInst param by const-ref

(Broken out from http://reviews.llvm.org/D11167)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242160 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd default value for Args parameter of IRBuilder::CreateCall
David Blaikie [Tue, 14 Jul 2015 16:38:30 +0000 (16:38 +0000)]
Add default value for Args parameter of IRBuilder::CreateCall

Convenient for calls to zero-argument functions.

Patch by servuswiegehtz at yahoo.de

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242159 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSleep for 2.1 seconds to see if that makes the test stable on windows.
Rafael Espindola [Tue, 14 Jul 2015 16:34:23 +0000 (16:34 +0000)]
Sleep for 2.1 seconds to see if that makes the test stable on windows.

Might fix pr24106.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242158 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAllocate the IntervalMap in ELF.h on the heap to work around MSVC alignment bug ...
Hans Wennborg [Tue, 14 Jul 2015 16:27:16 +0000 (16:27 +0000)]
Allocate the IntervalMap in ELF.h on the heap to work around MSVC alignment bug (PR24113)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242157 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agollvm-ar: print an error when the requested member is not found.
Rafael Espindola [Tue, 14 Jul 2015 16:02:40 +0000 (16:02 +0000)]
llvm-ar: print an error when the requested member is not found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242156 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse a range loop. NFC.
Rafael Espindola [Tue, 14 Jul 2015 15:22:42 +0000 (15:22 +0000)]
Use a range loop. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242153 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Fix `llvm-config` to emit the linker flag for the combined shared object...
JF Bastien [Tue, 14 Jul 2015 15:10:34 +0000 (15:10 +0000)]
Revert "Fix `llvm-config` to emit the linker flag for the combined shared object built by autoconfig/make instead of the individual components."

This reverts commit 01446706b4c0a86bb64768f307079cab5c514aa3.

Causes breakage, seems to be related to 'svn' in the file's name:

  CC=gcc CXX=g++ \
  ../llvm/configure \
    --prefix=/usr \
    --sysconfdir=/etc \
    --enable-shared \
    --enable-libffi \
    --enable-targets=all \
    --disable-assertions \
    --with-python=/usr/bin/python2 \
    --enable-optimized

  make REQUIRES_RTTI=1 ENABLE_PIC=1

results:
llvm[2]: Linking Release unit test Support (without symbols)
llvm[2]: ======= Finished Linking Release Unit test Support (without symbols)
make[3]: Entering directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
make[3]: *** No rule to make target '/build/llvm-
svn/src/build/Release/lib/ocaml/libLLVM-3.7.0svn.so', needed by 'build-
deplibs'.  Stop.
make[3]: *** Waiting for unfinished jobs....
llvm[3]: Compiling llvm_ocaml.c for Release build
make[3]: Leaving directory '/build/llvm-svn/src/build/bindings/ocaml/llvm'
/build/llvm-svn/src/llvm/Makefile.rules:880: recipe for target 'all' failed
/build/llvm-svn/src/llvm/Makefile.rules:965: recipe for target 'all' failed

Differential Revision: http://reviews.llvm.org/D10716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242152 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRename a test. NFC.
Rafael Espindola [Tue, 14 Jul 2015 15:06:18 +0000 (15:06 +0000)]
Rename a test. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242151 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCaused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9
Alexandros Lamprineas [Tue, 14 Jul 2015 14:34:06 +0000 (14:34 +0000)]
Caused regressions: compile Release+Asserts failed on clang-native-arm-cortex-a9
Revert "-Added API for retrieving the default FPU of a CPU from TargetParser."

This reverts commit 01199ab0c6ff2d5c4f6b2c05a95ec011e41c4669.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242147 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Tom Stellard [Tue, 14 Jul 2015 14:15:03 +0000 (14:15 +0000)]
AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242146 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to 'int16_t...
Aaron Ballman [Tue, 14 Jul 2015 14:14:00 +0000 (14:14 +0000)]
Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to 'int16_t' and truncation of constant value. NFC intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242145 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago-Added API for retrieving the default FPU of a CPU from TargetParser.
Alexandros Lamprineas [Tue, 14 Jul 2015 13:20:48 +0000 (13:20 +0000)]
-Added API for retrieving the default FPU of a CPU from TargetParser.
-Implemented as a table lookup.

Change-Id: Ibf7217f6bd2769e9c06835a5aede3d072dee6757
Phabricator: http://reviews.llvm.org/D11100

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242141 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Fix li/la differences between IAS and GAS.
Daniel Sanders [Tue, 14 Jul 2015 12:24:22 +0000 (12:24 +0000)]
[mips] Fix li/la differences between IAS and GAS.

Summary:
- Signed 16-bit should have priority over unsigned.
- For la, unsigned 16-bit must use ori+addu rather than directly use ori.
- Correct tests on 32-bit immediates with 64-bit predicates by
  sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000)
  should be true and use addiu.

Also split li/la testing into separate files due to their size.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10967

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242139 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PM/AA] Reformat GlobalsModRef so that subsequent patches I make here
Chandler Carruth [Tue, 14 Jul 2015 08:42:39 +0000 (08:42 +0000)]
[PM/AA] Reformat GlobalsModRef so that subsequent patches I make here
don't continually introduce formatting deltas. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242129 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix comment typo
Petr Pavlu [Tue, 14 Jul 2015 08:00:34 +0000 (08:00 +0000)]
Fix comment typo

Test commit access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242128 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SROA] Don't de-atomic volatile loads and stores
David Majnemer [Tue, 14 Jul 2015 06:19:58 +0000 (06:19 +0000)]
[SROA] Don't de-atomic volatile loads and stores

Volatile loads and stores are made visible in global state regardless of
what memory is involved.  It is not correct to disregard the ordering
and synchronization scope because it is possible to synchronize with
memory operations performed by hardware.

This partially addresses PR23737.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242126 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGenerate correct asm info for mingw and cygwin ARM targets.
Yaron Keren [Tue, 14 Jul 2015 05:51:05 +0000 (05:51 +0000)]
Generate correct asm info for mingw and cygwin ARM targets.

http://reviews.llvm.org/D11075

Patch by Martell Malone
Reviewed by Reid Kleckner

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242123 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[CMake] Unbreak add_llvm_external_project when external projects are specified.
NAKAMURA Takumi [Tue, 14 Jul 2015 05:12:53 +0000 (05:12 +0000)]
[CMake] Unbreak add_llvm_external_project when external projects are specified.

LLVM_EXTERNAL_*_SOURCE_DIR is reset as PATH with set(CACHE PATH).
Then the CACHE PATH variable, LLVM_EXTERNAL_*_SOURCE_DIR, is normalized as
${CMAKE_SOURCE_DIR}/${path_var} if ${path_var} is relative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242120 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPrune trailing whitespaces and CRs.
NAKAMURA Takumi [Tue, 14 Jul 2015 04:03:49 +0000 (04:03 +0000)]
Prune trailing whitespaces and CRs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242117 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoGive an explicit triple to llvm/test/CodeGen/X86/pr13577.ll.
NAKAMURA Takumi [Tue, 14 Jul 2015 03:07:06 +0000 (03:07 +0000)]
Give an explicit triple to llvm/test/CodeGen/X86/pr13577.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242111 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"
Matthias Braun [Tue, 14 Jul 2015 02:09:57 +0000 (02:09 +0000)]
Revert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"

Accidental commit, needs review first.

This reverts commit r242107.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242108 91177308-0d34-0410-b5e6-96231b3b80d8