oota-llvm.git
7 years agoFix the ocaml bindings.
Rafael Espindola [Thu, 7 Aug 2014 14:48:13 +0000 (14:48 +0000)]
Fix the ocaml bindings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215117 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix configure+make build
Rafael Espindola [Thu, 7 Aug 2014 14:38:49 +0000 (14:38 +0000)]
fix configure+make build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215116 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove empty directories.
Rafael Espindola [Thu, 7 Aug 2014 14:25:55 +0000 (14:25 +0000)]
Remove empty directories.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215115 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoNuke the old JIT.
Rafael Espindola [Thu, 7 Aug 2014 14:21:18 +0000 (14:21 +0000)]
Nuke the old JIT.

I am sure we will be finding bits and pieces of dead code for years to
come, but this is a good start.

Thanks to Lang Hames for making MCJIT a good replacement!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215111 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd mfasr and mtasr
Joerg Sonnenberger [Thu, 7 Aug 2014 13:35:34 +0000 (13:35 +0000)]
Add mfasr and mtasr

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215110 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd mfrtcu and mfrtcl instructions
Joerg Sonnenberger [Thu, 7 Aug 2014 13:16:58 +0000 (13:16 +0000)]
Add mfrtcu and mfrtcl instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215109 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSupport mttbl and mttbu mnemonic
Joerg Sonnenberger [Thu, 7 Aug 2014 13:06:23 +0000 (13:06 +0000)]
Support mttbl and mttbu mnemonic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215108 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd RFID instruction.
Joerg Sonnenberger [Thu, 7 Aug 2014 12:39:59 +0000 (12:39 +0000)]
Add RFID instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215105 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix Itineray class of rfi
Joerg Sonnenberger [Thu, 7 Aug 2014 12:35:16 +0000 (12:35 +0000)]
Fix Itineray class of rfi

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215104 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSpell e500 feature in lower case.
Joerg Sonnenberger [Thu, 7 Aug 2014 12:31:28 +0000 (12:31 +0000)]
Spell e500 feature in lower case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215103 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd first bunch of SPE instructions. As they overlap with Altivec, mark
Joerg Sonnenberger [Thu, 7 Aug 2014 12:18:21 +0000 (12:18 +0000)]
Add first bunch of SPE instructions. As they overlap with Altivec, mark
them as parser-only until the disassembler is extended to handle
predicates properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215102 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInsert parens to avoid a warning:
Alexander Kornienko [Thu, 7 Aug 2014 12:09:34 +0000 (12:09 +0000)]
Insert parens to avoid a warning:
  suggest parentheses around arithmetic in operand of '^' [-Wparentheses]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215101 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSilencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted...
Aaron Ballman [Thu, 7 Aug 2014 12:07:33 +0000 (12:07 +0000)]
Silencing an MSVC C4334 warning ('<<' : result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)). No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215100 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Add assembler support for .set msa/nomsa directive.
Daniel Sanders [Thu, 7 Aug 2014 12:03:36 +0000 (12:03 +0000)]
[mips] Add assembler support for .set msa/nomsa directive.

Summary:
These directives are used to toggle whether the assembler accepts MSA-specific instructions or not.

Patch by Matheus Almeida and Toma Tabacu.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215099 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix lld-x86_64-win7 Build #11969
Pavel Chupin [Thu, 7 Aug 2014 11:09:59 +0000 (11:09 +0000)]
Fix lld-x86_64-win7 Build #11969

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215097 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix another miscompile found through fuzz testing the new vector
Chandler Carruth [Thu, 7 Aug 2014 10:37:35 +0000 (10:37 +0000)]
[x86] Fix another miscompile found through fuzz testing the new vector
shuffle lowering.

This is closely related to the previous one. Here we failed to use the
source offset when swapping in the other case -- where we end up
swapping the *final* shuffle. The cause of this bug is a bit different:
I simply wasn't thinking about the fact that this mask is actually
a slice of a wide mask and thus has numbers that need SourceOffset
applied. Simple fix. Would be even more simple with an algorithm-y thing
to use here, but correctness first. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215095 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix another miscompile in the new vector shuffle lowering found
Chandler Carruth [Thu, 7 Aug 2014 10:14:27 +0000 (10:14 +0000)]
[x86] Fix another miscompile in the new vector shuffle lowering found
via the fuzz tester.

Here I missed an offset when round-tripping a value through a shuffle
mask. I got it right 2 lines below. See a problem? I do. ;] I'll
probably be adding a little "swap" algorithm which accepts a range and
two values and swaps those values where they occur in the range. Don't
really have a name for it, let me know if you do.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215094 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix another miscompile in the new vector shuffle lowering found
Chandler Carruth [Thu, 7 Aug 2014 09:45:02 +0000 (09:45 +0000)]
[x86] Fix another miscompile in the new vector shuffle lowering found
through the new fuzzer.

This one is great: bad operator precedence led the modulus to happen at
the wrong point. All the asserts didn't fire because there were usually
the right values past the end of the 4 element region we were looking
at. Probably could have gotten a crash here with ASan + fuzzing, but the
correctness tests pinpointed this really nicely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215092 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x32] Use ebp/esp as frame and stack pointer
Pavel Chupin [Thu, 7 Aug 2014 09:41:19 +0000 (09:41 +0000)]
[x32] Use ebp/esp as frame and stack pointer

Summary:
Since pointers are 32-bit on x32 we can use ebp and esp as frame and stack
pointer. Some operations like PUSH/POP and CFI_INSTRUCTION still
require 64-bit register, so using 64-bit MachineFramePtr where required.

X86_64 NaCl uses 64-bit frame/stack pointers, however it's been found that
both isTarget64BitLP64 and isTarget64BitILP32 are true for NaCl. Addressing
this issue here as well by making isTarget64BitLP64 false.

Also mark hasReservedSpillSlot unreachable on X86. See inlined comments.

Test Plan: Add one new simple test and upgrade 2 existing with x32 target case.

Reviewers: nadav, dschuff

Subscribers: llvm-commits, zinovy.nis

Differential Revision: http://reviews.llvm.org/D4617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215091 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix a miscompile in the new shuffle lowering found through the new
Chandler Carruth [Thu, 7 Aug 2014 08:11:31 +0000 (08:11 +0000)]
[x86] Fix a miscompile in the new shuffle lowering found through the new
fuzz testing.

The function which tested for adjacency did what it said on the tin, but
when I called it, I wanted it to do something more thorough: I wanted to
know if the *pairs* of shuffle elements were adjacent and started at
0 mod 2. In one place I had the decency to try to test for this, but in
the other it was completely skipped, miscompiling this test case. Fix
this by making the helper actually do what I wanted it to do everywhere
I called it (and removing the now redundant code in one place).

I *really* dislike the name "canWidenShuffleElements" for this
predicate. If anyone can come up with a better name, please let me know.
The other name I thought about was "canWidenShuffleMask" but is it
really widening the mask to reduce the number of lanes shuffled? I don't
know. Naming things is hard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215089 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate Tablegen documents given that binary literals are now sized
Pete Cooper [Thu, 7 Aug 2014 05:47:13 +0000 (05:47 +0000)]
Update Tablegen documents given that binary literals are now sized

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215088 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate BitRecTy::convertValue to allow if expressions with bit values on both sides...
Pete Cooper [Thu, 7 Aug 2014 05:47:10 +0000 (05:47 +0000)]
Update BitRecTy::convertValue to allow if expressions with bit values on both sides of the if

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215087 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange the { } expression in tablegen to accept sized binary literals which are not...
Pete Cooper [Thu, 7 Aug 2014 05:47:07 +0000 (05:47 +0000)]
Change the { } expression in tablegen to accept sized binary literals which are not just 0 and 1.

It also allows nested { } expressions, as now that they are sized, we can merge pull bits from the nested value.

In the current behaviour, everything in { } must have been convertible to a single bit.
However, now that binary literals are sized, its useful to be able to initialize a range of bits.

So, for example, its now possible to do

bits<8> x = { 0, 1, { 0b1001 }, 0, 0b0 }

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215086 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange BitsInit to inherit from TypedInit.
Pete Cooper [Thu, 7 Aug 2014 05:47:04 +0000 (05:47 +0000)]
Change BitsInit to inherit from TypedInit.

This is useful in a later patch where binary literals such as 0b000 will become BitsInit values instead of IntInit values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215085 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoChange TableGen so that binary literals such as 0b001 are now sized.
Pete Cooper [Thu, 7 Aug 2014 05:47:00 +0000 (05:47 +0000)]
Change TableGen so that binary literals such as 0b001 are now sized.

Instead of these becoming an integer literal internally, they now become bits<n> values.

Prior to this change, 0b001 was 1 bit long.  This is confusing as clearly the user gave 3 bits.
This new type holds both the literal value and the size, and so can ensure sizes match on initializers.

For example, this used to be legal

bits<1> x = 0b00;

but now it must be written as

bits<2> x = 0b00;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215084 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoTableGen: Change { } to only accept bits<n> entries when n == 1.
Pete Cooper [Thu, 7 Aug 2014 05:46:57 +0000 (05:46 +0000)]
TableGen: Change { } to only accept bits<n> entries when n == 1.

Prior to this change, it was legal to do something like

  bits<2> opc = { 0, 1 };
  bits<2> opc2 = { 1, 0 };
  bits<2> a = { opc, opc2 };

This involved silently dropping bits from opc and opc2 which is very hard to debug.

Now the above test would be an error.  Having tested with an assert, none of LLVM/clang was relying on this behaviour.

Thanks to Adam Nemet for the above test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215083 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a whole bunch of binary literals which were the wrong size. All were being silen...
Pete Cooper [Thu, 7 Aug 2014 05:46:54 +0000 (05:46 +0000)]
Fix a whole bunch of binary literals which were the wrong size.  All were being silently zero extended to the correct width.

The commit after this changes { } and 0bxx literals to be of type bits<n> and not int.  This means we need to write exactly the right number of bits, and not rely on the values being silently zero extended for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215082 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd an option to the shuffle fuzzer that lets you fuzz exclusively
Chandler Carruth [Thu, 7 Aug 2014 04:49:54 +0000 (04:49 +0000)]
Add an option to the shuffle fuzzer that lets you fuzz exclusively
within a single bit-width of vectors. This is particularly useful for
when you know you have bugs in a certain area and want to find simpler
test cases than those produced by an open-ended fuzzing that ends up
legalizing the vector in addition to shuffling it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215056 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUse the minor number for the revision numbers.
Bill Wendling [Thu, 7 Aug 2014 04:21:45 +0000 (04:21 +0000)]
Use the minor number for the revision numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215055 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a vector shuffle fuzzer.
Chandler Carruth [Thu, 7 Aug 2014 04:13:51 +0000 (04:13 +0000)]
Add a vector shuffle fuzzer.

This is a python script which for a given seed generates a random
sequence of random shuffles of a random vector width. It embeds this
into a function and emits a main function which calls the test routine
and checks that the results (where defined) match the obvious results.

I'll be using this to drive out miscompiles from the new vector shuffle
logic now that it is clean of any crashes I can find with llvm-stress.

Note, my python skills are very poor. Sorry if this is terrible code,
and feel free to tell me how I should write this or just patch it as
necessary.

The tests generated try to be very portable and use boring C routines.
It technically will mis-declare the C routines and pass 32-bit integers
to parametrs that expect 64-bit integers. If someone wants to fix this
and has less terrible ideas of how to do it, I'm all ears. Fortunately,
this "just works" for x86. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215054 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Make a test more portable
Justin Bogner [Thu, 7 Aug 2014 03:47:28 +0000 (03:47 +0000)]
DebugInfo: Make a test more portable

mach-o doesn't like sections without segments, and elf is perfectly
happy with commas in section names, so use a Darwin-like section name.

Suggestion by Eric Christopher.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215052 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMC: split Win64EHUnwindEmitter into a shared streamer
Saleem Abdulrasool [Thu, 7 Aug 2014 02:59:41 +0000 (02:59 +0000)]
MC: split Win64EHUnwindEmitter into a shared streamer

This changes Win64EHEmitter into a utility WinEH UnwindEmitter that can be
shared across multiple architectures and a target specific bit which is
overridden (Win64::UnwindEmitter).  This enables sharing the section selection
code across X86 and the intended use in ARM for emitting unwind information for
Windows on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215050 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.
Quentin Colombet [Thu, 7 Aug 2014 00:20:44 +0000 (00:20 +0000)]
[X86][SchedModel] Fixed missing/wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables.

Related to <rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215045 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd the -mcpu= option to llvm-objdump for use with the disassemblers.
Kevin Enderby [Wed, 6 Aug 2014 23:24:41 +0000 (23:24 +0000)]
Add the -mcpu= option to llvm-objdump for use with the disassemblers.
Also make the disassembler created with the Mach-O parser (the -m option)
pick up the Target specific attributes specified with -mattr option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215032 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMC X86: Accept ".att_syntax prefix" and diagnose noprefix
Reid Kleckner [Wed, 6 Aug 2014 23:21:13 +0000 (23:21 +0000)]
MC X86: Accept ".att_syntax prefix" and diagnose noprefix

Fixes PR18916.  I don't think we need to implement support for either
hybrid syntax.  Nobody should write Intel assembly with '%' prefixes on
their registers or AT&T assembly without them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215031 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Reapply "DebugInfo: Ensure that all debug location scope chains from instruct...
David Blaikie [Wed, 6 Aug 2014 22:30:12 +0000 (22:30 +0000)]
Revert "Reapply "DebugInfo: Ensure that all debug location scope chains from instructions within a function, lead to the function itself.""

This reverts commit r214761.

Revert while Reid investigates & provides a reproduction for an
assertion failure for this on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214999 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agofix typo
Sanjay Patel [Wed, 6 Aug 2014 21:08:38 +0000 (21:08 +0000)]
fix typo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214995 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agogetNewMemBuffer memsets the buffer to zeros,
Yaron Keren [Wed, 6 Aug 2014 20:59:09 +0000 (20:59 +0000)]
getNewMemBuffer memsets the buffer to zeros,
the caller don't have to initialize it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214994 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix a test that has no checks.
Sanjay Patel [Wed, 6 Aug 2014 20:45:30 +0000 (20:45 +0000)]
Fix a test that has no checks.

X86 doesn't have fneg, so check for xor.

Differential Revision: http://reviews.llvm.org/D4812

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214992 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Cleanup fadd and fsub tests
Matt Arsenault [Wed, 6 Aug 2014 20:27:55 +0000 (20:27 +0000)]
R600: Cleanup fadd and fsub tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214991 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "r214897 - Remove dead zero store to calloc initialized memory"
Rui Ueyama [Wed, 6 Aug 2014 19:30:38 +0000 (19:30 +0000)]
Revert "r214897 - Remove dead zero store to calloc initialized memory"

It broke msan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214989 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove the target machine from CCState. Previously it was only used
Eric Christopher [Wed, 6 Aug 2014 18:45:26 +0000 (18:45 +0000)]
Remove the target machine from CCState. Previously it was only used
to get the subtarget and that's accessible from the MachineFunction
now. This helps clear the way for smaller changes where we getting
a subtarget will require passing in a MachineFunction/Function as
well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214988 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove performance of calculateDbgValueHistory.
Adrian Prantl [Wed, 6 Aug 2014 18:41:24 +0000 (18:41 +0000)]
Improve performance of calculateDbgValueHistory.

In r210492 the logic of calculateDbgValueHistory was changed to end
register variable live ranges at the end of MBB conditionally on
the fact that the register was or not clobbered by the function body.

This requires an initial scan of all the operands of the function
to collect all clobbered registers. In a second pass over all
instructions, we compare this set with the set of clobbered
registers for the current MachineInstruction. This modification
incurred a compilation time regression on some benchmarks: the
debug info emission phase takes ~10% more time.

While a small performance hit is unavoidable due to the initial
scan requirement, we can improve the situation by avoiding to
create too many temporary sets and just use lambdas to work directly
on the result of the initial scan.

Fixes <rdar://problem/17884104>

Patch by Frederic Riss!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214987 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCleanup collectChangingRegs
Adrian Prantl [Wed, 6 Aug 2014 18:41:19 +0000 (18:41 +0000)]
Cleanup collectChangingRegs

The handling of the epilogue is best expressed as an early exit and
there is no reason to look for register defs in DbgValue MIs.

Patch by Frederic Riss!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214986 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Fix ranges+gmlt test case to actually exercise the gmlt situation.
David Blaikie [Wed, 6 Aug 2014 18:24:19 +0000 (18:24 +0000)]
DebugInfo: Fix ranges+gmlt test case to actually exercise the gmlt situation.

Originally this test case tested the specified behavior (that -gmlt
would not produce DW_AT_ranges and that when no CU DW_AT_ranges were
produced, no debug_ranges section (not even an empty list) would be
produced) but then the ranges emission code was improved not to create
ranges of a single element (instead favoring high_pc/low_pc) and so this
test case no longer exercised the -gmlt portion of the behavior.

This caused me some confusion when reading the comments and trying to
update this test case for future changes to -gmlt. I've made this test
resilient to those changes (by using the {{DW_TAG|NULL}} pattern to
block the end of the attribute search at the end of the CU's attribute
list without mandating that it must (or must not) be followed by another
tag (the future changes to -gmlt should produce no subprograms in this
CU))

Fix the test case to have two functions in distinct sections to force
the use of DW_AT_ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214985 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a triple to this test to get the right IR mangling
Reid Kleckner [Wed, 6 Aug 2014 18:09:15 +0000 (18:09 +0000)]
Add a triple to this test to get the right IR mangling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214982 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't count inreg params when mangling fastcall functions
Reid Kleckner [Wed, 6 Aug 2014 18:09:04 +0000 (18:09 +0000)]
Don't count inreg params when mangling fastcall functions

This is consistent with MSVC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214981 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRound up the size of byval arguments to MinAlign
Reid Kleckner [Wed, 6 Aug 2014 17:57:23 +0000 (17:57 +0000)]
Round up the size of byval arguments to MinAlign

Otherwise we can end up with an argument frame size that is not a
multiple of stack slot size, which is very awkward.

This fixes PR20547, which was a bug in x86_64 Sys V vararg handling.
However, it's much easier to test this with x86 callee-cleanup
functions, which previously ended in "retl $6" instead of "retl $8".

This does affect behavior of all backends, but it presumably fixes the
same bug in all of them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214980 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUseListOrder: Use std::vector
Duncan P. N. Exon Smith [Wed, 6 Aug 2014 17:36:08 +0000 (17:36 +0000)]
UseListOrder: Use std::vector

I initially used a `SmallVector<>` for `UseListOrder::Shuffle`, which
was a silly choice.  When I realized my error I quickly rolled a custom
data structure.

This commit simplifies it to a `std::vector<>`.  Now that I've had a
chance to measure performance, this data structure isn't part of a
bottleneck, so the additional complexity is unnecessary.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214979 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add a few isTarget* API to AArch64 Subtarget.
Chad Rosier [Wed, 6 Aug 2014 16:56:58 +0000 (16:56 +0000)]
[AArch64] Add a few isTarget* API to AArch64 Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214977 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd test case omitted in r214974.
Chad Rosier [Wed, 6 Aug 2014 16:06:41 +0000 (16:06 +0000)]
Add test case omitted in r214974.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214975 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Fix OS ABI flag for aarch64-linux-gnu target.
Chad Rosier [Wed, 6 Aug 2014 16:05:02 +0000 (16:05 +0000)]
[AArch64] Fix OS ABI flag for aarch64-linux-gnu target.

For triple aarch64-linux-gnu we were incorrectly setting IRIX.
For triple aarch64 we are correctly setting SYSV.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214974 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agouse register iterators that include self to reduce code duplication in CriticalAntiDe...
Sanjay Patel [Wed, 6 Aug 2014 15:58:15 +0000 (15:58 +0000)]
use register iterators that include self to reduce code duplication in CriticalAntiDepBreaker

This patch addresses 2 FIXME comments that I added to CriticalAntiDepBreaker while fixing PR20020.

Initialize an MCSubRegIterator and an MCRegAliasIterator to include the self reg.

Assuming that works as advertised, there should be functional difference with this patch, just less code.

Also, remove the associated asserts - we're setting those values just before, so the asserts don't do anything meaningful.

Differential Revision: http://reviews.llvm.org/D4566

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214973 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Added load/store instructions to Register2Memory opcode tables.
Robert Khasanov [Wed, 6 Aug 2014 15:40:34 +0000 (15:40 +0000)]
[AVX512] Added load/store instructions to Register2Memory opcode tables.
Added lowering tests for load/store.

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214972 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Add a testcase for r214957.
James Molloy [Wed, 6 Aug 2014 13:31:32 +0000 (13:31 +0000)]
[AArch64] Add a testcase for r214957.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214965 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a new option -run-slp-after-loop-vectorization.
James Molloy [Wed, 6 Aug 2014 12:56:19 +0000 (12:56 +0000)]
Add a new option -run-slp-after-loop-vectorization.

This swaps the order of the loop vectorizer and the SLP/BB vectorizers. It is disabled by default so we can do performance testing - ideally we want to change to having the loop vectorizer running first, and the SLP vectorizer using its leftovers instead of the other way around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214963 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM: do not generate BLX instructions on Cortex-M CPUs.
Tim Northover [Wed, 6 Aug 2014 11:13:14 +0000 (11:13 +0000)]
ARM: do not generate BLX instructions on Cortex-M CPUs.

Particularly on MachO, we were generating "blx _dest" instructions on M-class
CPUs, which don't actually exist. They happen to get fixed up by the linker
into valid "bl _dest" instructions (which is why such a massive issue has
remained largely undetected), but we shouldn't rely on that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214959 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoARM-MachO: materialize callee address correctly on v4t.
Tim Northover [Wed, 6 Aug 2014 11:13:06 +0000 (11:13 +0000)]
ARM-MachO: materialize callee address correctly on v4t.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214958 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AArch64] Conditional selects are expensive on out-of-order cores.
James Molloy [Wed, 6 Aug 2014 10:42:18 +0000 (10:42 +0000)]
[AArch64] Conditional selects are expensive on out-of-order cores.

Specifically Cortex-A57. This probably applies to Cyclone too but I haven't enabled it for that as I can't test it.

This gives ~4% improvement on SPEC 174.vpr, and ~1% in 471.omnetpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214957 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix two independent miscompiles in the process of getting the same
Chandler Carruth [Wed, 6 Aug 2014 10:16:36 +0000 (10:16 +0000)]
[x86] Fix two independent miscompiles in the process of getting the same
test case to actually generate correct code.

The primary miscompile fixed here is that we weren't correctly handling
in-place elements in one half of a single-input v8i16 shuffle when
moving a dword of elements from that half to the other half. Some times,
we would clobber the in-place elements in forming the dword to move
across halves.

The fix to this involves forcibly marking the in-place inputs even when
there is no need to gather them into a dword, and to much more carefully
re-arrange the elements when grouping them into a dword to move across
halves. With these two changes we would generate correct shuffles for
the test case, but found another miscompile. There are also some random
perturbations of the generated shuffle pattern in SSE2. It looks like
a wash; more instructions in some cases fewer in others.

The second miscompile would corrupt the results into nonsense. This is
a buggy pattern in one of the added DAG combines. Mapping elements
through a PSHUFD when pairing redundant half-shuffles is *much* harder
than this code makes it out to be -- it requires reasoning about *all*
of where the input is used in the PSHUFD, not just one part of where it
is used. Plus, we can't combine a half shuffle *into* a PSHUFD but the
code didn't guard against it. I think this was just a bad idea and I've
just removed that aspect of the combine. No tests regress as
a consequence so seems OK.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214954 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Switch to a formulation of a for loop that is much more obviously
Chandler Carruth [Wed, 6 Aug 2014 10:16:33 +0000 (10:16 +0000)]
[x86] Switch to a formulation of a for loop that is much more obviously
not corrupting the mask by mutating it more times than intended. No
functionality changed (the results were non-overlapping so the old
version "worked" but was non-obvious).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214953 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fixes commit r214890 to match the posted patch
Adam Nemet [Wed, 6 Aug 2014 07:13:12 +0000 (07:13 +0000)]
[X86] Fixes commit r214890 to match the posted patch

This was another fallout from my local rebase where something went wrong :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214951 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCorrect comment
Matt Arsenault [Wed, 6 Aug 2014 00:44:25 +0000 (00:44 +0000)]
Correct comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214945 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[dfsan] Try not to create too many additional basic blocks in functions which
Peter Collingbourne [Wed, 6 Aug 2014 00:33:40 +0000 (00:33 +0000)]
[dfsan] Try not to create too many additional basic blocks in functions which
already have a large number of blocks. Works around a performance issue with
the greedy register allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214944 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600: Increase nearby load scheduling threshold.
Matt Arsenault [Wed, 6 Aug 2014 00:29:49 +0000 (00:29 +0000)]
R600: Increase nearby load scheduling threshold.

This partially fixes weird looking load scheduling
in memcpy test. The load clustering doesn't seem
particularly smart, but this method seems to be partially
deprecated so it might not be worth trying to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214943 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Implement areLoadsFromSameBasePtr
Matt Arsenault [Wed, 6 Aug 2014 00:29:43 +0000 (00:29 +0000)]
R600/SI: Implement areLoadsFromSameBasePtr

This currently has a noticable effect on the kernel argument loads.
LDS and global loads are more problematic, I think because of how copies
are currently inserted to ensure that the address is a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214942 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86][SchedModel] Fixed some wrong scheduling model found by code inspection.
Quentin Colombet [Wed, 6 Aug 2014 00:22:39 +0000 (00:22 +0000)]
[X86][SchedModel] Fixed some wrong scheduling model found by code inspection.
Source: Agner Fog's Instruction tables.

Related to <rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214940 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least...
David Blaikie [Wed, 6 Aug 2014 00:21:25 +0000 (00:21 +0000)]
DebugInfo: Assert that any CU for which debug_loc lists are emitted, has at least one range.

This was coming in weird debug info that had variables (and hence
debug_locs) but was in GMLT mode (because it was missing the 13th field
of the compile_unit metadata) so no ranges were constructed. We should
always have at least one range for any CU with a debug_loc in it -
because the range should cover the debug_loc.

The assertion just ensures that the "!= 1" range case inside the
subsequent loop doesn't get entered for the case where there are no
ranges at all, which should never reach here in the first place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214939 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Fix a bunch of tests that, owing to their compile_unit metadata not includ...
David Blaikie [Tue, 5 Aug 2014 23:57:31 +0000 (23:57 +0000)]
DebugInfo: Fix a bunch of tests that, owing to their compile_unit metadata not including a 13th field, had some subtle behavior.

Without the 13th field, the "emission kind" field defaults to 0 (which
is not equal to either of the values of the emission kind enum (1 ==
full debug info, 2 == line tables only)).

In this particular instance, the comparison with "FullDebugInfo" was
done when adding elements to the ranges list - so for these test cases
no values were added to the ranges list.

This got weirder when emitting debug_loc entries as the addresses should
be relative to the range of the CU if the CU has only one range (the
reasonable assumption is that if we're emitting debug_loc lists for a CU
that CU has at least one range - but due to the above situation, it has
zero) so the ranges were emitted relative to the start of the section
rather than relative to the start of the CU's singular range.

Fix these tests by accounting for the difference in the description of
debug_loc entries (in some cases making the test ignorant to these
differences, in others adding the extra label difference expression,
etc) or the presence/absence of high/low_pc on the CU, and add the 13th
field to their CUs to enable proper "full debug info" emission here.

In a future commit I'll fix up a bunch of other test cases that are not
so rigorously depending on this behavior, but still doing similarly
weird things due to the missing 13th field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214937 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Add definitions for ds_read2st64_ / ds_write2st64_
Matt Arsenault [Tue, 5 Aug 2014 23:53:20 +0000 (23:53 +0000)]
R600/SI: Add definitions for ds_read2st64_ / ds_write2st64_

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214936 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typos in comments and doc
JF Bastien [Tue, 5 Aug 2014 23:27:34 +0000 (23:27 +0000)]
Fix typos in comments and doc

Committing http://reviews.llvm.org/D4798 for Robin Morisset (morisset@google.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214934 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Move the reference to the CU from the location list entry to the list...
David Blaikie [Tue, 5 Aug 2014 23:14:16 +0000 (23:14 +0000)]
DebugInfo: Move the reference to the CU from the location list entry to the list itself, since it is constant across an entire list.

This simplifies construction and usage while making the data structure
smaller. It was a holdover from the days when we didn't have a separate
DebugLocList and all we had was a flat list of DebugLocEntries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214933 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove a virtual function from TargetMachine. NFC.
Rafael Espindola [Tue, 5 Aug 2014 22:10:21 +0000 (22:10 +0000)]
Remove a virtual function from TargetMachine. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214929 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-apply r214881: Fix return sequence on armv4 thumb
Jonathan Roelofs [Tue, 5 Aug 2014 21:32:21 +0000 (21:32 +0000)]
Re-apply r214881: Fix return sequence on armv4 thumb

This reverts r214893, re-applying r214881 with the test case relaxed a bit to
satiate the build bots.

POP on armv4t cannot be used to change thumb state (unilke later non-m-class
architectures), therefore we need a different return sequence that uses 'bx'
instead:

  POP {r3}
  ADD sp, #offset
  BX r3

This patch also fixes an issue where the return value in r3 would get clobbered
for functions that return 128 bits of data. In that case, we generate this
sequence instead:

  MOV ip, r3
  POP {r3}
  ADD sp, #offset
  MOV lr, r3
  MOV r3, ip
  BX lr

http://reviews.llvm.org/D4748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214928 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[MCJIT] Make llvm-rtdyld check RuntimeDyld's error state when running in -verify
Lang Hames [Tue, 5 Aug 2014 20:51:46 +0000 (20:51 +0000)]
[MCJIT] Make llvm-rtdyld check RuntimeDyld's error state when running in -verify
mode.

This will cause -verify mode to report failure when RuntimeDyld encounters an
internal error (e.g. overflows in relocation computations). Previously we had
let these errors slip past unreported.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214925 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian
Bill Schmidt [Tue, 5 Aug 2014 20:47:25 +0000 (20:47 +0000)]
[PowerPC] Swap arguments and adjust shift count for vsldoi on little endian

Commits r213915 and r214718 fix recognition of shuffle masks for vmrg*
and vpku*um instructions for a little-endian target, by swapping the
input arguments.  The vsldoi instruction requires similar treatment,
and also needs its shift count adjusted for little endian.

Reviewed by Ulrich Weigand.

This is a bug fix candidate for release 3.5 (and hopefully the last of
those for PowerPC).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214923 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImproved test cases that were added with r214892.
Sanjay Patel [Tue, 5 Aug 2014 20:16:35 +0000 (20:16 +0000)]
Improved test cases that were added with r214892.

1. Added ':' to CHECK-LABELs
2. Added more CHECKs
3. Added CHECK-NEXTs
4. Added verbose hex immediate comments to CHECKs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214921 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDon't internalize all but main by default.
Rafael Espindola [Tue, 5 Aug 2014 20:10:38 +0000 (20:10 +0000)]
Don't internalize all but main by default.

This is mostly a cleanup, but it changes a fairly old behavior.

Every "real" LTO user was already disabling the silly internalize pass
and creating the internalize pass itself. The difference with this
patch is for "opt -std-link-opts" and the C api.

Now to get a usable behavior out of opt one doesn't need the funny
looking command line:

opt -internalize -disable-internalize -internalize-public-api-list=foo,bar -std-link-opts

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214919 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd a test showing the interaction of linker scripts and plugin.
Rafael Espindola [Tue, 5 Aug 2014 19:56:53 +0000 (19:56 +0000)]
Add a test showing the interaction of linker scripts and plugin.

In particular, the linker script is processed early enough for function g
to be internalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214916 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[x86] Fix a crasher due to shuffles which cancel each other out and add
Chandler Carruth [Tue, 5 Aug 2014 18:45:49 +0000 (18:45 +0000)]
[x86] Fix a crasher due to shuffles which cancel each other out and add
a test case.

We also miscompile this test case which is showing a serious flaw in the
single-input v8i16 shuffle code. I've left the specific instruction
checks FIXME-ed out until I can address the bug in the single-input
code, but I wanted to separate out a significant functionality change to
produce correct code from a very simple and targeted crasher fix.

The miscompile problem stems from keeping track of inputs by value
rather than by index. As a consequence of doing this, we can't reliably
update those inputs because they might swap and we can't detect this
without copying the mask.

The blend code now uses indices for the input lists and this seems
strictly better. It also should make it easier to sort things and do
other cleanups. I think the time has come to simplify The Great Lambda
here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214914 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove dead code in condition
Duncan P. N. Exon Smith [Tue, 5 Aug 2014 18:22:58 +0000 (18:22 +0000)]
Remove dead code in condition

Whether or not it's appropriate, labels have been first-class types
since r51511.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214908 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoX86CodeEmitter.cpp: Add SEH_Epilogue to ignored list for legacy JIT, corresponding...
NAKAMURA Takumi [Tue, 5 Aug 2014 18:04:15 +0000 (18:04 +0000)]
X86CodeEmitter.cpp: Add SEH_Epilogue to ignored list for legacy JIT, corresponding to r214775.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214905 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Improve comments for r214888
Adam Nemet [Tue, 5 Aug 2014 17:58:49 +0000 (17:58 +0000)]
[X86] Improve comments for r214888

A rebase somehow ate my comments. This restores them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214903 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Use register class instead of list of registers
Matt Arsenault [Tue, 5 Aug 2014 17:52:40 +0000 (17:52 +0000)]
R600/SI: Use register class instead of list of registers

I'm not sure if this has any consequence or not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214902 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Add exec_lo and exec_hi subregisters.
Matt Arsenault [Tue, 5 Aug 2014 17:52:37 +0000 (17:52 +0000)]
R600/SI: Add exec_lo and exec_hi subregisters.

This allows accessing an SReg subregister with a normal subregister
index, instead of getting a machine verifier error.

Also be sure to include all of these subregisters in SReg_32.
This fixes inferring SGPR instead of SReg when finding a
super register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214901 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoBitcodeReader: Fix non-determinism in use-list order
Duncan P. N. Exon Smith [Tue, 5 Aug 2014 17:49:48 +0000 (17:49 +0000)]
BitcodeReader: Fix non-determinism in use-list order

`BasicBlockFwdRefs` (and `BlockAddrFwdRefs` before it) was being emptied
in a non-deterministic order.  When predicting use-list order I've
worked around this another way, but even when parsing lazily (and we
can't recreate use-list order) use-lists should be deterministic.

Make them so by using a side-queue of functions with forward-referenced
blocks that gets visited in order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214899 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRemove dead zero store to calloc initialized memory
Philip Reames [Tue, 5 Aug 2014 17:48:20 +0000 (17:48 +0000)]
Remove dead zero store to calloc initialized memory

Optimize the following IR:

%1 = tail call noalias i8* @calloc(i64 1, i64 4)
%2 = bitcast i8* %1 to i32*
; This store is dead and should be removed
store i32 0, i32* %2, align 4

Memory returned by calloc is guaranteed to be zero initialized. If the value being stored is the constant zero (and the store is not otherwise observable across threads), we can delete the store.  If the store is to an out of bounds address, it is undefined and thus also removable.

Reviewed By: nicholas

Differential Revision: http://reviews.llvm.org/D3942

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214897 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r214881 because it broke lots of build-bots
Jonathan Roelofs [Tue, 5 Aug 2014 17:36:05 +0000 (17:36 +0000)]
Revert r214881 because it broke lots of build-bots

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214893 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoOptimize vector fabs of bitcasted constant integer values.
Sanjay Patel [Tue, 5 Aug 2014 17:35:22 +0000 (17:35 +0000)]
Optimize vector fabs of bitcasted constant integer values.

Allow vector fabs operations on bitcasted constant integer values to be optimized
in the same way that we already optimize scalar fabs.

So for code like this:
%bitcast = bitcast i64 18446744069414584320 to <2 x float> ; 0xFFFF_FFFF_0000_0000
%fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %bitcast)
%ret = bitcast <2 x float> %fabs to i64

Instead of generating something like this:

movabsq (constant pool loadi of mask for sign bits)
vmovq   (move from integer register to vector/fp register)
vandps  (mask off sign bits)
vmovq   (move vector/fp register back to integer return register)

We should generate:

mov     (put constant value in return register)

I have also removed a redundant clause in the first 'if' statement:
N0.getOperand(0).getValueType().isInteger()

is the same thing as:
IntVT.isInteger()

Testcases for x86 and ARM added to existing files that deal with vector fabs.
One existing testcase for x86 removed because it is no longer ideal.

For more background, please see:
http://reviews.llvm.org/D4770

And:
http://llvm.org/bugs/show_bug.cgi?id=20354

Differential Revision: http://reviews.llvm.org/D4785

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214892 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Add masking variant and intrinsics for valignd/q
Adam Nemet [Tue, 5 Aug 2014 17:23:04 +0000 (17:23 +0000)]
[AVX512] Add masking variant and intrinsics for valignd/q

This is similar to what I did with the two-source permutation recently.  (It's
almost too similar so that we should consider generating the masking variants
with some tablegen help.)

Both encoding and intrinsic tests are added as well.  For the latter, this is
what the IR that the intrinsic test on the clang side generates.

Part of <rdar://problem/17688758>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214890 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Increase X86_MAX_OPERANDS from 5 to 6
Adam Nemet [Tue, 5 Aug 2014 17:23:01 +0000 (17:23 +0000)]
[X86] Increase X86_MAX_OPERANDS from 5 to 6

This controls the number of operands in the disassembler's x86OperandSets
table.  The entries describe how the operand is encoded and its type.

Not to surprisingly 5 operands is insufficient for AVX512.  Consider
VALIGNDrrik in the next patch.  These are its operand specifiers:

  { /* 328 */
    { ENCODING_DUP, TYPE_DUP1 },
    { ENCODING_REG, TYPE_XMM512 },
    { ENCODING_WRITEMASK, TYPE_VK8 },
    { ENCODING_VVVV, TYPE_XMM512 },
    { ENCODING_RM_CD64, TYPE_XMM512 },
    { ENCODING_IB, TYPE_IMM8 },
  },

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214889 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Add lowering to VALIGN
Adam Nemet [Tue, 5 Aug 2014 17:22:59 +0000 (17:22 +0000)]
[X86] Add lowering to VALIGN

This was currently part of lowering to PALIGNR with some special-casing to
make interlane shifting work.  Since AVX512F has interlane alignr (valignd/q)
and AVX512BW has vpalignr we need to support both of these *at the same time*,
e.g. for SKX.

This patch breaks out the common code and then add support to check both of
these lowering options from LowerVECTOR_SHUFFLE.

I also added some FIXMEs where I think the AVX512BW and AVX512VL additions
should probably go.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214888 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Separate DAG node for valign and palignr
Adam Nemet [Tue, 5 Aug 2014 17:22:55 +0000 (17:22 +0000)]
[X86] Separate DAG node for valign and palignr

They have different semantics (valign is interlane while palingr is intralane)
and palingr is still needed even in the AVX512 context.  According to the
latest spec AVX512BW provides these.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214887 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] alignr: Use suffix rather than name argument to multiclass
Adam Nemet [Tue, 5 Aug 2014 17:22:52 +0000 (17:22 +0000)]
[AVX512] alignr: Use suffix rather than name argument to multiclass

Again no functional change.  This prepares for the suffix to be used with the
intrinsic matching.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214886 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[AVX512] Pull everything alignr-related into the multiclass
Adam Nemet [Tue, 5 Aug 2014 17:22:50 +0000 (17:22 +0000)]
[AVX512] Pull everything alignr-related into the multiclass

The packed integer pattern becomes the DAG pattern for rri and the packed
float, another Pat<> inside the multiclass.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214885 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoWrap long lines
Adam Nemet [Tue, 5 Aug 2014 17:22:47 +0000 (17:22 +0000)]
Wrap long lines

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214884 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix return sequence on armv4 thumb
Jonathan Roelofs [Tue, 5 Aug 2014 17:13:17 +0000 (17:13 +0000)]
Fix return sequence on armv4 thumb

POP on armv4t cannot be used to change thumb state (unilke later non-m-class
architectures), therefore we need a different return sequence that uses 'bx'
instead:

  POP {r3}
  ADD sp, #offset
  BX r3

This patch also fixes an issue where the return value in r3 would get clobbered
for functions that return 128 bits of data. In that case, we generate this
sequence instead:

  MOV ip, r3
  POP {r3}
  ADD sp, #offset
  MOV lr, r3
  MOV r3, ip
  BX lr

http://reviews.llvm.org/D4748

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214881 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoPartially revert r214761 that asserted that all concrete debug info variables had...
David Blaikie [Tue, 5 Aug 2014 16:47:23 +0000 (16:47 +0000)]
Partially revert r214761 that asserted that all concrete debug info variables had DIEs, due to a failure on Darwin.

I'll work on a reduction and fix after this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214880 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoImprove test for merged global debug info by using llvm-dwarfdump.
David Blaikie [Tue, 5 Aug 2014 16:20:25 +0000 (16:20 +0000)]
Improve test for merged global debug info by using llvm-dwarfdump.

It's a bit of a tradeoff, since llvm-dwarfdump doesn't print the name of
the global symbol being used as an address in the addressing mode, but
this avoids the dependence on hardcoded set labels that keep changing
(5+ commits over the last few years that each update the set label as it
changes due to other, unrelated differences in output). This could've,
instead, been changed to match the set name then match the name in the
string pool but that would present other issues (needing to skip over
the sets that weren't of interest, etc) and checking that the addresses
(granted, without relocations applied - so it's not the whole story)
match in the two variable location descriptions seems sufficient and
fairly stable here.

There are a few similar other tests with similar label dependence that
I'll update soonish.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214878 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd accessors for the PPC 403 bank registers.
Joerg Sonnenberger [Tue, 5 Aug 2014 15:45:15 +0000 (15:45 +0000)]
Add accessors for the PPC 403 bank registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214875 91177308-0d34-0410-b5e6-96231b3b80d8