7 years agoReformat.
NAKAMURA Takumi [Wed, 6 May 2015 14:03:22 +0000 (14:03 +0000)]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236601 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert r236546, "propagate IR-level fast-math-flags to DAG nodes (NFC)"
NAKAMURA Takumi [Wed, 6 May 2015 14:03:12 +0000 (14:03 +0000)]
Revert r236546, "propagate IR-level fast-math-flags to DAG nodes (NFC)"

It caused undefined behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236600 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] generate VMAXNM/VMINNM for a compare followed by a select, in safe math mode too
Artyom Skrobov [Wed, 6 May 2015 11:44:10 +0000 (11:44 +0000)]
[ARM] generate VMAXNM/VMINNM for a compare followed by a select, in safe math mode too

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236590 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert regression test from r236584.
Pawel Bylica [Wed, 6 May 2015 10:41:46 +0000 (10:41 +0000)]
Revert regression test from r236584.

Temporary remove a regression test added in r236584. It fails on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236586 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoSelectionDAG: Handle out-of-bounds index in extract vector element
Pawel Bylica [Wed, 6 May 2015 10:19:14 +0000 (10:19 +0000)]
SelectionDAG: Handle out-of-bounds index in extract vector element

Summary: This patch correctly handles undef case of EXTRACT_VECTOR_ELT node where the element index is constant and not less than vector size.

Test Plan:
CodeGen for X86 test included.
Also one incorrect regression test fixed.

Reviewers: qcolombet, chandlerc, hfinkel

Reviewed By: hfinkel

Subscribers: hfinkel, llvm-commits

Differential Revision: http://reviews.llvm.org/D9250

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236584 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DomTree] verifyDomTree to unconditionally perform DT verification
Adam Nemet [Wed, 6 May 2015 08:18:41 +0000 (08:18 +0000)]
[DomTree] verifyDomTree to unconditionally perform DT verification

I folded the check for the flag -verify-dom-info into the only caller
where I think it is supposed to be checked: verifyAnalysis.  (The idea
of the flag is to enable this expensive verification in

I'm assuming that when manually scheduling the verification pass
with -passes=verify<domtree>, we do want to perform the verification.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236575 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM][FastISel] Use TST #1 instead of CMP #0 for select.
Ahmed Bougacha [Wed, 6 May 2015 04:14:02 +0000 (04:14 +0000)]
[ARM][FastISel] Use TST #1 instead of CMP #0 for select.

Since r234249, i1 are sext instead of zext; because of that, doing
"CMP rN, #0; IT EQ/NE" isn't correct anymore.

"TST #1" is the conservatively correct alternative - the tradeoff being
that it doesn't have a 16-bit encoding -, so use that instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236569 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Statepoints] Remove broken test case.
Sanjoy Das [Wed, 6 May 2015 02:51:46 +0000 (02:51 +0000)]
[Statepoints] Remove broken test case.

statepoint-indirect-return.ll breaks on linux systems.  Delete the test
case to make the bots green while I figure out what the right fix is.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236568 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IRBuilder] Fix indentation. NFC.
Sanjoy Das [Wed, 6 May 2015 02:36:34 +0000 (02:36 +0000)]
[IRBuilder] Fix indentation.  NFC.

Whitespace-only change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236567 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Statepoint] Clean up StatepointLowering: symbolic constants.
Sanjoy Das [Wed, 6 May 2015 02:36:31 +0000 (02:36 +0000)]
[Statepoint] Clean up StatepointLowering: symbolic constants.

For accessors in the `Statepoint` class, use symbolic constants for
offsets into the argument vector instead of literals.  This makes the
code intent clearer and simpler to change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236566 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Statepoint] Clean up Statepoint.h: clang-format.
Sanjoy Das [Wed, 6 May 2015 02:36:28 +0000 (02:36 +0000)]
[Statepoint] Clean up Statepoint.h: clang-format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236565 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Statepoint] Clean up Statepoint.h: accessor names.
Sanjoy Das [Wed, 6 May 2015 02:36:26 +0000 (02:36 +0000)]
[Statepoint] Clean up Statepoint.h: accessor names.

Use getFoo() as accessors consistently and some other naming changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236564 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[StatepointLowering] Don't create temporary instructions. NFCI.
Sanjoy Das [Wed, 6 May 2015 02:36:20 +0000 (02:36 +0000)]
[StatepointLowering] Don't create temporary instructions.  NFCI.

Instead of creating a temporary call instruction and lowering that, use

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236563 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[WinEH] Reset WinEHPrepare::SEHExceptionCodeSlot when we're done.
Ahmed Bougacha [Wed, 6 May 2015 01:28:58 +0000 (01:28 +0000)]
[WinEH] Reset WinEHPrepare::SEHExceptionCodeSlot when we're done.

This caused a use-after-free on test/CodeGen/X86/win32-eh.ll
No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236561 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoInstrProf: Strip filename prefixes from the names we display for coverage
Justin Bogner [Tue, 5 May 2015 23:44:48 +0000 (23:44 +0000)]
InstrProf: Strip filename prefixes from the names we display for coverage

For consumers of coverage data, any filename prefixes we store in the
profile data are just noise. Strip this prefix if it exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236558 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86 fast-isel] Constrain the index reg class to not include SP.
Pete Cooper [Tue, 5 May 2015 23:41:53 +0000 (23:41 +0000)]
[X86 fast-isel] Constrain the index reg class to not include SP.

The index reg on instructions with complex address modes is a GPR64_NOSP.  Constrain it to appease the machine verifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236557 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SelectionDAG] Make an argument optional in RFV::getCopyToRegs. NFC.
Sanjoy Das [Tue, 5 May 2015 23:06:57 +0000 (23:06 +0000)]
[SelectionDAG] Make an argument optional in RFV::getCopyToRegs.  NFC.

We default the value argument to nullptr.  The only use of the value is
in diagnosePossiblyInvalidConstraint and that seems to be resilient to
it being nullptr.

Reviewers: atrick, reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9479

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236555 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SelectionDAG] Move RegsForValue into SelectionDAGBuilder.h. NFC.
Sanjoy Das [Tue, 5 May 2015 23:06:54 +0000 (23:06 +0000)]
[SelectionDAG] Move RegsForValue into SelectionDAGBuilder.h. NFC.

The exported class will be used in later change, in
StatepointLowering.cpp.  It is still internal to SelectionDAG (not
exported via include/).

Reviewers: reames, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9478

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236554 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SelectionDAG] Pass explicit type to lowerCallOperands. NFC.
Sanjoy Das [Tue, 5 May 2015 23:06:52 +0000 (23:06 +0000)]
[SelectionDAG] Pass explicit type to lowerCallOperands. NFC.

Currently this does not change anything, but change will be used in a
later change to StatepointLowering.cpp

Reviewers: reames, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9477

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236553 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[StatepointLowering] Rename variable, NFC.
Sanjoy Das [Tue, 5 May 2015 23:06:49 +0000 (23:06 +0000)]
[StatepointLowering] Rename variable, NFC.

Rename LoweredArgs to LoweredMetaArgs to clarify intent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236552 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix IfConverter to handle regmask machine operands.
Pete Cooper [Tue, 5 May 2015 22:09:41 +0000 (22:09 +0000)]
Fix IfConverter to handle regmask machine operands.

Note, this is a recommit of r236515 after fixing an error in r236514.  The buildbot ran fast enough that it picked up r236514 prior to r236515 and threw an error.  r236515 itself ran 'make check' without errors.

Original commit message follows:

A regmask (typically seen on a call) clobbers the set of registers it lists.  The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks.

These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier.  Otherwise, uses after the if converted call could think they are reading an undefined register.

Reviewed by Matthias Braun and Quentin Colombet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236550 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[lib/Fuzzer] on crash print the contents of the crashy input as base64
Kostya Serebryany [Tue, 5 May 2015 21:59:51 +0000 (21:59 +0000)]
[lib/Fuzzer] on crash print the contents of the crashy input as base64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236548 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agopropagate IR-level fast-math-flags to DAG nodes (NFC)
Sanjay Patel [Tue, 5 May 2015 21:40:38 +0000 (21:40 +0000)]
propagate IR-level fast-math-flags to DAG nodes (NFC)

This patch adds the minimum plumbing necessary to use IR-level
fast-math-flags (FMF) in the backend without actually using
them for anything yet. This is a follow-on to:

...which split the existing nsw / nuw / exact flags and FMF
into their own struct.

There are 2 structural changes here:

1. The main diff is that we're preparing to extend the optimization
flags to affect more than just binary SDNodes. Eg, IR intrinsics
( https://llvm.org/bugs/show_bug.cgi?id=21290 ) or non-binop nodes
that don't even exist in IR such as FMA, FNEG, etc.

2. The other change is that we're actually copying the FP fast-math-flags
from the IR instructions to SDNodes.

Differential Revision: http://reviews.llvm.org/D8900

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236546 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agouse range-based for-loop; NFC
Sanjay Patel [Tue, 5 May 2015 21:20:52 +0000 (21:20 +0000)]
use range-based for-loop; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236544 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdded Andrey Churbanov as the owner of the OpenMP runtime library code
Andrey Churbanov [Tue, 5 May 2015 20:17:53 +0000 (20:17 +0000)]
Added Andrey Churbanov as the owner of the OpenMP runtime library code

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236540 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Inliner] Discard empty COMDAT groups
David Majnemer [Tue, 5 May 2015 20:14:22 +0000 (20:14 +0000)]
[Inliner] Discard empty COMDAT groups

COMDAT groups which have become rendered unused because of inline are
discardable if we can prove that we've made the group empty.

This fixes PR22285.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236539 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor UpdatePredRedefs and StepForward to avoid duplication. NFC
Pete Cooper [Tue, 5 May 2015 20:14:22 +0000 (20:14 +0000)]
Refactor UpdatePredRedefs and StepForward to avoid duplication.  NFC

Note, this is a reapplication of r236515 with a fix to not assert on non-register operands, but instead only handle them until the subsequent commit.  Original commit message follows.

The code was basically the same here already.  Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs.

Will be used in the next commit to also handle regmasks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236538 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThumb2SizeReduction: Check the correct set of registers for LDMIA.
Peter Collingbourne [Tue, 5 May 2015 20:07:10 +0000 (20:07 +0000)]
Thumb2SizeReduction: Check the correct set of registers for LDMIA.

The register set for LDMIA begins at offset 3, not 4. We were previously
missing the short encoding of this instruction in the case where the base
register was the first register in the register set.

Also clean up some dead code:

- The isARMLowRegister check is redundant with what VerifyLowRegs does;
  replace with an assert.
- Remove handling of LDMDB instruction, which has no short encoding (and
  does not appear in ReduceTable).

Differential Revision: http://reviews.llvm.org/D9485

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236535 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load
Ulrich Weigand [Tue, 5 May 2015 19:34:10 +0000 (19:34 +0000)]
[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

This patch makes ReplaceExtractVectorEltOfLoadWithNarrowedLoad convert
the element number from getVectorIdxTy() to PtrTy before doing pointer
arithmetic on it.  This is needed on z, where element numbers are i32
but pointers are i64.

Original patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236530 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Fix ReplaceExtractVectorEltOfLoadWithNarrowedLoad for BE
Ulrich Weigand [Tue, 5 May 2015 19:33:37 +0000 (19:33 +0000)]
[DAGCombiner] Fix ReplaceExtractVectorEltOfLoadWithNarrowedLoad for BE

For little-endian, the function would convert (extract_vector_elt (load X), Y)
to X + Y*sizeof(elt).  For big-endian it would instead use
X + sizeof(vec) - Y*sizeof(elt).  The big-endian case wasn't right since
vector index order always follows memory/array order, even for big-endian.
(Note that the current handling has to be wrong for Y==0 since it would
access beyond the end of the vector.)

Original patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236529 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[LegalizeVectorTypes] Allow single loads and stores for more short vectors
Ulrich Weigand [Tue, 5 May 2015 19:32:57 +0000 (19:32 +0000)]
[LegalizeVectorTypes] Allow single loads and stores for more short vectors

When lowering a load or store for TypeWidenVector, the type legalizer
would use a single load or store if the associated integer type was legal.
E.g. it would load a v4i8 as an i32 if i32 was legal.

This patch extends that behavior to promoted integers as well as legal ones.
If the integer type for the full vector width is TypePromoteInteger,
the element type is going to be TypePromoteInteger too, and it's still
better to use a single promoting load or truncating store rather than N
individual promoting loads or truncating stores.  E.g. if you have a v2i8
on a target where i16 is promoted to i32, it's better to load the v2i8 as
an i16 rather than load both i8s individually.

Original patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236528 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add vector intrinsics
Ulrich Weigand [Tue, 5 May 2015 19:31:09 +0000 (19:31 +0000)]
[SystemZ] Add vector intrinsics

This adds intrinsics to allow access to all of the z13 vector instructions.
Note that instructions whose semantics can be described by standard LLVM IR
do not get any intrinsics.

For each instructions whose semantics *cannot* (fully) be described, we
define an LLVM IR target-specific intrinsic that directly maps to this

For instructions that also set the condition code, the LLVM IR intrinsic
returns the post-instruction CC value as a second result.  Instruction
selection will attempt to detect code that compares that CC value against
constants and use the condition code directly instead.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236527 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Mark v1i128 and v1f128 as unsupported
Ulrich Weigand [Tue, 5 May 2015 19:30:05 +0000 (19:30 +0000)]
[SystemZ] Mark v1i128 and v1f128 as unsupported

The ABI specifies that <1 x i128> and <1 x fp128> are supposed to be
passed in vector registers.  We do not yet support those types, and
some infrastructure is missing before we can do so.

In order to prevent accidentally generating code violating the ABI,
this patch adds checks to detect those types and error out if user
code attempts to use them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236526 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Handle sub-128 vectors
Ulrich Weigand [Tue, 5 May 2015 19:29:21 +0000 (19:29 +0000)]
[SystemZ] Handle sub-128 vectors

The ABI allows sub-128 vectors to be passed and returned in registers,
with the vector occupying the upper part of a register.  We therefore
want to legalize those types by widening the vector rather than promoting
the elements.

The patch includes some simple tests for sub-128 vectors and also tests
that we can recognize various pack sequences, some of which use sub-128
vectors as temporary results.  One of these forms is based on the pack
sequences generated by llvmpipe when no intrinsics are used.

Signed unpacks are recognized as BUILD_VECTORs whose elements are
individually sign-extended.  Unsigned unpacks can have the equivalent
form with zero extension, but they also occur as shuffles in which some
elements are zero.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236525 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add CodeGen support for scalar f64 ops in vector registers
Ulrich Weigand [Tue, 5 May 2015 19:28:34 +0000 (19:28 +0000)]
[SystemZ] Add CodeGen support for scalar f64 ops in vector registers

The z13 vector facility includes some instructions that operate only on the
high f64 in a v2f64, effectively extending the FP register set from 16
to 32 registers.  It's still better to use the old instructions if the
operands happen to fit though, since the older instructions have a shorter

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add CodeGen support for v4f32
Ulrich Weigand [Tue, 5 May 2015 19:27:45 +0000 (19:27 +0000)]
[SystemZ] Add CodeGen support for v4f32

The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used.  Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.

This particularly helps with llvmpipe.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236523 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add CodeGen support for v2f64
Ulrich Weigand [Tue, 5 May 2015 19:26:48 +0000 (19:26 +0000)]
[SystemZ] Add CodeGen support for v2f64

This adds ABI and CodeGen support for the v2f64 type, which is natively
supported by z13 instructions.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236522 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add CodeGen support for integer vector types
Ulrich Weigand [Tue, 5 May 2015 19:25:42 +0000 (19:25 +0000)]
[SystemZ] Add CodeGen support for integer vector types

This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility.  This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).

When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
  (except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.

The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.

However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.

These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level.  This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236521 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Add z13 vector facility and MC support
Ulrich Weigand [Tue, 5 May 2015 19:23:40 +0000 (19:23 +0000)]
[SystemZ] Add z13 vector facility and MC support

This patch adds support for the z13 processor type and its vector facility,
and adds MC support for all new instructions provided by that facilily.

Apart from defining the new instructions, the main changes are:

- Adding VR128, VR64 and VR32 register classes.
- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.
- Adding a D(V,B) addressing mode for scatter/gather operations
- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields.
  Until now all immediate operands have been the same width as the
  underlying field (hence the assert->return change in decode[SU]ImmOperand).

In addition, sys::getHostCPUName is extended to detect running natively
on a z13 machine.

Based on a patch by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Refactor UpdatePredRedefs and StepForward to avoid duplication. NFC"
Pete Cooper [Tue, 5 May 2015 18:49:08 +0000 (18:49 +0000)]
Revert "Refactor UpdatePredRedefs and StepForward to avoid duplication.  NFC"

This reverts commit 963cdbccf6e5578822836fd9b2ebece0ba9a60b7 (ie r236514)

This is to get the bots green while i investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236518 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "Fix IfConverter to handle regmask machine operands."
Pete Cooper [Tue, 5 May 2015 18:49:05 +0000 (18:49 +0000)]
Revert "Fix IfConverter to handle regmask machine operands."

This reverts commit b27413cbfd78d959c18e713bfa271fb69e6b3303 (ie r236515).

This is to get the bots green while i investigate the failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236517 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix IfConverter to handle regmask machine operands.
Pete Cooper [Tue, 5 May 2015 18:31:36 +0000 (18:31 +0000)]
Fix IfConverter to handle regmask machine operands.

A regmask (typically seen on a call) clobbers the set of registers it lists.  The IfConverter, in UpdatePredRedefs, was handling register defs, but not regmasks.

These are slightly different to a def in that we need to add both an implicit use and def to appease the machine verifier.  Otherwise, uses after the if converted call could think they are reading an undefined register.

Reviewed by Matthias Braun and Quentin Colombet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236515 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRefactor UpdatePredRedefs and StepForward to avoid duplication. NFC
Pete Cooper [Tue, 5 May 2015 18:31:31 +0000 (18:31 +0000)]
Refactor UpdatePredRedefs and StepForward to avoid duplication.  NFC

The code was basically the same here already.  Just added an out parameter for a vector of seen defs so that UpdatePredRedefs can call StepForward first, then do its own post processing on the seen defs.

Will be used in the next commit to also handle regmasks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236514 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo in assert message. NFC.
Diego Novillo [Tue, 5 May 2015 18:24:47 +0000 (18:24 +0000)]
Fix typo in assert message. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236513 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix the clang -Werror build, use of uninitialized variable.
David Blaikie [Tue, 5 May 2015 18:12:33 +0000 (18:12 +0000)]
Fix the clang -Werror build, use of uninitialized variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236512 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoUpdate BasicAliasAnalysis to understand that nothing aliases with undef values.
Daniel Berlin [Tue, 5 May 2015 18:10:49 +0000 (18:10 +0000)]
Update BasicAliasAnalysis to understand that nothing aliases with undef values.
It got this in some cases (if one of them was an identified object), but not in all cases.

This caused stores to undef to block load-forwarding in some cases, etc.

Added test to Transforms/GVN to verify optimization occurs as expected.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236511 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[opaque pointer type] Track explicit GEP pointee type through in-memory IR
David Blaikie [Tue, 5 May 2015 18:03:48 +0000 (18:03 +0000)]
[opaque pointer type] Track explicit GEP pointee type through in-memory IR

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236510 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRe-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
Reid Kleckner [Tue, 5 May 2015 17:44:16 +0000 (17:44 +0000)]
Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"

This reverts commit r236360.

This change exposed a bug in WinEHPrepare by opting win32 code into EH
preparation. We already knew that WinEHPrepare has bugs, and is the
status quo for x64, so I don't think that's a reason to hold off on this
change. I disabled exceptions in the sanitizer tests in r236505 and an
earlier revision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236508 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ShrinkWrap] Add (a simplified version) of shrink-wrapping.
Quentin Colombet [Tue, 5 May 2015 17:38:16 +0000 (17:38 +0000)]
[ShrinkWrap] Add (a simplified version) of shrink-wrapping.

This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits

As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.

** Context **

Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
The job of the shrink-wrapping pass is to identify such places.

** Motivating example **

Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b)  {
 %tmp = alloca i32, align 4
 %tmp2 = icmp slt i32 %a, %b
 br i1 %tmp2, label %true, label %false

 store i32 %a, i32* %tmp, align 4
 %tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
 br label %false

 %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
 ret i32 %tmp.0

On AArch64 this code generates (removing the cfi directives to ease
_f:                                     ; @f
; BB#0:
  stp x29, x30, [sp, #-16]!
  mov  x29, sp
  sub sp, sp, #16             ; =16
  cmp  w0, w1
  b.ge  LBB0_2
; BB#1:                                 ; %true
  stur  w0, [x29, #-4]
  sub x1, x29, #4             ; =4
  mov  w0, wzr
  bl  _doSomething
LBB0_2:                                 ; %false
  mov  sp, x29
  ldp x29, x30, [sp], #16

With shrink-wrapping we could generate:
_f:                                     ; @f
; BB#0:
  cmp  w0, w1
  b.ge  LBB0_2
; BB#1:                                 ; %true
  stp x29, x30, [sp, #-16]!
  mov  x29, sp
  sub sp, sp, #16             ; =16
  stur  w0, [x29, #-4]
  sub x1, x29, #4             ; =4
  mov  w0, wzr
  bl  _doSomething
  add sp, x29, #16            ; =16
  ldp x29, x30, [sp], #16
LBB0_2:                                 ; %false

Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.

** Proposed Solution **

This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.

Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.

The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using

Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.

** Design Decisions **

1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating

Differential Revision: http://reviews.llvm.org/D9210


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236507 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Reapply r236465 with fixes for the MSVC bots.
Lang Hames [Tue, 5 May 2015 17:37:18 +0000 (17:37 +0000)]
[Orc] Reapply r236465 with fixes for the MSVC bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236506 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[bugpoint] Increase default memory limit to 400MB to fix bugpoint tests.
Daniel Sanders [Tue, 5 May 2015 16:29:40 +0000 (16:29 +0000)]
[bugpoint] Increase default memory limit to 400MB to fix bugpoint tests.

I tracked down the bug to an unchecked malloc in SmallVectorBase::grow_pod().
This malloc is returning NULL on my machine when running under bugpoint but not
when -enable-valgrind is given.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236504 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoThis patch adds ABI support for v1i128 data type.
Kit Barton [Tue, 5 May 2015 16:10:44 +0000 (16:10 +0000)]
This patch adds ABI support for v1i128 data type.
It adds v1i128 to the appropriate register classes and checks parameter passing
and return values.

This is related to http://reviews.llvm.org/D9081, which will add instructions
that exploit the v1i128 datatype.

Phabricator review: http://reviews.llvm.org/D9475

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236503 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoEmit comment for gc.relocate showing base and derived pointers in human readable...
Igor Laevsky [Tue, 5 May 2015 13:20:42 +0000 (13:20 +0000)]
Emit comment for gc.relocate showing base and derived pointers in human readable form.

Differential Revision: http://reviews.llvm.org/D9326

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236497 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips] Generate code for insert/extract operations when using the N64 ABI and MSA.
Daniel Sanders [Tue, 5 May 2015 10:32:24 +0000 (10:32 +0000)]
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA.

When using the N64 ABI, element-indices use the i64 type instead of i32.
In many cases, we can use iPTR to account for this but additional patterns
and pseudo's are also required.

This fixes most (but not quite all) failures in the test-suite when using
N64 and MSA together.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9342

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236494 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix regression in parsing armv{6,7}hl- triples. These are used by SUSE
Ismail Donmez [Tue, 5 May 2015 09:29:43 +0000 (09:29 +0000)]
Fix regression in parsing armv{6,7}hl- triples. These are used by SUSE
and Redhat currently.

Reviewed by Jonathan Roelofs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236492 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[mips][msa] Test basic operations for the N32 ABI too.
Daniel Sanders [Tue, 5 May 2015 08:48:35 +0000 (08:48 +0000)]
[mips][msa] Test basic operations for the N32 ABI too.

This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236489 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[lib/Fuzzer] use handle_abort=1 by default so that when assert() fires we save the...
Kostya Serebryany [Tue, 5 May 2015 01:42:55 +0000 (01:42 +0000)]
[lib/Fuzzer] use handle_abort=1 by default so that when assert() fires we save the test case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236476 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Revert r236465 - It broke the Windows bots.
Lang Hames [Mon, 4 May 2015 23:30:01 +0000 (23:30 +0000)]
[Orc] Revert r236465 - It broke the Windows bots.

Looks like the usual missing explicit move-constructor issue with MSVC. I should
have a fix shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236472 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[X86] Fix assertion while DAG combining offsets and ExternalSymbols
Reid Kleckner [Mon, 4 May 2015 23:22:36 +0000 (23:22 +0000)]
[X86] Fix assertion while DAG combining offsets and ExternalSymbols

ExternalSymbol nodes do not contain offsets, unlike GlobalValue nodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236471 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[ARM] IT block insertion needs to update kill flags
Pete Cooper [Mon, 4 May 2015 22:44:47 +0000 (22:44 +0000)]
[ARM] IT block insertion needs to update kill flags

When forming an IT block from the first MOV here:

%R2<def> = t2MOVr %R0, pred:1, pred:%CPSR, opt:%noreg
%R3<def> = tMOVr %R0<kill>, pred:14, pred:%noreg

the move in to R3 is moved out of the IT block so that later instructions on the same predicate can be inside this block, and we can share the IT instruction.

However, when moving the R3 copy out of the IT block, we need to clear its kill flags for anything in use at this point in time, ie, R0 here.

This appeases the machine verifier which thought that R0 wasn't defined when used.

I have a test case, but its extremely register allocator specific.  It would be too fragile to commit a test which depends on the register allocator here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236468 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAdd TransformUtils dependency to lli.
Pete Cooper [Mon, 4 May 2015 22:33:39 +0000 (22:33 +0000)]
Add TransformUtils dependency to lli.

After r236465, Orc uses ValueMaterializer and so needs to link against TransformUtils to get the ValueMaterializer::anchor().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236467 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[Orc] Refactor the compile-on-demand layer to make module partitioning lazy,
Lang Hames [Mon, 4 May 2015 22:03:10 +0000 (22:03 +0000)]
[Orc] Refactor the compile-on-demand layer to make module partitioning lazy,
and avoid cloning unused decls into every partition.

Module partitioning showed up as a source of significant overhead when I
profiled some trivial test cases. Avoiding the overhead of partitionging
for uncalled functions helps to mitigate this.

This change also means that it is no longer necessary to have a
LazyEmittingLayer underneath the CompileOnDemand layer, since the
CompileOnDemandLayer will not extract or emit function bodies until they are

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236465 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVim: Fix some bugs in llvm indent plugin.
Matthias Braun [Mon, 4 May 2015 21:41:25 +0000 (21:41 +0000)]
Vim: Fix some bugs in llvm indent plugin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236464 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoVim: Set filetype=python for lit configuration files.
Matthias Braun [Mon, 4 May 2015 21:41:23 +0000 (21:41 +0000)]
Vim: Set filetype=python for lit configuration files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236463 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDocument some of the options in test/lit.cfg
Matthias Braun [Mon, 4 May 2015 21:37:00 +0000 (21:37 +0000)]
Document some of the options in test/lit.cfg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236462 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLit: Allow overriding llvm tool paths+arguments, make -D an alias for --param
Matthias Braun [Mon, 4 May 2015 21:36:36 +0000 (21:36 +0000)]
Lit: Allow overriding llvm tool paths+arguments, make -D an alias for --param

These changes allow usages where you want to pass an additional
commandline option to all invocations of a specific llvm tool. Example:

> llvm-lit -Dllc=llc -enable-misched -verify-machineinstrs

Differential Revision: http://reviews.llvm.org/D9487

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236461 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agozap windows line endings; NFC
Sanjay Patel [Mon, 4 May 2015 21:27:27 +0000 (21:27 +0000)]
zap windows line endings; NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236460 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoCodeGen: match up correct insertvalue indices when assessing tail calls.
Tim Northover [Mon, 4 May 2015 20:41:51 +0000 (20:41 +0000)]
CodeGen: match up correct insertvalue indices when assessing tail calls.

When deciding whether a value comes from the aggregate or inserted value of an
insertvalue instruction, we compare the indices against those of the location
we're interested in. One of the lists needs reversing because the input data is
backwards (so that modifications take place at the end of the SmallVector), but
we were reversing both before leading to incorrect results.

Should fix PR23408

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236457 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoYAML: Add an optional 'flow' field to the mapping trait to allow flow mapping output.
Alex Lorenz [Mon, 4 May 2015 20:11:40 +0000 (20:11 +0000)]
YAML: Add an optional 'flow' field to the mapping trait to allow flow mapping output.

This patch adds an optional 'flow' field to the MappingTrait
class so that yaml IO will be able to output flow mappings.

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9450

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236456 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRespect object format choice on Darwin
Keno Fischer [Mon, 4 May 2015 20:03:01 +0000 (20:03 +0000)]
Respect object format choice on Darwin

The object format can be set to something other than MachO, e.g.
to use ELF-on-Darwin for MCJIT. This already works on Windows, so
there's no reason it shouldn't on Darwin.

Reviewers: lhames, grosbach

Subscribers: rafael, grosbach, t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D6185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236455 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix -Wmicrosoft warning by making enum unsigned
Reid Kleckner [Mon, 4 May 2015 18:21:35 +0000 (18:21 +0000)]
Fix -Wmicrosoft warning by making enum unsigned

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236436 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[IR/Diagnostic] Assert that DebugLoc is valid before accessing.
Davide Italiano [Mon, 4 May 2015 18:08:35 +0000 (18:08 +0000)]
[IR/Diagnostic] Assert that DebugLoc is valid before accessing.

PR: 23380
Differential Revision: http://reviews.llvm.org/D9464
Reviewed by: dexonsmith

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236435 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoOption parsing: properly handle flag aliases for joined options (PR23394)
Hans Wennborg [Mon, 4 May 2015 18:00:13 +0000 (18:00 +0000)]
Option parsing: properly handle flag aliases for joined options (PR23394)

A joined option always needs to have an argument, even if it's an empty one.

Clang would previously assert when trying to use --extra-warnings, which is
a flag alias for -W, which is a joined option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236434 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Reclassify f32 subregs of f64 registers
Ulrich Weigand [Mon, 4 May 2015 17:41:22 +0000 (17:41 +0000)]
[SystemZ] Reclassify f32 subregs of f64 registers

At the moment, all subregs defined by the SystemZ target can be modified
independently of the wider register.  E.g. writing to a GR32 does not
change the upper 32 bits of the GR64.  Writing to an FP32 does not change
the lower 32 bits of the FP64.

Hoewver, the upcoming support for the vector extension redefines FP64 as
one half of a V128.  Floating-point operations leave the other half of
a V128 in an unpredictable state, so it's no longer the case that writing
to an FP32 leaves the bits of the underlying register (the V128) alone.
I'd prefer to have separate subreg_ names for this situation, so that
it's obvious at a glance whether we're talking about a subreg that leaves
the other parts of the register alone.

No behavioral change intended.

Patch originally by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236433 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Clean up AsmParser isMem() handling
Ulrich Weigand [Mon, 4 May 2015 17:40:53 +0000 (17:40 +0000)]
[SystemZ] Clean up AsmParser isMem() handling

We know what MemoryKind an operand has at the time we construct it,
so we might as well just record it in an unused part of the structure.
This makes it easier to add scatter/gather addresses later.

No behavioral change intended.

Patch originally by Richard Sandiford.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236432 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SystemZ] Fix getTargetNodeName
Ulrich Weigand [Mon, 4 May 2015 17:39:40 +0000 (17:39 +0000)]
[SystemZ] Fix getTargetNodeName

It seems SystemZTargetLowering::getTargetNodeName got out of sync with
some recent changes to the SystemZISD opcode list.  Add back all the
missing opcodes (and re-sort to the same order as SystemISelLowering.h).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236430 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoScheduleDAGInstrs should toggle kill flags on bundled instrs.
Pete Cooper [Mon, 4 May 2015 16:52:06 +0000 (16:52 +0000)]
ScheduleDAGInstrs should toggle kill flags on bundled instrs.

ScheduleDAGInstrs wasn't setting or clearing the kill flags on instructions inside bundles.  This led to code such as this

%R3<def> = t2ANDrr %R0
BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use,kill>
  t2IT 1, 24, %ITSTATE<imp-def>
  R6<def,tied6> = t2ORRrr %R0<kill>, ...

being transformed to

BUNDLE %ITSTATE<imp-def,dead>, %R0<imp-use>
  t2IT 1, 24, %ITSTATE<imp-def>
  R6<def,tied6> = t2ORRrr %R0<kill>, ...
%R3<def> = t2ANDrr %R0<kill>

where the kill flag was removed from the BUNDLE instruction, but not the t2ORRrr inside it.  The verifier then thought that
R0 was undefined when read by the AND.

This change make the toggleKillFlags method also check for bundles and toggle flags on bundled instructions.
Setting the kill flag is special cased as we only want to set the kill flag on the last instruction in the bundle.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236428 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoR600/SI: Code cleanup
Tom Stellard [Mon, 4 May 2015 16:45:08 +0000 (16:45 +0000)]
R600/SI: Code cleanup

This is a follow-up to r236004

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236427 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: added a test for encoding
Elena Demikhovsky [Mon, 4 May 2015 12:59:15 +0000 (12:59 +0000)]
AVX-512: added a test for encoding
by Asaf Badouh (asaf.badouh@intel.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236421 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: added calling convention for i1 vectors in 32-bit mode.
Elena Demikhovsky [Mon, 4 May 2015 12:40:50 +0000 (12:40 +0000)]
AVX-512: added calling convention for i1 vectors in 32-bit mode.
Fixed some bugs in extend/truncate for AVX-512 target.
Removed VBROADCASTM (masked broadcast) node, since it is not used any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236420 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: added integer "add" and "sub" instructions with saturation for SKX
Elena Demikhovsky [Mon, 4 May 2015 12:35:55 +0000 (12:35 +0000)]
AVX-512: added integer "add" and "sub" instructions with saturation for SKX
with intrinsics and tests

by Asaf Badouh (asaf.badouh@intel.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236418 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: enabled tests for AVX512F set
Elena Demikhovsky [Mon, 4 May 2015 11:09:41 +0000 (11:09 +0000)]
AVX-512: enabled tests for AVX512F set

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236416 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoAVX-512: Added VPACK* instructions forms for KNL and SKX
Elena Demikhovsky [Mon, 4 May 2015 09:14:02 +0000 (09:14 +0000)]
AVX-512: Added VPACK* instructions forms for KNL and SKX
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236414 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoReplace windows_error calls with mapWindowsError.
Yaron Keren [Mon, 4 May 2015 04:48:10 +0000 (04:48 +0000)]
Replace windows_error calls with mapWindowsError.

After r210687, windows_error does nothing but call mapWindowsError.
Other Windows/*.inc files directly call mapWindowsError. This patch
updates Path.inc and Process.inc to do the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236409 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agollvm-cov: Warn if object file is newer than profile
Justin Bogner [Mon, 4 May 2015 04:09:38 +0000 (04:09 +0000)]
llvm-cov: Warn if object file is newer than profile

Looking at coverage with an out of date profile can be confusing.
Provide a little hint that something might be wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236408 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDeprecate in-source autotools builds
Jonathan Roelofs [Mon, 4 May 2015 02:04:54 +0000 (02:04 +0000)]
Deprecate in-source autotools builds

This is a followup from:

Upgrade instructions:
  $ mv llvm/include/llvm/Config/config.h ./config.h.BACKUP
  # copy the configure line from line 7 of llvm/config.log
  # (for example: `$ ./configure --no-create --no-recursion`)
  $ mkdir build
  $ cd build
  # run the configure line, but this time with '../llvm' at the beginning:
  $ ../llvm/configure --no-create --no-recursion

These warnings will soon be turned into hard errors after a week.  Speak up now
if this is going to be a problem for you.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236399 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TableGen] Replace 'static_cast' with 'cast'.
Craig Topper [Mon, 4 May 2015 01:35:42 +0000 (01:35 +0000)]
[TableGen] Replace 'static_cast' with 'cast'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236398 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[TableGen] Formatting cleanup. Mostly removing trailing whitespace and unnecessary...
Craig Topper [Mon, 4 May 2015 01:35:39 +0000 (01:35 +0000)]
[TableGen] Formatting cleanup. Mostly removing trailing whitespace and unnecessary curly braces. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236397 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMasked gather and scatter intrinsics - enabled codegen for KNL.
Elena Demikhovsky [Sun, 3 May 2015 07:12:25 +0000 (07:12 +0000)]
Masked gather and scatter intrinsics - enabled codegen for KNL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236394 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix typo in comment.
Nico Weber [Sat, 2 May 2015 21:34:39 +0000 (21:34 +0000)]
Fix typo in comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236392 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SSE2] Minor tidyup of v16i8 SHL lowering. NFC.
Simon Pilgrim [Sat, 2 May 2015 14:42:43 +0000 (14:42 +0000)]
[SSE2] Minor tidyup of v16i8 SHL lowering. NFC.

Removed code that was replicating v8i16 'shift + mask' implementation that is done more nicely by making use of LowerScalarImmediateShift

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236388 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[DAGCombiner] Enabled vector float/double -> int constant folding
Simon Pilgrim [Sat, 2 May 2015 13:04:07 +0000 (13:04 +0000)]
[DAGCombiner] Enabled vector float/double -> int constant folding

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236387 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoLine ending fix
Simon Pilgrim [Sat, 2 May 2015 11:50:47 +0000 (11:50 +0000)]
Line ending fix

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236386 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SSE] Added vector int (i32 and i64) -> float/double conversion tests
Simon Pilgrim [Sat, 2 May 2015 11:42:47 +0000 (11:42 +0000)]
[SSE] Added vector int (i32 and i64) -> float/double conversion tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236385 91177308-0d34-0410-b5e6-96231b3b80d8

7 years ago[SSE] Added vector float/double -> i32 and i64 conversion tests
Simon Pilgrim [Sat, 2 May 2015 11:18:47 +0000 (11:18 +0000)]
[SSE] Added vector float/double -> i32 and i64 conversion tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236384 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoDebugInfo: Use low_pc relative debug_ranges under fission when the CU has a low_pc
David Blaikie [Sat, 2 May 2015 02:31:49 +0000 (02:31 +0000)]
DebugInfo: Use low_pc relative debug_ranges under fission when the CU has a low_pc

Seems we were setting the base address on the wrong DwarfCompileUnit
object so it wasn't being used when generating the ranges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236377 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRework test to use FileCheck by making sure we have no xmm registers
Eric Christopher [Sat, 2 May 2015 01:06:17 +0000 (01:06 +0000)]
Rework test to use FileCheck by making sure we have no xmm registers
with numbers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236373 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoMC: Tidy up comments and clean up formatting a bit. NFC.
Jim Grosbach [Sat, 2 May 2015 00:44:14 +0000 (00:44 +0000)]
MC: Tidy up comments and clean up formatting a bit. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236368 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoFix spelling.
Jim Grosbach [Sat, 2 May 2015 00:44:07 +0000 (00:44 +0000)]
Fix spelling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236367 91177308-0d34-0410-b5e6-96231b3b80d8

7 years agoRevert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"
Reid Kleckner [Fri, 1 May 2015 22:50:14 +0000 (22:50 +0000)]
Revert "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"

This reverts commit r236359. Things are still broken despite testing. :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236360 91177308-0d34-0410-b5e6-96231b3b80d8