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[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
[oota-llvm.git]
/
test
/
CodeGen
/
AArch64
/
fast-isel-shift.ll
2015-02-27
Mehdi Amini
Change the fast-isel-abort option from bool to int...
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2014-11-18
Chad Rosier
[FastISel][AArch64] Also allow folding of sign-/zero...
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2014-11-18
Chad Rosier
[FastISel][AArch64] Also allow folding of sign-/zero...
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2014-11-18
Juergen Ributzka
[FastISel][AArch64] Follow-up fix for "Fix shift-immedi...
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2014-11-18
Juergen Ributzka
[FastISel][AArch64] Fix shift-immediate emission for...
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2014-09-22
Juergen Ributzka
[FastISel][AArch64] Also allow folding of sign-/zero...
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2014-09-02
Juergen Ributzka
[FastISel][AArch64] Use the target-dependent selection...
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2014-08-27
Juergen Ributzka
[FastISel][AArch64] Fold Sign-/Zero-Extend into the...
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2014-08-21
Juergen Ributzka
[FastISel][AArch64] Add support for variable shift.
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2014-08-21
Juergen Ributzka
[FastISel][AArch64] Use the correct register class...
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2014-08-04
Juergen Ributzka
[FastISel][AArch64] Fix shift lowering for i8 and i16...
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2014-07-30
Juergen Ributzka
[FastISel][AArch64] Add support for shift-immediate.
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projects / oota-llvm.git / history