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[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.
[oota-llvm.git]
/
test
/
CodeGen
/
AArch64
/
fast-isel-mul.ll
2015-02-27
Mehdi Amini
Change the fast-isel-abort option from bool to int...
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2014-09-17
Juergen Ributzka
[FastISel][AArch64] Simplify mul to shift when possible.
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2014-08-21
Juergen Ributzka
[FastISel][AArch64] Use the correct register class...
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2014-07-10
Tim Northover
AArch64: correctly fast-isel i8 & i16 multiplies
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