[FunctionAttrs] Move the malloc-like test to a static helper function
[oota-llvm.git] / lib / Target /
2015-09-13 Elena DemikhovskyAVX-512: Fixed a bug in OR/XOR operations for 512-bit...
2015-09-12 Sanjay Patel[x86] enable machine combiner reassociations for 128...
2015-09-12 Simon Pilgrim[X86] Renamed lowerVectorShuffleAsUnpack NFCI.
2015-09-12 Simon Pilgrim[X86] Moved lowerVectorShuffleWithUNPCK earlier to...
2015-09-12 Sanjay Patelrevert r247506; need to verify changes in existing...
2015-09-12 Sanjay Patel[x86] enable machine combiner reassociations for 128...
2015-09-12 Bruce MitchenerFix typos.
2015-09-11 Akira HatanakaUse function attribute "stackrealign" to decide whether...
2015-09-11 Ahmed Bougacha[CodeGen] Refactor TLI/AtomicExpand interface to make...
2015-09-11 Ahmed Bougacha[CodeGen] Rename AtomicRMWExpansionKind to AtomicExpans...
2015-09-11 NAKAMURA TakumiPPCFrameLowering::emitEpilogue(): Avoid manipulating...
2015-09-10 Cong HouPass BranchProbability/BlockMass by value instead of...
2015-09-10 Reid Kleckner[WinEH] Push and pop EBP for 32-bit funclets
2015-09-10 Matt ArsenaultAMDGPU: Simplify debug printing
2015-09-10 Matt ArsenaultAMDGPU: Use StringRef value
2015-09-10 James Y Knight[SPARC] Switch to the Machine Scheduler.
2015-09-10 James Y KnightRevert "[SPARC] Switch to the Machine Scheduler."
2015-09-10 James Y Knight[SPARC] Switch to the Machine Scheduler.
2015-09-10 Hans WennborgRe-commit r247216: "Fix Clang-tidy misc-use-override...
2015-09-10 Steven WuFix an undefined behavior introduces in r247234
2015-09-10 Igor BregerAVX512: Implemented encoding and intrinsics for
2015-09-10 James Molloy[ARM] Do not use vtrn for vectorshuffle if the order...
2015-09-10 Chandler Carruth[ADT] Switch a bunch of places in LLVM that were doing...
2015-09-10 Kit BartonEnable the shrink wrapping optimization for PPC64.
2015-09-10 Ahmed Bougacha[AArch64] Match FI+offset in STNP addressing mode.
2015-09-10 Ahmed Bougacha[AArch64] Match base+offset in STNP addressing mode.
2015-09-10 Ahmed Bougacha[AArch64] Support selecting STNP.
2015-09-10 Matt ArsenaultAMDGPU/SI: Fix more cases of losing exec operands
2015-09-10 Matt ArsenaultAMDGPU/SI: Fix creating v_mov_b32s without exec uses
2015-09-10 Hans WennborgRevert r247216: "Fix Clang-tidy misc-use-override warni...
2015-09-10 Ahmed Bougacha[CodeGen] Make x86 nontemporal store patfrags generic...
2015-09-10 Reid Kleckner[WinEH] Add codegen support for cleanuppad and cleanupret
2015-09-10 Hans WennborgFix Clang-tidy misc-use-override warnings, other minor...
2015-09-09 Reid Kleckner[SEH] Emit 32-bit SEH tables for the new EH IR
2015-09-09 Renato GolinRevert "AVX512: Implemented encoding and intrinsics...
2015-09-09 Matthias BraunSave LaneMask with livein registers
2015-09-09 Chandler Carruth[PM/AA] Rebuild LLVM's alias analysis infrastructure...
2015-09-09 Matt ArsenaultAMDGPU: Extract full 64-bit subregister and use subregs
2015-09-09 Matt ArsenaultAMDGPU: Remove unused multiclass argument
2015-09-09 Dan Gohman[WebAssembly] Implement calls with void return types.
2015-09-09 Tom StellardAMDGPU/SI: Fold operands through REG_SEQUENCE instructions
2015-09-09 Silviu Baranga[CostModel][AArch64] Remove amortization factor for...
2015-09-09 Dan Gohman[WebAssembly] Tidy up some unneeded newline characters.
2015-09-09 Igor BregerAVX512: Implemented encoding and intrinsics for
2015-09-09 Zoran Jovanovic[mips][microMIPS] Implement ADDU16, AND16, ANDI16,...
2015-09-09 Zoran Jovanovic[mips][microMIPS] Implement CACHEE and PREFE instructions
2015-09-09 Matt ArsenaultAMDGPU: Fix not encoding src2 of VOP3b instructions
2015-09-09 Dan Gohman[WebAssembly] Fix lowering of calls with more than...
2015-09-09 Matt ArsenaultSelectionDAG: Support Expand of f16 extloads
2015-09-09 Dan Gohman[WebAssembly] Implement WebAssemblyInstrInfo::copyPhysReg
2015-09-08 Reid Kleckner[WinEH] Emit prologues and epilogues for funclets
2015-09-08 Eric ChristopherFix the PPC CTR Loop pass to look for calls to the...
2015-09-08 Matt ArsenaultAMDGPU/SI: Fix input vcc operand for VOP2b instructions
2015-09-08 Artem Belevich[NVPTX] Added run NVVMReflect pass to NVPTX back-end.
2015-09-08 Derek Schuffx32. Fixes a bug in how struct va_list is initialized...
2015-09-08 Dan Gohman[WebAssembly] Support running without a register alloca...
2015-09-08 Matt ArsenaultAMDGPU: Mark s_barrier as a high latency instruction
2015-09-08 Matt ArsenaultAMDGPU: Fix s_barrier flags
2015-09-08 Derek Schuffx32. Fixes a bug in i8mem_NOREX declaration.
2015-09-08 Matt ArsenaultAMDGPU: Handle sub of constant for DS offset folding
2015-09-08 David BlaikieFix CPP Backend for GEP API changes for opaque pointer...
2015-09-08 Andrew KaylorFix for bz24500: Avoid non-deterministic code generatio...
2015-09-08 JF BastienWebAssembly: NFC rename shr/sar
2015-09-08 Jun Bum LimRemove white space (test commit)
2015-09-08 Zoran Jovanovic[mips][microMIPS] Implement LLE, LUI, LW and LWE instru...
2015-09-08 Igor BregerAVX512: kunpck encoding implementation
2015-09-08 Dan Gohman[WebAssembly] Enable SSA lowering and other pre-regallo...
2015-09-08 Elena DemikhovskyRemoved an old comment, NFC
2015-09-08 Zoran Jovanovic[mips][microMIPS] Implement SB, SBE, SCE, SH and SHE...
2015-09-08 Daniel Sanders[mips] Reserve address spaces 1-255 for software use.
2015-09-08 Zoran Jovanovic[mips][microMIPS] Add microMIPS32r6 and microMIPS64r6...
2015-09-08 Elena Demikhovskycompilation issue, NFC
2015-09-08 Elena Demikhovskyfixed compilation issue, NFC.
2015-09-08 Elena DemikhovskyAVX-512: Lowering for 512-bit vector shuffles.
2015-09-07 Zoran Jovanovic[mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL...
2015-09-07 Zoran Jovanovic[mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16...
2015-09-07 John Brawn[ARM] Get rid of SelectT2ShifterOperandReg, NFC
2015-09-07 Zoran Jovanovic[mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT...
2015-09-07 NAKAMURA TakumiPrune utf8 chars in comments.
2015-09-06 Hal Finkel[PowerPC] Don't commute trivial rlwimi instructions
2015-09-05 Zoran Jovanovic[mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt...
2015-09-05 Hal Finkel[PowerPC] Fix and(or(x, c1), c2) -> rlwimi generation
2015-09-04 Hal Finkel[PowerPC] Enable interleaved-access vectorization
2015-09-03 Hal Finkel[PowerPC] Always use aggressive interleaving on the A2
2015-09-03 Hal Finkel[PowerPC] Try harder to find a base+offset when looking...
2015-09-03 Hal Finkel[PowerPC] Include the permutation cost for unaligned...
2015-09-03 Hal Finkel[PowerPC] Compute the MMO offset for an unaligned load...
2015-09-03 Chad Rosier[AArch64] Improve ISel using across lane addition reduc...
2015-09-03 Reid KlecknerSink COFF.h MC include into .cpp files
2015-09-03 Chad RosierRevert "[AArch64] Improve load/store optimizer to handl...
2015-09-03 Sanjay Patel[x86] enable machine combiner reassociations for scalar...
2015-09-03 Sanjay Patelcheck for fastness before merging in DAGCombiner::Merge...
2015-09-03 Chad Rosier[AArch64] Improve load/store optimizer to handle LDUR...
2015-09-03 Chad Rosier[AArch64] Reuse MayLoad. NFC.
2015-09-03 Daniel Sanders[mips] Added support for the div, divu, ddiv and ddivu...
2015-09-03 Igor BregerAVX512: Implemented encoding and intrinsics for vplzcnt...
2015-09-02 Ahmed Bougacha[X86] Require 32-byte alignment for 32-byte VMOVNTs.
2015-09-02 Ahmed Bougacha[X86] Cleanup nontemporal fragments. NFCI.
2015-09-02 Hal Finkel[PowerPC] Cleanup cost model for unaligned vector loads...
2015-09-02 Ahmed Bougacha[AArch64] More consistently separate asm opc and operan...
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