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Merging r261039:
[oota-llvm.git]
/
lib
/
Target
/
X86
/
X86InstrShiftRotate.td
2015-10-12
Craig Topper
[X86] Use u8imm for the immediate type for all shift...
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2015-04-28
Sergey Dmitrouk
Reapply r235977 "[DebugInfo] Add debug locations to...
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2015-04-28
Daniel Jasper
Revert "[DebugInfo] Add debug locations to constant...
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2015-04-28
Sergey Dmitrouk
[DebugInfo] Add debug locations to constant SD nodes
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2015-01-07
Craig Topper
[X86] Don't mark the shift by 1 instructions as isConve...
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2014-12-04
Michael Liao
[X86] Clean up whitespace as well as minor coding style
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2014-11-26
Craig Topper
Replace neverHasSideEffects=1 with hasSideEffects=0...
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2014-02-02
Craig Topper
Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a...
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2014-01-14
Craig Topper
Separate the concept of 16-bit/32-bit operand size...
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2014-01-08
David Woodhouse
[x86] Add OpSize16 to instructions that need it
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2013-07-31
Craig Topper
Changed register names (and pointer keywords) to be...
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2013-07-22
Craig Topper
Fix typo. Change %cl to CL in Intel pattern.
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2013-05-04
Nadav Rotem
whitespace
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2013-03-25
Jakob Stoklund Olesen
Annotate shifts and rotates with SchedRW lists.
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2012-12-27
Craig Topper
Add hasSideEffects=0 to some shift and rotate instructi...
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2012-09-26
Michael Liao
Add SARX/SHRX/SHLX code generation support
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2012-09-26
Michael Liao
Add RORX code generation support
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2012-02-18
Jia Liu
Emacs-tag and some comment fix for all ARM, CellSPU...
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2012-02-01
Andrew Trick
Instruction scheduling itinerary for Intel Atom.
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2012-01-03
Devang Patel
Intel style asm variant does not need '%' prefix.
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2011-10-23
Craig Topper
Add X86 SARX, SHRX, and SHLX instructions.
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2011-10-23
Craig Topper
Add X86 RORX instruction
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2010-11-06
Chris Lattner
rework the rotate-by-1 instructions to be defined like the
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2010-10-05
Chris Lattner
integrate the 64-bit shifts into X86InstrShiftRotate...
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2010-10-05
Chris Lattner
move 32-bit shift and rotates out to their own file.
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