R600/SI: Try to keep i32 mul on SALU
[oota-llvm.git] / lib / Target / R600 / SIInstructions.td
2014-09-03 Matt ArsenaultR600/SI: Try to keep i32 mul on SALU
2014-09-03 Tom StellardR600/SI: Add a pattern for i64 and in a branch
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul
2014-08-22 Tom StellardR600/SI: Use READ2/WRITE2 instructions for 64-bit mem...
2014-08-22 Tom StellardR600/SI: Use a ComplexPattern for DS loads and stores
2014-08-21 Tom StellardR600/SI: Use eliminateFrameIndex() to expand SGPR spill...
2014-08-15 Matt ArsenaultR600/SI: Move all fabs / fneg handling to patterns
2014-08-15 Matt ArsenaultR600/SI: Use source modifiers for f64 fneg
2014-08-15 Matt ArsenaultR600/SI: Refactor fneg / fabs patterns
2014-08-15 Matt ArsenaultR600/SI: Add intrinsic for ldexp
2014-08-11 Tom StellardR600/SI: Add an _OFFEN variant MUBUF_STORE_* and use...
2014-08-05 Matt ArsenaultR600/SI: Add definitions for ds_read2st64_ / ds_write2st64_
2014-08-04 Matt ArsenaultR600/SI: Fix definitions for ds_read2 / ds_write2 instr...
2014-08-01 Tom StellardR600/SI: Do abs/neg folding with ComplexPatterns
2014-07-30 Matt ArsenaultR600/SI: Remove redundant setting of bits on instructions.
2014-07-21 Tom StellardR600/SI: Use scratch memory for large private arrays
2014-07-21 Tom StellardR600/SI: Remove vaddr operand from BUFFER_LOAD_*_OFFSET...
2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant...
2014-07-21 Tom StellardR600/SI: Add isCFDepth0 Predicate to SALU addc pattern
2014-07-21 Tom StellardR600/SI: Use VALU for i1 XOR
2014-07-21 Tom StellardR600/SI: Use a custom encoding method for simm16 in...
2014-07-21 Tom StellardR600/SI: Rename SOPP operands to match the encoding...
2014-07-19 Matt ArsenaultR600/SI: implement range reduction for sin/cos
2014-07-17 Tim NorthoverCodeGen: extend f16 conversions to permit types > float.
2014-07-15 Matt ArsenaultR600/SI: Allow using f32 rcp / rsq when denormals not...
2014-07-15 Matt ArsenaultR600/SI: Implement less wrong f32 fdiv
2014-07-11 Marek OlsakR600/SI: Use i32 vectors for resources and samplers
2014-07-11 Marek OlsakR600/SI: add sample and image intrinsics exposing all...
2014-07-10 Matt ArsenaultR600/SI: Add support for llvm.convert.{to|from}.fp16
2014-07-02 Tom StellardR600/SI: Use a ComplexPattern for ADDR64 addressing...
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32
2014-07-02 Tom StellardR600/SI: Add verifier check for immediates in register...
2014-06-24 Tom StellardR600/SI: Use a ComplexPattern for MUBUF stores
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions.
2014-06-24 Matt ArsenaultR600/SI: Move pattern to instruction definition
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic.
2014-06-20 Tom StellardR600/SI: Add patterns for ctpop inside a branch
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc
2014-06-20 Tom StellardR600/SI: Add a VALU pattern for i64 xor
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions.
2014-06-18 Marek OlsakR600/SI: add gather4 and getlod intrinsics (v3)
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions
2014-06-18 Matt ArsenaultR600/SI: Comparisons set vcc.
2014-06-17 Matt ArsenaultR600/SI: Match cttz_zero_undef
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory
2014-06-17 Tom StellardR600/SI: Add a pattern for llvm.AMDGPU.barrier.global
2014-06-13 Tom StellardR600: Remove AMDIL instruction and register definitions
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics.
2014-06-12 Matt ArsenaultR600/SI: Use a register set to -1 for data0 on ds_inc...
2014-06-11 Matt ArsenaultR600/SI: Fix bitcast between v2i32 and f64
2014-06-11 Matt ArsenaultR600/SI: Update place using old subtarget predicate
2014-06-11 Matt ArsenaultR600/SI: Add common 64-bit LDS atomics
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for 64-bit LDS...
2014-06-11 Matt ArsenaultR600/SI: Add 32-bit LDS atomic cmpxchg
2014-06-11 Matt ArsenaultR600/SI: Use LDS atomic inc / dec
2014-06-11 Matt ArsenaultR600/SI: Add other LDS atomic operations
2014-06-11 Matt ArsenaultR600/SI: Add instruction definitions for more LDS ops
2014-06-11 Matt ArsenaultR600/SI: Fix backwards names for local atomic instructions.
2014-06-11 Matt ArsenaultR600/SI: Refactor local atomics.
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions
2014-06-11 Matt ArsenaultR600/SI: Fix selection failure on scalar_to_vector
2014-06-10 Tom StellardR600/SI: Fix a crash when spilling SGPRs
2014-06-10 Matt ArsenaultR600/SI: Implement i64 ctpop
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop
2014-06-10 Matt ArsenaultR600: Handle fcopysign
2014-06-10 Matt ArsenaultR600/SI: Handle sign_extend and zero_extend to i64...
2014-06-09 Matt ArsenaultR600/SI: Rename VOP3 helper class to be more general
2014-06-09 Matt ArsenaultR600/SI: Keep 64-bit not on SALU
2014-06-05 Matt ArsenaultR600/SI: Match rsq instructions
2014-05-31 Matt ArsenaultR600/SI: Remove redundant patterns
2014-05-31 Matt ArsenaultR600/SI: Fix [s|u]int_to_fp for i1
2014-05-29 Matt ArsenaultR600/SI: Fix pattern variable names.
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24
2014-05-22 Matt ArsenaultR600/SI: Move instruction pattern to instruction definition
2014-05-22 Matt ArsenaultR600/SI: Match fp_to_uint / uint_to_fp for f64
2014-05-16 Tom StellardR600/SI: Refactor the VOP3_32 tablegen class
2014-05-16 Tom StellardR600/SI: Add a PredicateControl class for managing...
2014-05-16 Tom StellardR600/SI: Move tablegen patterns away from instruction...
2014-05-16 Tom StellardR600/SI: Remove unused instruction
2014-05-16 Tom StellardR600/SI: Promote f32 SELECT to i32
2014-05-16 Tom StellardR600/SI: Remove duplicate pattern
2014-05-15 Tom StellardR600/SI: Stop using VSrc_* as the default register...
2014-05-15 Tom StellardR600/SI: Use VALU instructions for i1 ops
2014-05-10 Vincent LejeuneR600/SI: Prettier display of input modifiers
2014-05-10 Vincent LejeuneR600/SI: Use pseudo instruction for fabs/clamp/fneg
2014-05-09 Tom StellardR600/SI: Fix SMRD pattern for offsets > 32 bits
2014-05-02 Tom StellardR600/SI: Only create one instruction when spilling...
2014-04-30 Tom StellardR600/SI: Use VALU instructions for copying i1 values
2014-04-29 Tom StellardR600/SI: Custom lower SI_IF and SI_ELSE to avoid machin...
2014-04-29 Tom StellardR600/SI: Only select SALU instructions in the entry...
2014-04-22 Tom StellardR600/SI: Reorganize SIInstructions.td
2014-04-22 Matt ArsenaultR600: Make sign_extend_inreg legal.
2014-04-18 Matt ArsenaultR600/SI: Match sign_extend_inreg to s_sext_i32_i8 and...
2014-04-17 Tom StellardR600/SI: Stop using i128 as the resource descriptor...
2014-04-17 Matt ArsenaultR600/SI: f64 frint is legal on CI
2014-04-11 Matt ArsenaultR600/SI: Refactor SOPC classes slightly.
2014-04-09 Matt ArsenaultR600/SI: Match not instruction.
2014-04-07 Tom StellardR600: Match 24-bit arithmetic patterns in a Target...
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