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R600: Custom lower frem
[oota-llvm.git] / lib / Target / R600 / AMDGPUISelLowering.cpp
2014-09-10 Matt ArsenaultR600: Custom lower frem blob | commitdiff | raw
2014-08-29 Matt ArsenaultR600/SI: Use mad for fsub + fmul blob | commitdiff | raw | diff to current
2014-08-21 Sanjay Patelname change: isPow2DivCheap -> isPow2SDivCheap blob | commitdiff | raw | diff to current
2014-08-15 Matt ArsenaultR600/SI: Use source modifiers for f64 fneg blob | commitdiff | raw | diff to current
2014-08-15 Matt ArsenaultR600/SI: Use source modifier for f64 fabs blob | commitdiff | raw | diff to current
2014-08-15 Matt ArsenaultR600/SI: Add intrinsic for ldexp blob | commitdiff | raw | diff to current
2014-08-12 Jan VeselyR600: Use optimized 24bit path in udivrem blob | commitdiff | raw | diff to current
2014-08-12 Jan VeselyR600: Remove unused code. blob | commitdiff | raw | diff to current
2014-08-12 Jan VeselyR600: Use i24 optimized path for SREM blob | commitdiff | raw | diff to current
2014-08-09 Matt ArsenaultR600: Disable FP exceptions. blob | commitdiff | raw | diff to current
2014-08-05 Tom StellardR600/SI: Avoid generating REGISTER_LOAD instructions. blob | commitdiff | raw | diff to current
2014-08-04 Eric ChristopherRemove the TargetMachine forwards for TargetSubtargetIn... blob | commitdiff | raw | diff to current
2014-08-04 Matt ArsenaultUse the known address space constant rather than checki... blob | commitdiff | raw | diff to current
2014-08-01 Tom StellardRevert "R600: Move code for generating REGISTER_LOAD... blob | commitdiff | raw | diff to current
2014-08-01 Tom StellardR600: Move code for generating REGISTER_LOAD into R600I... blob | commitdiff | raw | diff to current
2014-07-31 Louis GerbargMake sure no loads resulting from load->switch DAGCombi... blob | commitdiff | raw | diff to current
2014-07-25 Chandler Carruth[SDAG] Enable the new assert for out-of-range result... blob | commitdiff | raw | diff to current
2014-07-24 Matt ArsenaultR600: Add new functions for splitting vector loads... blob | commitdiff | raw | diff to current
2014-07-24 Matt ArsenaultR600: Fix LowerSDIV24 blob | commitdiff | raw | diff to current
2014-07-21 Tom StellardR600/SI: Store constant initializer data in constant... blob | commitdiff | raw | diff to current
2014-07-18 Tim NorthoverR600: support fpext/fptrunc operations to and from... blob | commitdiff | raw | diff to current
2014-07-18 Tim NorthoverR600: support f16 -> f64 conversion intrinsic. blob | commitdiff | raw | diff to current
2014-07-15 Jan VeselyR600: Implement zero undef variants of ctlz/cttz blob | commitdiff | raw | diff to current
2014-07-15 Matt ArsenaultR600: Add dag combine for copy of an illegal type. blob | commitdiff | raw | diff to current
2014-07-10 Jan VeselyR600: Implement float to long/ulong blob | commitdiff | raw | diff to current
2014-07-07 Matt ArsenaultR600: Fix mishandling of load / store chains. blob | commitdiff | raw | diff to current
2014-07-02 Tom StellardR600: Add a comment that llvm.AMDGPU.trunc is a legacy... blob | commitdiff | raw | diff to current
2014-07-02 Tom StellardR600: Promote i64 loads to v2i32 blob | commitdiff | raw | diff to current
2014-07-02 Matt ArsenaultR600: Fix crashes when an illegal type load or store... blob | commitdiff | raw | diff to current
2014-06-30 Matt ArsenaultR600: Move mul combine to separate function blob | commitdiff | raw | diff to current
2014-06-27 Matt ArsenaultR600: Move load/store ReplaceNodeResults to common... blob | commitdiff | raw | diff to current
2014-06-26 Aaron BallmanSilencing a warning about isZExtFree hiding an inherite... blob | commitdiff | raw | diff to current
2014-06-26 Matt ArsenaultR600: Fix vector FMA blob | commitdiff | raw | diff to current
2014-06-24 Tom StellardR600: Promote i64 stores to v2i32 blob | commitdiff | raw | diff to current
2014-06-24 Matt ArsenaultR600: Fix inconsistency in rsq instructions. blob | commitdiff | raw | diff to current
2014-06-24 Matt ArsenaultR600: Remove DIV_INF blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600/SI: Fix div_scale intrinsic. blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600: Remove AMDILISelLowering blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600: Select is not expensive. blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600: Move add/sub with overflow out of AMDILISelLowering blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600: Move more out of AMDILISelLowering blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600/SI: Handle i64 sub. blob | commitdiff | raw | diff to current
2014-06-23 Matt ArsenaultR600: Rename AMDIL file blob | commitdiff | raw | diff to current
2014-06-22 Jan VeselyR600: Use LowerSDIVREM for i64 node replace blob | commitdiff | raw | diff to current
2014-06-22 Jan VeselyR600: Implement custom SDIVREM. blob | commitdiff | raw | diff to current
2014-06-20 Tom StellardR600/SI: Add a pattern for f32 ftrunc blob | commitdiff | raw | diff to current
2014-06-20 Tom StellardR600: Expand vector flog2 blob | commitdiff | raw | diff to current
2014-06-20 Tom StellardR600: Expand vector fexp2 blob | commitdiff | raw | diff to current
2014-06-19 Matt ArsenaultR600/SI: Add intrinsics for various math instructions. blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultUse stdint macros for specifying size of constants blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultR600: Handle fnearbyint blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultUse LL suffix for literal that should be 64-bits. blob | commitdiff | raw | diff to current
2014-06-18 Jan VeselyR600: Expand vector fceil blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultWork around ridiculous warning. blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultR600/SI: Add intrinsics for brev instructions blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultR600: Implement f64 ftrunc, ffloor and fceil. blob | commitdiff | raw | diff to current
2014-06-18 Matt ArsenaultR600: Custom lower f64 frint for pre-CI blob | commitdiff | raw | diff to current
2014-06-17 Matt ArsenaultR600/SI: Match ctlz_zero_undef blob | commitdiff | raw | diff to current
2014-06-17 Tom StellardR600: Use LDS and vectors for private memory blob | commitdiff | raw | diff to current
2014-06-17 Tom StellardSelectionDAG: Expand i64 = FP_TO_SINT i32 blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultFix copy paste error blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultR600: Remove a few more things from AMDILISelLowering blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultR600: Fix assert on vector sdiv blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultR600: Move / cleanup more leftover AMDIL stuff. blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultR600: Move division custom lowering out of AMDILISelLow... blob | commitdiff | raw | diff to current
2014-06-15 Matt ArsenaultR600: Report that integer division is expensive. blob | commitdiff | raw | diff to current
2014-06-14 Matt ArsenaultR600: Fix asserts related to constant initializers blob | commitdiff | raw | diff to current
2014-06-14 Matt ArsenaultR600: Use address space enum instead of value blob | commitdiff | raw | diff to current
2014-06-13 Matt ArsenaultR600: Cleanup some old AMDIL stuff. blob | commitdiff | raw | diff to current
2014-06-13 Matt ArsenaultR600/SI: Fix selection error on i64 rotl / rotr. blob | commitdiff | raw | diff to current
2014-06-12 Matt ArsenaultR600: Mostly remove remaining AMDIL intrinsics. blob | commitdiff | raw | diff to current
2014-06-11 Matt ArsenaultR600/SI: Use v_cvt_f32_ubyte* instructions blob | commitdiff | raw | diff to current
2014-06-11 Rafael EspindolaTry to fix the msvc build. blob | commitdiff | raw | diff to current
2014-06-11 Matt ArsenaultUse cast instead of assert + dyn_cast blob | commitdiff | raw | diff to current
2014-06-11 Matt ArsenaultR600: Add helper functions. blob | commitdiff | raw | diff to current
2014-06-10 Matt ArsenaultR600: Use BCNT_INT for evergreen blob | commitdiff | raw | diff to current
2014-06-10 Matt ArsenaultR600/SI: Use bcnt instruction for ctpop blob | commitdiff | raw | diff to current
2014-06-10 Matt ArsenaultR600: Handle fcopysign blob | commitdiff | raw | diff to current
2014-06-09 Matt ArsenaultR600: Fix selection failure for vector bswap blob | commitdiff | raw | diff to current
2014-06-01 Matt ArsenaultR600: Set all float vector expands in the same place blob | commitdiff | raw | diff to current
2014-05-22 Matt ArsenaultR600: Try to convert BFE back to standard bit ops when... blob | commitdiff | raw | diff to current
2014-05-22 Matt ArsenaultR600: Add dag combine for BFE blob | commitdiff | raw | diff to current
2014-05-22 Matt ArsenaultR600: Implement ComputeNumSignBitsForTargetNode for BFE blob | commitdiff | raw | diff to current
2014-05-22 Matt ArsenaultR600: Implement computeMaskedBitsForTargetNode for BFE blob | commitdiff | raw | diff to current
2014-05-22 Matt ArsenaultR600: Add intrinsics for mad24 blob | commitdiff | raw | diff to current
2014-05-21 Matt ArsenaultR600: Add comment describing problems with LowerConstan... blob | commitdiff | raw | diff to current
2014-05-21 Matt ArsenaultR600: Partially fix constant initializers for structs... blob | commitdiff | raw | diff to current
2014-05-21 Matt ArsenaultUse cast<> instead of unchecked dyn_cast blob | commitdiff | raw | diff to current
2014-05-15 Matt ArsenaultUse range for blob | commitdiff | raw | diff to current
2014-05-14 Jay FoadRename ComputeMaskedBits to computeKnownBits. "Masked... blob | commitdiff | raw | diff to current
2014-05-12 Matt ArsenaultR600: Add mul24 intrinsics blob | commitdiff | raw | diff to current
2014-05-11 Matt ArsenaultFix return before else blob | commitdiff | raw | diff to current
2014-05-09 Tom StellardR600: Expand i64 SELECT_CC blob | commitdiff | raw | diff to current
2014-05-09 Tom StellardR600: Move MIN/MAX matching from LowerOperation() to... blob | commitdiff | raw | diff to current
2014-05-08 Matt ArsenaultR600: Promote f64 vector load/stores to i64 for consistency blob | commitdiff | raw | diff to current
2014-05-05 Tom StellardR600: Expand i64 ISD:SUB blob | commitdiff | raw | diff to current
2014-05-02 Tom StellardR600: Expand vector sin and cos. blob | commitdiff | raw | diff to current
2014-05-02 Tom StellardR600: Expand TruncStore i64 -> {i16,i8} blob | commitdiff | raw | diff to current
2014-04-29 Tom StellardR600: optimize the UDIVREM 64 algorithm blob | commitdiff | raw | diff to current
2014-04-29 Tom StellardR600: Implement iterative algorithm for udivrem blob | commitdiff | raw | diff to current
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