Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
[oota-llvm.git] / lib / Target / Hexagon / HexagonInstrInfo.td
2014-11-26 Craig TopperReplace neverHasSideEffects=1 with hasSideEffects=0...
2014-11-25 Colin LeMahieu[Hexagon] Adding add64 and sub64 instructions.
2014-11-25 Colin LeMahieuReverting 222792
2014-11-25 Colin LeMahieu[Hexagon] Adding compare with immediate instructions.
2014-11-25 Colin LeMahieu[Hexagon] Adding NOP encoding bits.
2014-11-25 Colin LeMahieu[Hexagon] Adding C2_mux instruction.
2014-11-25 Colin LeMahieu[Hexagon] Replacing cmp* instructions with ones that...
2014-11-24 Colin LeMahieu[Hexagon] Adding asrh instruction, removing unused...
2014-11-24 Colin LeMahieu[Hexagon] Adding aslh instruction.
2014-11-24 Colin LeMahieu[Hexagon] Adding zxth instruction.
2014-11-24 Colin LeMahieu[Hexagon] Adding zxtb instruction.
2014-11-21 Colin LeMahieu[Hexagon] Adding sxth instruction.
2014-11-21 Colin LeMahieu[Hexagon] Adding sxtb instruction. Renaming some ident...
2014-11-21 Colin LeMahieu[Hexagon] Removing SUB_rr and replacing with A2_sub.
2014-11-19 Colin LeMahieu[Hexagon] Adding A2_xor instruction with IR selection...
2014-11-19 Colin LeMahieu[Hexagon] Adding A2_or instruction with IR selection...
2014-11-18 Colin LeMahieu[Hexagon] Adding A2_and instruction.
2014-11-18 Colin LeMahieu[Hexagon] Adding A2_sub instruction
2014-11-18 Colin LeMahieu[Hexagon] Converting from ADD_rr to A2_add which has...
2014-11-04 Colin LeMahieu[Hexagon] Reverting 220584 to address ASAN errors.
2014-10-24 Colin LeMahieu[Hexagon] Resubmission of 220427
2014-10-23 NAKAMURA TakumiRevert r220427, "[Hexagon] Adding encoding bits for...
2014-10-22 Colin LeMahieu[Hexagon] Adding encoding bits for add opcode.
2014-10-22 Colin LeMahieu[Hexagon] Adding basic disassembler.
2014-05-07 Jyotsna Verma[Hexagon] Add New TSFlags to be used in the upcoming...
2013-05-14 Jyotsna VermaHexagon: Pass to replace tranfer/copy instructions...
2013-05-07 Jyotsna VermaHexagon: Set accessSize and addrMode on all load/store...
2013-05-02 Pranav BhandarkarHexagon - Add peephole optimizations for zero extends.
2013-05-01 Jyotsna VermaHexagon: Use multiclass for Jump instructions.
2013-04-23 Jyotsna VermaHexagon: Use multiclass for combine and STri[bhwd]_shl_...
2013-04-23 Jyotsna VermaHexagon: Remove assembler mapped instruction definitions.
2013-04-12 Jyotsna VermaHexagon: Set isPredicatedNew flag on predicate new...
2013-04-12 Jyotsna VermaHexagon: Set isPredicatedFlase flag for all the instruc...
2013-03-28 Jyotsna VermaHexagon: Replace switch-case in isDotNewInst with TSFlags.
2013-03-28 Jyotsna VermaHexagon: Use multiclass for gp-relative instructions.
2013-03-26 Jyotsna VermaHexagon: Use multiclass for aslh, asrh, sxtb, sxth...
2013-03-08 Jyotsna VermaHexagon: Add patterns for zero extended loads from...
2013-03-07 Jyotsna VermaHexagon: Add support to lower block address.
2013-03-05 Jyotsna Vermareverting patch 176508.
2013-03-05 Jyotsna VermaHexagon: Add support for lowering block address.
2013-03-05 Jyotsna VermaHexagon: Add encoding bits to the TFR64 instructions.
2013-02-14 Jyotsna VermaHexagon: Change insn class to support instruction encoding.
2013-02-05 Jakob Stoklund OlesenMove MRI liveouts to Hexagon return instructions.
2013-02-04 Jyotsna VermaHexagon: Add V4 combine instructions and some more...
2013-01-29 Jyotsna VermaUse multiclass for post-increment store instructions.
2013-01-29 Jyotsna VermaAdd constant extender support for MInst type instructions.
2013-01-07 Craig TopperRemove more unnecessary # operators with nothing to...
2013-01-07 Craig TopperRemove # from the beginning and end of def names. The...
2012-12-20 Jyotsna VermaAdd constant extender support to GP-relative load/store...
2012-12-04 Jyotsna VermaAdd patterns to define 'combine', 'tstbit', 'ct0/cl0...
2012-12-04 Jyotsna VermaAdd constant extender support to ALU32 instructions...
2012-12-04 Jyotsna VermaMove all operand definitions into HexagonOperands.td
2012-12-04 Jyotsna VermaMove generic Hexagon subtarget information into Hexagon.td
2012-12-03 Jyotsna VermaDefine store instructions with base+immediate offset...
2012-12-03 Jyotsna VermaDefine load instructions with base+immediate offset...
2012-11-30 Jyotsna VermaUse multiclass for the load instructions with MEMri...
2012-11-30 Jyotsna VermaUse multiclass for the store instructions with MEMri...
2012-11-29 Jyotsna VermaUse multiclass for 'transfer' instructions.
2012-11-21 Jyotsna VermaRenamed HexagonImmediates.td -> HexagonOperands.td.
2012-11-14 Jyotsna VermaAdded multiclass for post-increment load instructions.
2012-11-13 Jyotsna VermaTest commit.
2012-11-01 Pranav BhandarkarUse the relationship models infrastructure to add two...
2012-08-13 Arnold Schwaighofer[Hexagon] Don't mark callee saved registers as clobbere...
2012-07-13 Jakob Stoklund OlesenRemove variable_ops from call instructions in most...
2012-06-02 Benjamin KramerFix typos found by github.com/lyda/misspell-check
2012-05-14 Brendon CahoonRevert 156634 upon request until code improvement chang...
2012-05-11 Brendon CahoonHexagon constant extender support.
2012-05-10 Sirish PandeHexagon V5 FP Support.
2012-05-03 Sirish PandeExtensions of Hexagon V4 instructions.
2012-04-23 Chandler CarruthRevert r155365, r155366, and r155367. All three of...
2012-04-23 Sirish PandeHexagon V5 (floating point) support.
2012-04-23 Sirish PandeSupport for Hexagon architectural feature, new value...
2012-04-23 Sirish PandeSupport for Hexagon VLIW Packetizer.
2012-04-18 Chandler CarruthThis reverts a long string of commits to the Hexagon...
2012-04-16 Sirish PandeHexagon V5 (Floating Point) Support.
2012-04-13 Sirish PandeAdd support for Hexagon Architectural feature, New...
2012-04-13 Sirish PandePass to replace tranfer/copy instructions into combine...
2012-04-12 Sirish PandeHexagonPacketizer patch.
2012-04-12 Evandro MenezesHexagon: enable assembler output through the MC layer.
2012-02-22 Sirish PandeEfficient pattern for store truncate. Patch by Evandro...
2012-02-15 Sirish PandeOptimize redundant sign extends and negation of predicates.
2012-02-15 Eric ChristopherRevert "Optimize redundant sign extends and negation...
2012-02-15 Sirish PandeOptimize redundant sign extends and negation of predicates
2012-02-08 Brendon CahoonUse TSFlag bit to describe instruction properties.
2011-12-12 Tony LinthicumHexagon backend support