Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC...
[oota-llvm.git] / lib / Target / ARM / ARMInstrThumb.td
2012-02-18 Jia LiuEmacs-tag and some comment fix for all ARM, CellSPU...
2012-02-09 James MolloyTeach the MC and disassembler about SoftFail, and hook...
2012-01-18 Jim GrosbachRename pattern for clarity.
2012-01-13 Jakob Stoklund OlesenUse RegisterTuples to generate pseudo-registers.
2011-12-22 Bob WilsonAdd variants of the dispatchsetup pseudo for Thumb...
2011-12-20 Evan ChengARM target code clean up. Check for iOS, not Darwin...
2011-12-13 Jim GrosbachARM pre-UAL NEG mnemonic for convenience when porting...
2011-10-17 Bill WendlingNow Igor, throw the switch...give my creation life!
2011-10-15 Jakob Stoklund OlesenMark tADDrSPi as having side effects again.
2011-10-14 Jakob Stoklund OlesenBan rematerializable instructions with side effects.
2011-09-20 Jim GrosbachThumb1 convenience aliases for disassembler round-trip...
2011-09-20 Jim GrosbachThumb CPS definition is not disassembler only.
2011-09-16 Jim GrosbachThumb2 assembly parsing and encoding for SUB(immediate).
2011-09-15 Eli FriedmanUse a more efficient lowering for Unordered/Monotonic...
2011-09-09 Owen AndersonThumb unconditional branches are allowed in IT blocks...
2011-08-24 Jim GrosbachThumb parsing and encoding for SUB (SP minu immediate).
2011-08-24 Jim GrosbachThumb parsing and encoding support for ADD SP instructions.
2011-08-24 Jim GrosbachAdd missing explicit writeback operand to tSTMIA_UPD.
2011-08-24 Jim GrosbachThumb add SP assembly syntax fix.
2011-08-24 Jim GrosbachThumb1 ADD/SUB SP instructions are predicable in Thumb2...
2011-08-23 Jim GrosbachThumb parsing and encoding for SVC.
2011-08-23 Jim GrosbachThumb parsing and encoding for tSTRspi.
2011-08-23 Jim GrosbachClean up Thumb load/store multiple definitions.
2011-08-22 Jim GrosbachRevert r138278 now that r138289 has fixed the root...
2011-08-22 Jim GrosbachTemporarilly mark tMUL as not commutable.
2011-08-22 Jim GrosbachClean up predicates on ARM target instruction aliases.
2011-08-19 Jim GrosbachThumb parsing and encoding support for NOP.
2011-08-19 Jim GrosbachFix NEG alias
2011-08-19 Jim GrosbachUpdate tests.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for MUL.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for MOV.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LSL(immediate).
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRSB and LDRSH.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRH.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDRB.
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDR(immediate...
2011-08-19 Jim GrosbachThumb assembly parsing and encoding for LDR(immediate...
2011-08-19 Jim GrosbachAdd explanatory comment.
2011-08-18 Jim GrosbachThumb assembly parsing and encoding for LDM instruction.
2011-08-18 Jim GrosbachThumb assembly parsing and encoding for CMP.
2011-08-18 Jim GrosbachThumb instructions CBZ and CBNZ are Thumb2, not THumb1.
2011-08-18 Jim Grosbach80 columns.
2011-08-17 Jim GrosbachClean up patterns for Thumb1 system instructions.
2011-08-17 Jim GrosbachARM clean up the imm_sr operand class representation.
2011-08-17 Jim GrosbachThumb assembly parsing and encoding for ADR.
2011-08-16 Jim GrosbachThumb ADD(immediate) parsing support.
2011-08-15 Owen AndersonFix decoding LDRSB and LDRSH in Thumb1 mode. Patch...
2011-08-09 Owen AndersonReplace the existing ARM disassembler with a new one...
2011-08-08 Owen AndersonThumb1 BL instructions encoding 22 bits of displacement...
2011-08-08 Owen AndersonFix encodings for Thumb ASR and LSR immediate operands...
2011-08-03 Jim GrosbachARM refactoring assembly parsing of memory address...
2011-08-03 Owen AndersonFix broken encoding of tCBNZ.
2011-08-01 Jim GrosbachMove imm0_255 to ARMInstrInfo.td with the other immedia...
2011-07-26 Jim GrosbachARM parsing and encoding for SVC instruction.
2011-07-22 Jim GrosbachThumb assembly support for SETEND instruction.
2011-07-18 Owen AndersonRevamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD...
2011-07-18 Owen AndersonMark the Darwin assembler workout as isCodeGenOnly...
2011-07-18 Owen AndersonRe-apply r135319 with a fix for the constant island...
2011-07-16 Owen AndersonRevert r135319 in an attempt to get to unbreak testers.
2011-07-15 Owen AndersonGet rid of the separate opcodes for the Darwin versions...
2011-07-14 Benjamin KramerAdd OperandTypes for Thumb branch targets.
2011-07-13 Owen AndersonAdd a target-indepedent entry to MCInstrDesc to describ...
2011-07-13 Jim GrosbachRange checking for CDP[2] immediates.
2011-07-13 Jim GrosbachFix predicates for Thumb co-processor instructions.
2011-07-08 Jim GrosbachMark tBRIND as predicable.
2011-07-08 Jim GrosbachPseudo-ize tBRIND.
2011-07-08 Jim GrosbachMake tBX_RET and tBX_RET_vararg predicable.
2011-07-08 Jim GrosbachPseudo-ize tBX_RET and tBX_RET_vararg.
2011-07-08 Jim GrosbachShuffle productions around a bit.
2011-07-08 Jim GrosbachUse tPseudoExpand for tTAILJMPrND and tTAILJMPr.
2011-07-08 Jim GrosbachUse tPseudoExpand for tTAILJMPd and tTAILJMPdND.
2011-07-08 Jim GrosbachMove Thumb tail call pseudos to Thumb.td file.
2011-07-08 Jim GrosbachUse TableGen'erated pseudo lowering for ARM.
2011-07-01 Jim GrosbachPseudo-ize t2MOVCC[ri].
2011-06-30 Jim GrosbachRefact ARM Thumb1 tMOVr instruction family.
2011-06-30 Jim GrosbachThumb1 register to register MOV instruction is predicable.
2011-06-30 Jim GrosbachPseudo-ize the Thumb tTPsoft instruction.
2011-06-30 Jim GrosbachPseudo-ize the Thumb tPOP_RET instruction.
2011-06-29 Jim GrosbachRefactor away tSpill and tRestore pseudos in ARM backend.
2011-06-27 Jim GrosbachARM Assembly support for Thumb mov-immediate.
2011-06-21 Evan ChengTeach dag combine to match halfword byteswap patterns.
2011-06-13 Jim GrosbachClean up a few 80 column violations.
2011-06-07 Andrew TrickFix for setjmp/longjmp exception handling on ARM. setjm...
2011-05-27 Eric ChristopherMake the branch encoding for tBcc more obvious that...
2011-05-26 Cameron ZwarichMark tBX as an indirect branch rather than a return.
2011-05-25 Cameron ZwarichConvert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
2011-05-25 Cameron ZwarichMove some code to a more logical place.
2011-05-25 Cameron ZwarichChange the order of tBX's operands so that the predicat...
2011-05-25 Cameron ZwarichRename tBX_Rm to tBX.
2011-05-25 Cameron ZwarichRename the existing tBX/tBXr9 instructions to tBX_CALL...
2011-05-11 Owen AndersonFix encoding of Thumb BLX register instructions. Patch...
2011-05-03 Jakob Stoklund OlesenMark ultra-super-registers QQQQ as call-clobbered inste...
2011-05-03 Bruno Cardoso LopesFold ARM coprocessor intrinsics patterns into the instr...
2011-05-03 Bruno Cardoso LopesAdd a few ARM coprocessor intrinsics. Testcases included
2011-04-28 Eric ChristopherLet the immediate leaf pattern take transforms and...
2011-04-22 Johnny ChenDisassembly of A8.6.59 LDR (literal) Encoding T1 (16...
2011-04-15 Chris LattnerFix a ton of comment typos found by codespell. Patch by
2011-04-14 Evan ChengFollow up on r127913. Fix Thumb revsh isel. rdar:/...
2011-04-11 Johnny ChenThumb disassembler was erroneously rejecting "blx sp...
2011-03-22 Bruno Cardoso LopesChange MRC and MRC2 instructions to model the output...
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