From: Eric Christopher Date: Wed, 2 Jul 2014 21:29:23 +0000 (+0000) Subject: Move the data layout and selection dag info from the mips target machine X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=fddd7ad306090ff69f195d849455201ddc4fa516 Move the data layout and selection dag info from the mips target machine down to the subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212224 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 286d398e56a..ac0ffc75dc2 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -72,6 +72,36 @@ static StringRef selectMipsCPU(Triple TT, StringRef CPU) { void MipsSubtarget::anchor() { } +static std::string computeDataLayout(const MipsSubtarget &ST) { + std::string Ret = ""; + + // There are both little and big endian mips. + if (ST.isLittle()) + Ret += "e"; + else + Ret += "E"; + + Ret += "-m:m"; + + // Pointers are 32 bit on some ABIs. + if (!ST.isABI_N64()) + Ret += "-p:32:32"; + + // 8 and 16 bit integers only need no have natural alignment, but try to + // align them to 32 bits. 64 bit integers have natural alignment. + Ret += "-i8:8:32-i16:16:32-i64:64"; + + // 32 bit registers are always available and the stack is at least 64 bit + // aligned. On N64 64 bit registers are also available and the stack is + // 128 bit aligned. + if (ST.isABI_N64() || ST.isABI_N32()) + Ret += "-n32:64-S128"; + else + Ret += "-n32-S64"; + + return Ret; +} + MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little, Reloc::Model _RM, MipsTargetMachine *_TM) @@ -83,10 +113,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), - RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), JITInfo() { + RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT), + DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS))), + TSInfo(DL), JITInfo() { - initializeSubtargetDependencies(CPU, FS); - if (InMips16Mode && !TM->Options.UseSoftFloat) { // Hard float for mips16 means essentially to compile as soft float // but to use a runtime library for soft float that is written with diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 8aa390bbe59..d02a3ed6a87 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -15,6 +15,8 @@ #define MIPSSUBTARGET_H #include "MipsJITInfo.h" +#include "MipsSelectionDAGInfo.h" +#include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetSubtargetInfo.h" @@ -134,7 +136,10 @@ protected: Triple TargetTriple; + const DataLayout DL; // Calculates type size & alignment + const MipsSelectionDAGInfo TSInfo; MipsJITInfo JITInfo; + public: bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, AntiDepBreakMode& Mode, @@ -255,6 +260,8 @@ public: bool systemSupportsUnalignedAccess() const { return hasMips32r6(); } MipsJITInfo *getJITInfo() { return &JITInfo; } + const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } + const DataLayout *getDataLayout() const { return &DL; } }; } // End llvm namespace diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index e6b077ec008..c38639eadcb 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -45,36 +45,6 @@ extern "C" void LLVMInitializeMipsTarget() { RegisterTargetMachine B(TheMips64elTarget); } -static std::string computeDataLayout(const MipsSubtarget &ST) { - std::string Ret = ""; - - // There are both little and big endian mips. - if (ST.isLittle()) - Ret += "e"; - else - Ret += "E"; - - Ret += "-m:m"; - - // Pointers are 32 bit on some ABIs. - if (!ST.isABI_N64()) - Ret += "-p:32:32"; - - // 8 and 16 bit integers only need no have natural alignment, but try to - // align them to 32 bits. 64 bit integers have natural alignment. - Ret += "-i8:8:32-i16:16:32-i64:64"; - - // 32 bit registers are always available and the stack is at least 64 bit - // aligned. On N64 64 bit registers are also available and the stack is - // 128 bit aligned. - if (ST.isABI_N64() || ST.isABI_N32()) - Ret += "-n32:64-S128"; - else - Ret += "-n32-S64"; - - return Ret; -} - // On function prologue, the stack is created by decrementing // its pointer. Once decremented, all references are done with positive // offset from the stack/frame pointer, using StackGrowsUp enables @@ -87,9 +57,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), Subtarget(TT, CPU, FS, isLittle, RM, this), - DL(computeDataLayout(Subtarget)), InstrInfo(MipsInstrInfo::create(*this)), + InstrInfo(MipsInstrInfo::create(*this)), FrameLowering(MipsFrameLowering::create(*this, Subtarget)), - TLInfo(MipsTargetLowering::create(*this)), TSInfo(DL) { + TLInfo(MipsTargetLowering::create(*this)) { initAsmInfo(); } diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index 79e7e1d3c72..21950c71916 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -17,11 +17,9 @@ #include "MipsFrameLowering.h" #include "MipsISelLowering.h" #include "MipsInstrInfo.h" -#include "MipsSelectionDAGInfo.h" #include "MipsSubtarget.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/SelectionDAGISel.h" -#include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" @@ -31,7 +29,6 @@ class MipsRegisterInfo; class MipsTargetMachine : public LLVMTargetMachine { MipsSubtarget Subtarget; - const DataLayout DL; // Calculates type size & alignment std::unique_ptr InstrInfo; std::unique_ptr FrameLowering; std::unique_ptr TLInfo; @@ -41,7 +38,6 @@ class MipsTargetMachine : public LLVMTargetMachine { std::unique_ptr InstrInfoSE; std::unique_ptr FrameLoweringSE; std::unique_ptr TLInfoSE; - MipsSelectionDAGInfo TSInfo; public: MipsTargetMachine(const Target &T, StringRef TT, @@ -60,8 +56,6 @@ public: { return FrameLowering.get(); } const MipsSubtarget *getSubtargetImpl() const override { return &Subtarget; } - const DataLayout *getDataLayout() const override - { return &DL;} const InstrItineraryData *getInstrItineraryData() const override { return Subtarget.inMips16Mode() @@ -81,8 +75,11 @@ public: return TLInfo.get(); } + const DataLayout *getDataLayout() const override { + return getSubtargetImpl()->getDataLayout(); + } const MipsSelectionDAGInfo* getSelectionDAGInfo() const override { - return &TSInfo; + return getSubtargetImpl()->getSelectionDAGInfo(); } // Pass Pipeline Configuration