From: Dale Johannesen Date: Fri, 13 Jul 2007 17:13:54 +0000 (+0000) Subject: Skeleton of post-RA scheduler; doesn't do anything yet. X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=e7e7d0d7e39d0c7c659d26b97e8081fce0fcd749 Skeleton of post-RA scheduler; doesn't do anything yet. Change name of -sched option and DEBUG_TYPE to pre-RA-sched; adjust testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39816 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 32d696e2c1b..eda6a5dc8b4 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -89,6 +89,9 @@ namespace llvm { /// FunctionPass *createPrologEpilogCodeInserter(); + /// createPostRAScheduler - under development. + FunctionPass *createPostRAScheduler(); + /// BranchFolding Pass - This pass performs machine code CFG based /// optimizations to delete branches to branches, eliminate branches to /// successor blocks (creating fall throughs), and eliminating branches over diff --git a/lib/CodeGen/LLVMTargetMachine.cpp b/lib/CodeGen/LLVMTargetMachine.cpp index 4e3982df62a..b50b2753922 100644 --- a/lib/CodeGen/LLVMTargetMachine.cpp +++ b/lib/CodeGen/LLVMTargetMachine.cpp @@ -78,6 +78,9 @@ LLVMTargetMachine::addPassesToEmitFile(FunctionPassManager &PM, // Insert prolog/epilog code. Eliminate abstract frame index references... PM.add(createPrologEpilogCodeInserter()); + // Second pass scheduler. + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); @@ -181,6 +184,9 @@ bool LLVMTargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM, if (PrintMachineCode) // Print the register-allocated code PM.add(createMachineFunctionPrinterPass(cerr)); + // Second pass scheduler. + PM.add(createPostRAScheduler()); + // Branch folding must be run after regalloc and prolog/epilog insertion. if (!Fast) PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp new file mode 100644 index 00000000000..3708f56be0c --- /dev/null +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -0,0 +1,81 @@ +//===----- SchedulePostRAList.cpp - list scheduler ----===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by Dale Johannesen and is distributed under the +// University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This implements a top-down list scheduler, using standard algorithms. +// The basic approach uses a priority queue of available nodes to schedule. +// One at a time, nodes are taken from the priority queue (thus in priority +// order), checked for legality to schedule, and emitted if legal. +// +// Nodes may not be legal to schedule either due to structural hazards (e.g. +// pipeline or resource constraints) or because an input to the instruction has +// not completed execution. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "post-RA-sched" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/Support/Debug.h" +//#include "llvm/ADT/Statistic.h" +//#include +//#include +#include "llvm/Support/CommandLine.h" +using namespace llvm; + +namespace { + bool NoPostRAScheduling; + + // When this works it will be on by default. + cl::opt + DisablePostRAScheduler("disable-post-RA-scheduler", + cl::desc("Disable scheduling after register allocation"), + cl::location(NoPostRAScheduling), + cl::init(true)); + + class VISIBILITY_HIDDEN SchedulePostRATDList : public MachineFunctionPass { + public: + static char ID; + SchedulePostRATDList() : MachineFunctionPass((intptr_t)&ID) {} + private: + MachineFunction *MF; + const TargetMachine *TM; + public: + const char *getPassName() const { + return "Post RA top-down list latency scheduler (STUB)"; + } + + bool runOnMachineFunction(MachineFunction &Fn); + }; + char SchedulePostRATDList::ID = 0; +} + +bool SchedulePostRATDList::runOnMachineFunction(MachineFunction &Fn) { + if (NoPostRAScheduling) + return true; + + DOUT << "SchedulePostRATDList\n"; + MF = &Fn; + TM = &MF->getTarget(); + + // Loop over all of the basic blocks + for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end(); + MBB != MBBe; ++MBB) + ; + + return true; +} + + +//===----------------------------------------------------------------------===// +// Public Constructor Functions +//===----------------------------------------------------------------------===// + +FunctionPass *llvm::createPostRAScheduler() { + return new SchedulePostRATDList(); +} diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index 2252e7dcd79..06b23296589 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -13,7 +13,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sched" +#define DEBUG_TYPE "pre-RA-sched" #include "llvm/Type.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/MachineConstantPool.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp index dbbf3f94fb7..9e4e46f1cc7 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp @@ -18,7 +18,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sched" +#define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAGISel.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 51831ff75a8..f95be7dff9c 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -15,7 +15,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sched" +#define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SSARegMap.h" diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp index 9e44fcee254..62854f76f95 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp @@ -13,7 +13,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sched" +#define DEBUG_TYPE "pre-RA-sched" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/CodeGen/SchedulerRegistry.h" diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 373bce559d6..87bf2497640 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -73,9 +73,9 @@ MachinePassRegistry RegisterScheduler::Registry; namespace { cl::opt > - ISHeuristic("sched", + ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), - cl::desc("Instruction schedulers available:")); + cl::desc("Instruction schedulers available (before register allocation):")); static RegisterScheduler defaultListDAGScheduler("default", " Best scheduler for the target", diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 52f8ca7b592..26e1f47226a 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "sched" +#define DEBUG_TYPE "pre-RA-sched" #include "PPCHazardRecognizers.h" #include "PPC.h" #include "PPCInstrInfo.h" diff --git a/test/CodeGen/Generic/2006-07-03-schedulers.ll b/test/CodeGen/Generic/2006-07-03-schedulers.ll index 70fc0731298..6edb7a05999 100644 --- a/test/CodeGen/Generic/2006-07-03-schedulers.ll +++ b/test/CodeGen/Generic/2006-07-03-schedulers.ll @@ -1,10 +1,10 @@ -; RUN: llvm-upgrade %s | llvm-as | llc -sched=none -; RUN: llvm-upgrade %s | llvm-as | llc -sched=default -; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple -; RUN: llvm-upgrade %s | llvm-as | llc -sched=simple-noitin -; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-td -; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-tdrr -; RUN: llvm-upgrade %s | llvm-as | llc -sched=list-burr +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=none +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=default +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=simple-noitin +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-td +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-tdrr +; RUN: llvm-upgrade %s | llvm-as | llc -pre-RA-sched=list-burr ; PR859 implementation diff --git a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll index bdef507f93c..7e77cce41e7 100644 --- a/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll +++ b/test/CodeGen/X86/2007-01-13-StackPtrIndex.ll @@ -1,5 +1,5 @@ -; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | grep leaq -; RUN: llvm-as < %s | llc -march=x86-64 -sched=none | not grep {,%rsp)} +; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | grep leaq +; RUN: llvm-as < %s | llc -march=x86-64 -pre-RA-sched=none | not grep {,%rsp)} ; PR1103 target datalayout = "e-p:64:64"