From: Venkatraman Govindaraju Date: Mon, 3 Jun 2013 05:58:33 +0000 (+0000) Subject: Sparc: Add support for indirect branch and blockaddress in Sparc backend. X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=e7cbb792c95cb27a9704551579da19ebcaa06cdb Sparc: Add support for indirect branch and blockaddress in Sparc backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 108eb904790..412442974e0 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -120,6 +120,9 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, case MachineOperand::MO_GlobalAddress: O << *Mang->getSymbol(MO.getGlobal()); break; + case MachineOperand::MO_BlockAddress: + O << GetBlockAddressSymbol(MO.getBlockAddress())->getName(); + break; case MachineOperand::MO_ExternalSymbol: O << MO.getSymbolName(); break; diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 140efc3a53f..1aede443ab1 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -1258,6 +1258,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); + setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); // Sparc doesn't have sext_inreg, replace them with shl/sra setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); @@ -1460,6 +1461,12 @@ SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, CP->getAlignment(), CP->getOffset(), TF); + if (const BlockAddressSDNode *BA = dyn_cast(Op)) + return DAG.getTargetBlockAddress(BA->getBlockAddress(), + Op.getValueType(), + 0, + TF); + if (const ExternalSymbolSDNode *ES = dyn_cast(Op)) return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0), TF); @@ -1530,6 +1537,11 @@ SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, return makeAddress(Op, DAG); } +SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, + SelectionDAG &DAG) const { + return makeAddress(Op, DAG); +} + static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { SDLoc dl(Op); // Convert the fp value to integer in an FP register. @@ -1752,6 +1764,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for Sparc."); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); + case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index 0a75069d3d1..71371716e11 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -120,6 +120,7 @@ namespace llvm { SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; unsigned getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const; SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 45ff113b72c..8f01d83f23e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -516,6 +516,20 @@ let isBarrier = 1 in "ba $dst", [(br bb:$dst)]>; +//Indirect Branch +let isTerminator = 1, isBarrier = 1, + hasDelaySlot = 1, isBranch =1, + isIndirectBranch = 1 in { + def BINDrr : F3_1<2, 0b111000, + (outs), (ins MEMrr:$ptr), + "jmp $ptr", + [(brind ADDRrr:$ptr)]>; + def BINDri : F3_2<2, 0b111000, + (outs), (ins MEMri:$ptr), + "jmp $ptr", + [(brind ADDRri:$ptr)]>; +} + // FIXME: the encoding for the JIT should look at the condition field. let Uses = [ICC] in def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), @@ -793,9 +807,15 @@ def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; +// Blockaddress +def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; +def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; + // Add reg, lo. This is used when taking the addr of a global/constpool entry. def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; +def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), + (ADDri $r, tblockaddress:$in)>; // Calls: def : Pat<(call tglobaladdr:$dst), diff --git a/test/CodeGen/SPARC/blockaddr.ll b/test/CodeGen/SPARC/blockaddr.ll new file mode 100644 index 00000000000..a7e85fe2d45 --- /dev/null +++ b/test/CodeGen/SPARC/blockaddr.ll @@ -0,0 +1,77 @@ +; RUN: llc < %s -march=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=medium | FileCheck --check-prefix=abs44 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=large | FileCheck --check-prefix=abs64 %s +; RUN: llc < %s -march=sparc -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v8pic32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v9pic32 %s + +; +; copied from test/CodeGen/Mips/blockaddr.ll and modified for SPARC +; +@reg = common global i8* null, align 4 + +define i8* @dummy(i8* %x) nounwind readnone noinline { +entry: + ret i8* %x +} + +; abs32: func_block_addr: +; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]] +; abs32: call dummy +; abs32: add [[R]], %lo([[BLK]]), %o0 +; abs32: jmp %o0 + +; abs44: func_block_addr: +; abs44: sethi %h44([[BLK:.+]]), [[R:%[gilo][0-7]]] +; abs44: add [[R]], %m44([[BLK]]), [[R1:%[gilo][0-7]]] +; abs44: sllx [[R1]], 12, [[R2:%[gilo][0-7]]] +; abs44: call dummy +; abs44: add [[R2]], %l44([[BLK]]), %o0 +; abs44: jmp %o0 + +; abs64: func_block_addr: +; abs64: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]] +; abs64: add [[R]], %lo([[BLK]]), [[R1:%[gilo][0-7]]] +; abs64: sethi %hh([[BLK]]), [[R2:%[gilo][0-7]]] +; abs64: add [[R2]], %hm([[BLK]]), [[R3:%[gilo][0-7]]] +; abs64: sllx [[R3]], 32, [[R4:%[gilo][0-7]]] +; abs64: call dummy +; abs64: add [[R2]], [[R1]], %o0 +; abs64: jmp %o0 + + +; v8pic32: func_block_addr +; v8pic32: sethi %hi(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R:%[gilo][0-7]]] +; v8pic32: or [[R]], %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R1:%[gilo][0-7]]] +; v8pic32: add [[R1]], %o7, %[[R2:[gilo][0-7]]] +; v8pic32: sethi %hi([[BLK:.+]]), [[R3:%[gilo][0-7]]] +; v8pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]] +; v8pic32: call dummy +; v8pic32: ld [%[[R2]]+%[[R4]]], %o0 +; v8pic32: jmp %o0 + + +; v9pic32: func_block_addr +; v9pic32: sethi %hi(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R:%[gilo][0-7]]] +; v9pic32: or [[R]], %lo(_GLOBAL_OFFSET_TABLE_+{{.+}}), [[R1:%[gilo][0-7]]] +; v9pic32: add [[R1]], %o7, %[[R2:[gilo][0-7]]] +; v9pic32: sethi %hi([[BLK:.+]]), [[R3:%[gilo][0-7]]] +; v9pic32: add [[R3]], %lo([[BLK]]), %[[R4:[gilo][0-7]]] +; v9pic32: call dummy +; v9pic32: ldx [%[[R2]]+%[[R4]]], %o0 +; v9pic32: jmp %o0 + + +define void @func_block_addr() nounwind { +entry: + %call = tail call i8* @dummy(i8* blockaddress(@func_block_addr, %baz)) + indirectbr i8* %call, [label %baz, label %foo] + +foo: ; preds = %foo, %entry + store i8* blockaddress(@func_block_addr, %foo), i8** @reg, align 4 + br label %foo + +baz: ; preds = %entry + store i8* null, i8** @reg, align 4 + ret void +}