From: Adam Nemet <anemet@apple.com>
Date: Tue, 5 Aug 2014 17:58:49 +0000 (+0000)
Subject: [X86] Improve comments for r214888
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=c64a05905a19841ca8df90f6c12f2693a7fd7f05

[X86] Improve comments for r214888

A rebase somehow ate my comments. This restores them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214903 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c92fc8460bc..a3cd02f44b2 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3803,6 +3803,9 @@ static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
   return true;
 }
 
+/// \brief Return true if the mask specifies a shuffle of elements that is
+/// suitable for input to intralane (palignr) or interlane (valign) vector
+/// right-shift.
 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
   unsigned NumElts = VT.getVectorNumElements();
   unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
@@ -3869,8 +3872,8 @@ static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
   return true;
 }
 
-/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
-/// is suitable for input to PALIGNR.
+/// \brief Return true if the node specifies a shuffle of elements that is
+/// suitable for input to PALIGNR.
 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
                           const X86Subtarget *Subtarget) {
   if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
@@ -3881,8 +3884,8 @@ static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
   return isAlignrMask(Mask, VT, false);
 }
 
-/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
-/// is suitable for input to PALIGNR.
+/// \brief Return true if the node specifies a shuffle of elements that is
+/// suitable for input to VALIGN.
 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
                           const X86Subtarget *Subtarget) {
   // FIXME: Add AVX512VL.
@@ -4715,8 +4718,9 @@ static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
   return Mask;
 }
 
-/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
-/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
+/// \brief Return the appropriate immediate to shuffle the specified
+/// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
+/// VALIGN (if Interlane is true) instructions.
 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
                                            bool InterLane) {
   MVT VT = SVOp->getSimpleValueType(0);
@@ -4741,12 +4745,14 @@ static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
   return (Val - i) * EltSize;
 }
 
-/// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
-/// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
+/// \brief Return the appropriate immediate to shuffle the specified
+/// VECTOR_SHUFFLE mask with the PALIGNR instruction.
 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
   return getShuffleAlignrImmediate(SVOp, false);
 }
 
+/// \brief Return the appropriate immediate to shuffle the specified
+/// VECTOR_SHUFFLE mask with the VALIGN instruction.
 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
   return getShuffleAlignrImmediate(SVOp, true);
 }