From: Juergen Ributzka Date: Mon, 15 Sep 2014 23:47:57 +0000 (+0000) Subject: [FastISel][AArch64] Add missing test case for previous commit. X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=c0f00e90d2a7e8cfd0996fecea6710fc67c36972 [FastISel][AArch64] Add missing test case for previous commit. This adds the missing test case for the previous commit: Allow handling of vectors during return lowering for little endian machines. Sorry for the noise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217847 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/test/CodeGen/AArch64/fast-isel-vret.ll b/test/CodeGen/AArch64/fast-isel-vret.ll new file mode 100644 index 00000000000..9ad92273d3a --- /dev/null +++ b/test/CodeGen/AArch64/fast-isel-vret.ll @@ -0,0 +1,9 @@ +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s + +; Test that we don't abort fast-isle for ret +define <8 x i8> @ret_v8i8(<8 x i8> %a, <8 x i8> %b) { +; CHECK-LABEL: ret_v8i8 +; CHECK: add.8b v0, v0, v1 + %1 = add <8 x i8> %a, %b + ret <8 x i8> %1 +}