From: Hans Wennborg Date: Thu, 4 Jun 2015 15:55:00 +0000 (+0000) Subject: Switch lowering: fix assert in buildBitTests (PR23738) X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=bebb0b5a34919d393c1d55d8e76580cbfe8d2895;ds=sidebyside Switch lowering: fix assert in buildBitTests (PR23738) When checking (High - Low + 1).sle(BitWidth), BitWidth would be truncated to the size of the left-hand side. In the case of this PR, the left-hand side was i4, so BitWidth=64 got truncated to 0 and the assert failed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239048 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 6b366cc4af6..a07a024557c 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7614,7 +7614,8 @@ bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters, const int BitWidth = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits(); - assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!"); + uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1; + assert(Range <= (uint64_t)BitWidth && "Case range must fit in bit mask!"); if (Low.isNonNegative() && High.slt(BitWidth)) { // Optimize the case where all the case values fit in a diff --git a/test/CodeGen/X86/switch.ll b/test/CodeGen/X86/switch.ll index 66a739c8470..a4dece65479 100644 --- a/test/CodeGen/X86/switch.ll +++ b/test/CodeGen/X86/switch.ll @@ -534,3 +534,18 @@ return: ret void ; CHECK-NOT: cmpl ; CHECK: cmpl $99 } + + +define void @pr23738(i4 %x) { +entry: + switch i4 %x, label %bb0 [ + i4 0, label %bb1 + i4 1, label %bb1 + i4 -5, label %bb1 + ] +bb0: tail call void @g(i32 0) br label %return +bb1: tail call void @g(i32 1) br label %return +return: ret void +; Don't assert due to truncating the bitwidth (64) to i4 when checking +; that the bit-test range fits in a word. +}