From: Torok Edwin Date: Wed, 8 Jul 2009 18:01:40 +0000 (+0000) Subject: Start converting to new error handling API. X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=ab7c09b6b6f4516a631fd6788918c237c83939af Start converting to new error handling API. cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Support/ErrorHandling.h b/include/llvm/Support/ErrorHandling.h index fae7d8094b0..a65fbe69742 100644 --- a/include/llvm/Support/ErrorHandling.h +++ b/include/llvm/Support/ErrorHandling.h @@ -49,5 +49,7 @@ namespace llvm { void llvm_unreachable(void) NORETURN; } +#define LLVM_UNREACHABLE(msg) do { assert(0 && msg); llvm_unreachable(); } while(0); + #endif diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index c266d1aa944..3cefe437129 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -26,6 +26,7 @@ #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -69,8 +70,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) { case S30: return 30; case S31: return 31; default: - assert(0 && "Unknown ARM register!"); - abort(); + LLVM_UNREACHABLE("Unknown ARM register!"); } } @@ -81,8 +81,7 @@ unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum, using namespace ARM; switch (RegEnum) { default: - assert(0 && "Unknown ARM register!"); - abort(); + LLVM_UNREACHABLE("Unknown ARM register!"); case R0: case D0: return 0; case R1: case D1: return 1; case R2: case D2: return 2; diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index da7e85e5d06..f436e97bcc7 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -35,6 +35,8 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #ifndef NDEBUG #include #endif @@ -221,7 +223,7 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) { template unsigned Emitter::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::asr: return 2; case ARM_AM::lsl: return 0; case ARM_AM::lsr: return 1; @@ -255,8 +257,10 @@ unsigned Emitter::getMachineOpValue(const MachineInstr &MI, else if (MO.isMBB()) emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); else { - cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "ERROR: Unknown type of MachineOperand: " << MO; + llvm_report_error(Msg.str()); } return 0; } @@ -336,7 +340,7 @@ void Emitter::emitInstruction(const MachineInstr &MI) { NumEmitted++; // Keep track of the # of mi's emitted switch (MI.getDesc().TSFlags & ARMII::FormMask) { default: { - assert(0 && "Unhandled instruction encoding format!"); + LLVM_UNREACHABLE("Unhandled instruction encoding format!"); break; } case ARMII::Pseudo: @@ -454,12 +458,10 @@ void Emitter::emitConstPoolInstruction(const MachineInstr &MI) { else if (CFP->getType() == Type::DoubleTy) emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); else { - assert(0 && "Unable to handle this constantpool entry!"); - abort(); + LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); } } else { - assert(0 && "Unable to handle this constantpool entry!"); - abort(); + LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); } } } @@ -586,13 +588,12 @@ void Emitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - abort(); // FIXME: + llvm_report_error("ARMCodeEmitter::emitPseudoInstruction");//FIXME: case TargetInstrInfo::INLINEASM: { // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. if (MI.getOperand(0).getSymbolName()[0]) { - assert(0 && "JIT does not support inline asm!\n"); - abort(); + llvm_report_error("JIT does not support inline asm!\n"); } break; } @@ -674,7 +675,7 @@ unsigned Emitter::getMachineSoRegOpValue( // ROR - 0111 // RRX - 0110 and bit[11:8] clear. switch (SOpc) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x1; break; case ARM_AM::lsr: SBits = 0x3; break; case ARM_AM::asr: SBits = 0x5; break; @@ -688,7 +689,7 @@ unsigned Emitter::getMachineSoRegOpValue( // ASR - 100 // ROR - 110 switch (SOpc) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x2; break; case ARM_AM::asr: SBits = 0x4; break; @@ -741,8 +742,7 @@ void Emitter::emitDataProcessingInstruction( const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::BFC) { - cerr << "ERROR: ARMv6t2 JIT is not yet supported.\n"; - abort(); + llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported."); } // Part of binary is determined by TableGn. @@ -956,7 +956,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) { // DA - Decrement after - bit U = 0 and bit P = 0 // DB - Decrement before - bit U = 0 and bit P = 1 switch (Mode) { - default: assert(0 && "Unknown addressing sub-mode!"); + default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); case ARM_AM::da: break; case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; @@ -1120,7 +1120,7 @@ void Emitter::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); if (TID.Opcode == ARM::TPsoft) - abort(); // FIXME + llvm_report_error("ARM::TPsoft FIXME"); // FIXME // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index b207bcc356d..2d29142e388 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -36,6 +36,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/VectorExtras.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" using namespace llvm; @@ -2258,7 +2259,7 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op) { SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (Op.getOpcode()) { - default: assert(0 && "Don't know how to custom lower this!"); abort(); + default: LLVM_UNREACHABLE("Don't know how to custom lower this!"); case ISD::ConstantPool: return LowerConstantPool(Op, DAG); case ISD::GlobalAddress: return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : @@ -2593,8 +2594,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vshiftlu: if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) break; - assert(0 && "invalid shift count for vshll intrinsic"); - abort(); + LLVM_UNREACHABLE("invalid shift count for vshll intrinsic"); case Intrinsic::arm_neon_vrshifts: case Intrinsic::arm_neon_vrshiftu: @@ -2611,8 +2611,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vqshiftsu: if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) break; - assert(0 && "invalid shift count for vqshlu intrinsic"); - abort(); + LLVM_UNREACHABLE("invalid shift count for vqshlu intrinsic"); case Intrinsic::arm_neon_vshiftn: case Intrinsic::arm_neon_vrshiftn: @@ -2625,8 +2624,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { // Narrowing shifts require an immediate right shift. if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) break; - assert(0 && "invalid shift count for narrowing vector shift intrinsic"); - abort(); + LLVM_UNREACHABLE("invalid shift count for narrowing vector shift intrinsic"); default: assert(0 && "unhandled vector shift"); @@ -2687,8 +2685,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) VShiftOpc = ARMISD::VSRI; else { - assert(0 && "invalid shift count for vsli/vsri intrinsic"); - abort(); + LLVM_UNREACHABLE("invalid shift count for vsli/vsri intrinsic"); } return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), diff --git a/lib/Target/ARM/ARMJITInfo.cpp b/lib/Target/ARM/ARMJITInfo.cpp index e551c41936f..bc28919817c 100644 --- a/lib/Target/ARM/ARMJITInfo.cpp +++ b/lib/Target/ARM/ARMJITInfo.cpp @@ -21,13 +21,14 @@ #include "llvm/CodeGen/JITCodeEmitter.h" #include "llvm/Config/alloca.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Streams.h" #include "llvm/System/Memory.h" #include using namespace llvm; void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { - abort(); + llvm_report_error("ARMJITInfo::replaceMachineCodeForFunction"); } /// JITCompilerFunction - This contains the address of the JIT function used to @@ -103,8 +104,7 @@ extern "C" { ); #else // Not an ARM host void ARMCompilationCallback() { - assert(0 && "Cannot call ARMCompilationCallback() on a non-ARM arch!\n"); - abort(); + LLVM_UNREACHABLE("Cannot call ARMCompilationCallback() on a non-ARM arch!\n"); } #endif } @@ -123,14 +123,12 @@ extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { // ldr pc, [pc,#-4] // if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { - cerr << "ERROR: Unable to mark stub writable\n"; - abort(); + llvm_report_error("ERROR: Unable to mark stub writable"); } *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] *(intptr_t *)(StubAddr+4) = NewVal; if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { - cerr << "ERROR: Unable to mark stub executable\n"; - abort(); + llvm_report_error("ERROR: Unable to mark stub executable"); } } diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 59cf125a9b9..d9e21b8e077 100644 --- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -29,6 +29,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallPtrSet.h" @@ -119,7 +120,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) { case ARM::FSTD: NumFSTMGened++; return ARM::FSTMD; - default: abort(); + default: llvm_report_error("Unhandled opcode!"); } return 0; } @@ -441,7 +442,7 @@ static unsigned getPreIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: abort(); + default: llvm_report_error("Unhandled opcode!"); } return 0; } @@ -454,7 +455,7 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) { case ARM::FLDD: return ARM::FLDMD; case ARM::FSTS: return ARM::FSTMS; case ARM::FSTD: return ARM::FSTMD; - default: abort(); + default: llvm_report_error("Unhandled opcode!"); } return 0; } diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 6b70abe3f9e..c6ac5b53bad 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -26,6 +26,7 @@ #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -290,8 +291,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - assert(0 && "Unsupported addressing mode!"); - abort(); + LLVM_UNREACHABLE("Unsupported addressing mode!"); break; } diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 92f01d1006d..7417e58b894 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -30,6 +30,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" using namespace llvm; static cl::opt @@ -452,8 +453,7 @@ void Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - assert(0 && "Unsupported addressing mode!"); - abort(); + LLVM_UNREACHABLE("Unsupported addressing mode!"); break; } diff --git a/lib/Target/ARM/Thumb2RegisterInfo.cpp b/lib/Target/ARM/Thumb2RegisterInfo.cpp index 0f0c0e41fc5..42d39a6f694 100644 --- a/lib/Target/ARM/Thumb2RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb2RegisterInfo.cpp @@ -30,6 +30,7 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" using namespace llvm; static cl::opt @@ -452,8 +453,7 @@ void Thumb2RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, break; } default: - assert(0 && "Unsupported addressing mode!"); - abort(); + llvm_report_error("Unsupported addressing mode!"); break; } diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index fa0ee753f02..4f7a00a7cc0 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -16,6 +16,7 @@ #include "llvm/MC/MCInst.h" #include "X86ATTAsmPrinter.h" #include "llvm/Target/TargetAsmInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -103,7 +104,7 @@ void X86ATTAsmPrinter::printLeaMemReference(const MCInst *MI, unsigned Op) { if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) O << DispVal; } else { - abort(); + llvm_report_error("non-immediate displacement for LEA?"); //assert(DispSpec.isGlobal() || DispSpec.isCPI() || // DispSpec.isJTI() || DispSpec.isSymbol()); //printOperand(MI, Op+3, "mem"); diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index fffbf1fcdcc..afb1e1dedeb 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -31,6 +31,8 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" using namespace llvm; @@ -556,8 +558,7 @@ void Emitter::emitInstruction( // We allow inline assembler nodes with empty bodies - they can // implicitly define registers, which is ok for JIT. if (MI.getOperand(0).getSymbolName()[0]) { - assert(0 && "JIT does not support inline asm!\n"); - abort(); + llvm_report_error("JIT does not support inline asm!"); } break; } @@ -805,10 +806,10 @@ void Emitter::emitInstruction( } if (!Desc->isVariadic() && CurOp != NumOps) { - cerr << "Cannot encode: "; - MI.dump(); - cerr << '\n'; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Cannot encode: " << MI; + llvm_report_error(Msg.str()); } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index fe60614beb8..4c2bc45098f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -33,6 +33,7 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/StringExtras.h" @@ -6054,8 +6055,7 @@ SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDValue SrcPtr = Op.getOperand(1); SDValue SrcSV = Op.getOperand(2); - assert(0 && "VAArgInst is not yet implemented for x86-64!"); - abort(); + LLVM_UNREACHABLE("VAArgInst is not yet implemented for x86-64!"); return SDValue(); } @@ -6256,7 +6256,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { case Intrinsic::x86_mmx_psrai_d: NewIntNo = Intrinsic::x86_mmx_psra_d; break; - default: abort(); // Can't reach here. + default: LLVM_UNREACHABLE("Impossible intrinsic"); // Can't reach here. } break; } @@ -6428,8 +6428,7 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; if (InRegCount > 2) { - cerr << "Nest register in use - reduce number of inreg parameters!\n"; - abort(); + llvm_report_error("Nest register in use - reduce number of inreg parameters!"); } } break; diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index e5d84c50778..b253146713e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -27,6 +27,8 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/LiveVariables.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetAsmInfo.h" using namespace llvm; @@ -1889,8 +1891,7 @@ static unsigned getStoreRegOpcode(unsigned SrcReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64mr; } else { - assert(0 && "Unknown regclass"); - abort(); + LLVM_UNREACHABLE("Unknown regclass"); } return Opc; @@ -1982,8 +1983,7 @@ static unsigned getLoadRegOpcode(unsigned DestReg, } else if (RC == &X86::VR64RegClass) { Opc = X86::MMX_MOVQ64rm; } else { - assert(0 && "Unknown regclass"); - abort(); + LLVM_UNREACHABLE("Unknown regclass"); } return Opc; @@ -3196,10 +3196,10 @@ static unsigned GetInstSizeWithDesc(const MachineInstr &MI, } if (!Desc->isVariadic() && CurOp != NumOps) { - cerr << "Cannot determine size: "; - MI.dump(); - cerr << '\n'; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Cannot determine size: " << MI; + llvm_report_error(Msg.str()); } diff --git a/lib/Target/X86/X86JITInfo.cpp b/lib/Target/X86/X86JITInfo.cpp index f92310607a8..eb09def0c12 100644 --- a/lib/Target/X86/X86JITInfo.cpp +++ b/lib/Target/X86/X86JITInfo.cpp @@ -18,6 +18,7 @@ #include "llvm/Function.h" #include "llvm/Config/alloca.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/ErrorHandling.h" #include #include using namespace llvm; @@ -321,8 +322,7 @@ extern "C" { #else // Not an i386 host void X86CompilationCallback() { - assert(0 && "Cannot call X86CompilationCallback() on a non-x86 arch!\n"); - abort(); + LLVM_UNREACHABLE("Cannot call X86CompilationCallback() on a non-x86 arch!\n"); } #endif } diff --git a/lib/VMCore/AsmWriter.cpp b/lib/VMCore/AsmWriter.cpp index cbf7070d17e..70c27eb5111 100644 --- a/lib/VMCore/AsmWriter.cpp +++ b/lib/VMCore/AsmWriter.cpp @@ -31,6 +31,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" #include @@ -1234,8 +1235,7 @@ static void PrintLinkage(GlobalValue::LinkageTypes LT, raw_ostream &Out) { case GlobalValue::ExternalWeakLinkage: Out << "extern_weak "; break; case GlobalValue::ExternalLinkage: break; case GlobalValue::GhostLinkage: - Out << "GhostLinkage not allowed in AsmWriter!\n"; - abort(); + llvm_report_error("GhostLinkage not allowed in AsmWriter!"); } } diff --git a/lib/VMCore/Globals.cpp b/lib/VMCore/Globals.cpp index c31b7b5e76c..f8c10710529 100644 --- a/lib/VMCore/Globals.cpp +++ b/lib/VMCore/Globals.cpp @@ -19,6 +19,7 @@ #include "llvm/LLVMContext.h" #include "llvm/Module.h" #include "llvm/ADT/SmallPtrSet.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LeakDetector.h" using namespace llvm; @@ -77,8 +78,7 @@ void GlobalValue::removeDeadConstantUsers() const { /// Override destroyConstant to make sure it doesn't get called on /// GlobalValue's because they shouldn't be treated like other constants. void GlobalValue::destroyConstant() { - assert(0 && "You can't GV->destroyConstant()!"); - abort(); + LLVM_UNREACHABLE("You can't GV->destroyConstant()!"); } /// copyAttributesFrom - copy all additional attributes (those not needed to @@ -247,7 +247,7 @@ const GlobalValue *GlobalAlias::getAliasedGlobal() const { CE->getOpcode() == Instruction::GetElementPtr)) return dyn_cast(CE->getOperand(0)); else - assert(0 && "Unsupported aliasee"); + LLVM_UNREACHABLE("Unsupported aliasee"); } } return 0; diff --git a/lib/VMCore/Instructions.cpp b/lib/VMCore/Instructions.cpp index 8d14766c21a..66269301847 100644 --- a/lib/VMCore/Instructions.cpp +++ b/lib/VMCore/Instructions.cpp @@ -16,6 +16,7 @@ #include "llvm/DerivedTypes.h" #include "llvm/Function.h" #include "llvm/Instructions.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/ConstantRange.h" #include "llvm/Support/MathExtras.h" @@ -534,12 +535,11 @@ unsigned ReturnInst::getNumSuccessorsV() const { /// Out-of-line ReturnInst method, put here so the C++ compiler can choose to /// emit the vtable for the class in this translation unit. void ReturnInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - assert(0 && "ReturnInst has no successors!"); + LLVM_UNREACHABLE("ReturnInst has no successors!"); } BasicBlock *ReturnInst::getSuccessorV(unsigned idx) const { - assert(0 && "ReturnInst has no successors!"); - abort(); + LLVM_UNREACHABLE("ReturnInst has no successors!"); return 0; } @@ -563,12 +563,11 @@ unsigned UnwindInst::getNumSuccessorsV() const { } void UnwindInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - assert(0 && "UnwindInst has no successors!"); + LLVM_UNREACHABLE("UnwindInst has no successors!"); } BasicBlock *UnwindInst::getSuccessorV(unsigned idx) const { - assert(0 && "UnwindInst has no successors!"); - abort(); + LLVM_UNREACHABLE("UnwindInst has no successors!"); return 0; } @@ -588,12 +587,11 @@ unsigned UnreachableInst::getNumSuccessorsV() const { } void UnreachableInst::setSuccessorV(unsigned idx, BasicBlock *NewSucc) { - assert(0 && "UnwindInst has no successors!"); + LLVM_UNREACHABLE("UnwindInst has no successors!"); } BasicBlock *UnreachableInst::getSuccessorV(unsigned idx) const { - assert(0 && "UnwindInst has no successors!"); - abort(); + LLVM_UNREACHABLE("UnwindInst has no successors!"); return 0; } @@ -2295,7 +2293,7 @@ CastInst::getCastOpcode( PTy = NULL; return BitCast; // same size, no-op cast } else { - assert(0 && "Casting pointer or non-first class to float"); + LLVM_UNREACHABLE("Casting pointer or non-first class to float"); } } else if (const VectorType *DestPTy = dyn_cast(DestTy)) { if (const VectorType *SrcPTy = dyn_cast(SrcTy)) { diff --git a/lib/VMCore/PassManager.cpp b/lib/VMCore/PassManager.cpp index 74c09fd865e..0878694b047 100644 --- a/lib/VMCore/PassManager.cpp +++ b/lib/VMCore/PassManager.cpp @@ -17,6 +17,7 @@ #include "llvm/Support/Timer.h" #include "llvm/Module.h" #include "llvm/ModuleProvider.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Streams.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/raw_ostream.h" @@ -1248,8 +1249,7 @@ void FunctionPassManager::add(Pass *P) { bool FunctionPassManager::run(Function &F) { std::string errstr; if (MP->materializeFunction(&F, &errstr)) { - cerr << "Error reading bitcode file: " << errstr << "\n"; - abort(); + llvm_report_error("Error reading bitcode file: " + errstr); } return FPM->run(F); } diff --git a/lib/VMCore/Type.cpp b/lib/VMCore/Type.cpp index b4152514970..432a1cca818 100644 --- a/lib/VMCore/Type.cpp +++ b/lib/VMCore/Type.cpp @@ -20,6 +20,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" @@ -264,10 +265,10 @@ const Type *Type::getForwardedTypeInternal() const { } void Type::refineAbstractType(const DerivedType *OldTy, const Type *NewTy) { - abort(); + llvm_report_error("Attempting to refine a derived type!"); } void Type::typeBecameConcrete(const DerivedType *AbsTy) { - abort(); + llvm_report_error("DerivedType is already a concrete type!"); } diff --git a/lib/VMCore/Value.cpp b/lib/VMCore/Value.cpp index e980a5d0ff2..8c5d551c15e 100644 --- a/lib/VMCore/Value.cpp +++ b/lib/VMCore/Value.cpp @@ -19,6 +19,7 @@ #include "llvm/Module.h" #include "llvm/ValueSymbolTable.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/LeakDetector.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/ValueHandle.h" @@ -514,8 +515,8 @@ void ValueHandleBase::ValueIsDeleted(Value *V) { cerr << "While deleting: " << *V->getType() << " %" << V->getNameStr() << "\n"; #endif - cerr << "An asserting value handle still pointed to this value!\n"; - abort(); + llvm_report_error("An asserting value handle still pointed to this" + "value!"); case Weak: // Weak just goes to null, which will unlink it from the list. ThisNode->operator=(0); diff --git a/lib/VMCore/Verifier.cpp b/lib/VMCore/Verifier.cpp index 10816e6248b..6674acb79de 100644 --- a/lib/VMCore/Verifier.cpp +++ b/lib/VMCore/Verifier.cpp @@ -62,6 +62,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Compiler.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -93,7 +94,7 @@ namespace { // Anonymous namespace for class } if (Broken) - abort(); + llvm_report_error("Broken module, no Basic Block terminator!"); return false; } @@ -210,8 +211,7 @@ namespace { default: assert(0 && "Unknown action"); case AbortProcessAction: msgs << "compilation aborted!\n"; - cerr << msgs.str(); - abort(); + llvm_report_error(msgs.str()); case PrintMessageAction: msgs << "verification continues.\n"; cerr << msgs.str();