From: Craig Topper <craig.topper@gmail.com>
Date: Sun, 11 Oct 2015 18:27:24 +0000 (+0000)
Subject: [X86] Remove special validation for INT immediate operand from AsmParser. Instead... 
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=a9d6f4a14a48b56b03019cce3386532d4110256d

[X86] Remove special validation for INT immediate operand from AsmParser. Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior.

This also fixes a bug where negative immediates below -128 were not being reported as errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249989 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 01c92c62224..c6bb895cdaf 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -718,7 +718,6 @@ private:
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
   bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
 
-  bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
   bool processInstruction(MCInst &Inst, const OperandVector &Ops);
 
   /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
@@ -2401,22 +2400,6 @@ static bool convert64i32to64ri8(MCInst &Inst, unsigned Opcode,
   return convertToSExti8(Inst, Opcode, X86::RAX, isCmp);
 }
 
-bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
-  switch (Inst.getOpcode()) {
-  default: return true;
-  case X86::INT:
-    X86Operand &Op = static_cast<X86Operand &>(*Ops[1]);
-    assert(Op.isImm() && "expected immediate");
-    int64_t Res;
-    if (!Op.getImm()->evaluateAsAbsolute(Res) || Res > 255) {
-      Error(Op.getStartLoc(), "interrupt vector must be in range [0-255]");
-      return false;
-    }
-    return true;
-  }
-  llvm_unreachable("handle the instruction appropriately");
-}
-
 bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
   switch (Inst.getOpcode()) {
   default: return false;
@@ -2579,9 +2562,6 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
                                isParsingIntelSyntax())) {
   default: llvm_unreachable("Unexpected match result!");
   case Match_Success:
-    if (!validateInstruction(Inst, Operands))
-      return true;
-
     // Some instructions need post-processing to, for example, tweak which
     // encoding is selected. Loop on it while changes happen so the
     // individual transformations can chain off each other.
@@ -2825,9 +2805,6 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
   unsigned NumSuccessfulMatches =
       std::count(std::begin(Match), std::end(Match), Match_Success);
   if (NumSuccessfulMatches == 1) {
-    if (!validateInstruction(Inst, Operands))
-      return true;
-
     // Some instructions need post-processing to, for example, tweak which
     // encoding is selected. Loop on it while changes happen so the individual
     // transformations can chain off each other.
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td
index 0350566f8b9..917ae32382a 100644
--- a/lib/Target/X86/X86InstrSystem.td
+++ b/lib/Target/X86/X86InstrSystem.td
@@ -44,7 +44,7 @@ def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
 
 let SchedRW = [WriteSystem] in {
 
-def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
+def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
               [(int_x86_int imm:$trap)], IIC_INT>;
 
 
diff --git a/test/CodeGen/X86/int-intrinsic.ll b/test/CodeGen/X86/int-intrinsic.ll
index 45a9b0f15c6..b253e6c5f3b 100644
--- a/test/CodeGen/X86/int-intrinsic.ll
+++ b/test/CodeGen/X86/int-intrinsic.ll
@@ -11,7 +11,7 @@ bb.entry:
   ret void
 }
 
-; CHECK: int	$-128
+; CHECK: int	$128
 ; CHECK: ret
 define void @primitive_int128 () {
 bb.entry:
diff --git a/test/MC/X86/validate-inst-att.s b/test/MC/X86/validate-inst-att.s
index dec8bfdf660..61d5813613a 100644
--- a/test/MC/X86/validate-inst-att.s
+++ b/test/MC/X86/validate-inst-att.s
@@ -2,6 +2,11 @@
 
 	.text
 	int $65535
-# CHECK: error: interrupt vector must be in range [0-255]
+# CHECK: error: invalid operand for instruction
 # CHECK:	int $65535
+# CHECK:            ^
+
+	int $-129
+# CHECK: error: invalid operand for instruction
+# CHECK:	int $-129
 # CHECK:            ^
diff --git a/test/MC/X86/validate-inst-intel.s b/test/MC/X86/validate-inst-intel.s
index 9a7d122ca78..466b906fee7 100644
--- a/test/MC/X86/validate-inst-intel.s
+++ b/test/MC/X86/validate-inst-intel.s
@@ -3,7 +3,13 @@
 
 	.text
 	int 65535
-# CHECK: error: interrupt vector must be in range [0-255]
+# CHECK: error: invalid operand for instruction
 # CHECK:	int 65535
+# CHECK:            ^
+
+	.text
+	int -129
+# CHECK: error: invalid operand for instruction
+# CHECK:	int -129
 # CHECK:            ^