From: Owen Anderson <resistor@mac.com>
Date: Sat, 5 Jan 2008 00:48:55 +0000 (+0000)
Subject: I should not be allowed to commit when sleepy.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=a393cd3306b865e8e5d82dc4e6cfabcdf5d8dc44

I should not be allowed to commit when sleepy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45608 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 9c3912350f2..bd299142b27 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -249,7 +249,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
   // code into the entry block.
   MachineBasicBlock *MBB = Fn.begin();
   MachineBasicBlock::iterator I = MBB->begin();
-  if (!RegInfo->spillCalleeSavedRegisters(*MBB, I, CSI)) {
+  if (!TII.spillCalleeSavedRegisters(*MBB, I, CSI)) {
     for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
       // Add the callee-saved register as live-in. It's killed at the spill.
       MBB->addLiveIn(CSI[i].getReg());
@@ -280,7 +280,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
       
       // Restore all registers immediately before the return and any terminators
       // that preceed it.
-      if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
+      if (!TII.restoreCalleeSavedRegisters(*MBB, I, CSI)) {
         for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
           TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
                                         CSI[i].getFrameIdx(),