From: Michael Liao <michael.liao@intel.com>
Date: Fri, 19 Oct 2012 03:17:00 +0000 (+0000)
Subject: Simplify condition checking as CONCAT assume all inputs of the same type.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=9aecdb51c743f13f88748ef3c539a3e6e6df9e99;ds=sidebyside

Simplify condition checking as CONCAT assume all inputs of the same type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166260 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 22270968e3f..17386b74e36 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8629,9 +8629,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
     //    (extract_subvec (concat V1, V2, ...), i)
     // Into:
     //    Vi if possible
-    for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
-      if (V->getOperand(i).getValueType() != NVT)
-        return SDValue();
+    // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
+    if (V->getOperand(0).getValueType() != NVT)
+      return SDValue();
     unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
     unsigned NumElems = NVT.getVectorNumElements();
     assert((Idx % NumElems) == 0 &&