From: Dan Gohman <dan433584@gmail.com>
Date: Mon, 23 Nov 2015 21:16:35 +0000 (+0000)
Subject: [WebAssembly] Model the return value of store instructions in wasm.
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=9a9e26b34f676c4ffcc94e0dacbcb338117736aa

[WebAssembly] Model the return value of store instructions in wasm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253916 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/WebAssembly/WebAssemblyInstrMemory.td b/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
index 6cc28a2db85..847eeeabc8c 100644
--- a/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
+++ b/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
@@ -76,36 +76,47 @@ def : Pat<(i64 (extloadi16 I32:$addr)), (LOAD16_U_I64 $addr)>;
 def : Pat<(i64 (extloadi32 I32:$addr)), (LOAD32_U_I64 $addr)>;
 
 // Basic store.
+// Note that we split the patterns out of the instruction definitions because
+// WebAssembly's stores return their operand value, and tablegen doesn't like
+// instruction definition patterns that don't reference all of the output
+// operands.
 // Note: WebAssembly inverts SelectionDAG's usual operand order.
-def STORE_I32  : I<(outs), (ins I32:$addr, I32:$val),
-                   [(store i32:$val, I32:$addr)],
-                   "i32.store\t$addr, $val">;
-def STORE_I64  : I<(outs), (ins I32:$addr, I64:$val),
-                   [(store i64:$val, I32:$addr)],
-                   "i64.store\t$addr, $val">;
-def STORE_F32  : I<(outs), (ins I32:$addr, F32:$val),
-                   [(store f32:$val, I32:$addr)],
-                   "f32.store\t$addr, $val">;
-def STORE_F64  : I<(outs), (ins I32:$addr, F64:$val),
-                   [(store f64:$val, I32:$addr)],
-                   "f64.store\t$addr, $val">;
+def STORE_I32  : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
+                   "i32.store\t$dst, $addr, $val">;
+def STORE_I64  : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
+                   "i64.store\t$dst, $addr, $val">;
+def STORE_F32  : I<(outs F32:$dst), (ins I32:$addr, F32:$val), [],
+                   "f32.store\t$dst, $addr, $val">;
+def STORE_F64  : I<(outs F64:$dst), (ins I32:$addr, F64:$val), [],
+                   "f64.store\t$dst, $addr, $val">;
+
+def : Pat<(store I32:$val, I32:$addr), (STORE_I32 I32:$addr, I32:$val)>;
+def : Pat<(store I64:$val, I32:$addr), (STORE_I64 I32:$addr, I64:$val)>;
+def : Pat<(store F32:$val, I32:$addr), (STORE_F32 I32:$addr, F32:$val)>;
+def : Pat<(store F64:$val, I32:$addr), (STORE_F64 I32:$addr, F64:$val)>;
 
 // Truncating store.
-def STORE8_I32  : I<(outs), (ins I32:$addr, I32:$val),
-                    [(truncstorei8 I32:$val, I32:$addr)],
-                    "i32.store8\t$addr, $val">;
-def STORE16_I32 : I<(outs), (ins I32:$addr, I32:$val),
-                    [(truncstorei16 I32:$val, I32:$addr)],
-                    "i32.store16\t$addr, $val">;
-def STORE8_I64  : I<(outs), (ins I32:$addr, I64:$val),
-                    [(truncstorei8 I64:$val, I32:$addr)],
-                    "i64.store8\t$addr, $val">;
-def STORE16_I64 : I<(outs), (ins I32:$addr, I64:$val),
-                    [(truncstorei16 I64:$val, I32:$addr)],
-                    "i64.store16\t$addr, $val">;
-def STORE32_I64 : I<(outs), (ins I32:$addr, I64:$val),
-                    [(truncstorei32 I64:$val, I32:$addr)],
-                    "i64.store32\t$addr, $val">;
+def STORE8_I32  : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
+                    "i32.store8\t$dst, $addr, $val">;
+def STORE16_I32 : I<(outs I32:$dst), (ins I32:$addr, I32:$val), [],
+                    "i32.store16\t$dst, $addr, $val">;
+def STORE8_I64  : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
+                    "i64.store8\t$dst, $addr, $val">;
+def STORE16_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
+                    "i64.store16\t$dst, $addr, $val">;
+def STORE32_I64 : I<(outs I64:$dst), (ins I32:$addr, I64:$val), [],
+                    "i64.store32\t$dst, $addr, $val">;
+
+def : Pat<(truncstorei8 I32:$val, I32:$addr),
+          (STORE8_I32 I32:$addr, I32:$val)>;
+def : Pat<(truncstorei16 I32:$val, I32:$addr),
+          (STORE16_I32 I32:$addr, I32:$val)>;
+def : Pat<(truncstorei8 I64:$val, I32:$addr),
+          (STORE8_I64 I32:$addr, I64:$val)>;
+def : Pat<(truncstorei16 I64:$val, I32:$addr),
+          (STORE16_I64 I32:$addr, I64:$val)>;
+def : Pat<(truncstorei32 I64:$val, I32:$addr),
+          (STORE32_I64 I32:$addr, I64:$val)>;
 
 // Memory size.
 def MEMORY_SIZE_I32 : I<(outs I32:$dst), (ins),
diff --git a/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp b/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
index bf21024a731..b497612b54e 100644
--- a/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
+++ b/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
@@ -137,6 +137,9 @@ bool WebAssemblyRegColoring::runOnMachineFunction(MachineFunction &MF) {
     unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
     if (MFI.isVRegStackified(VReg))
       continue;
+    // Skip unused registers, which can use $discard.
+    if (MRI->use_empty(VReg))
+      continue;
 
     LiveInterval *LI = &Liveness->getInterval(VReg);
     assert(LI->weight == 0.0f);
diff --git a/test/CodeGen/WebAssembly/cfg-stackify.ll b/test/CodeGen/WebAssembly/cfg-stackify.ll
index e62a8c88ef9..742c42c22e5 100644
--- a/test/CodeGen/WebAssembly/cfg-stackify.ll
+++ b/test/CodeGen/WebAssembly/cfg-stackify.ll
@@ -184,7 +184,7 @@ entry:
 ; CHECK-LABEL: minimal_loop:
 ; CHECK-NOT: br
 ; CHECK: BB7_1:
-; CHECK: i32.store $0, $pop{{[0-9]+}}{{$}}
+; CHECK: i32.store $discard, $0, $pop{{[0-9]+}}{{$}}
 ; CHECK: br BB7_1{{$}}
 ; CHECK: BB7_2:
 define i32 @minimal_loop(i32* %p) {
diff --git a/test/CodeGen/WebAssembly/load-store-i1.ll b/test/CodeGen/WebAssembly/load-store-i1.ll
index b4dc90b2257..4d894d96bc4 100644
--- a/test/CodeGen/WebAssembly/load-store-i1.ll
+++ b/test/CodeGen/WebAssembly/load-store-i1.ll
@@ -50,7 +50,7 @@ define i64 @load_s_i1_i64(i1* %p) {
 ; CHECK-LABEL: store_i32_i1:
 ; CHECK:      i32.const $push[[NUM0:[0-9]+]], 1{{$}}
 ; CHECK-NEXT: i32.and $push[[NUM1:[0-9]+]], $1, $pop[[NUM0]]{{$}}
-; CHECK-NEXT: i32.store8 $0, $pop[[NUM1]]{{$}}
+; CHECK-NEXT: i32.store8 $discard, $0, $pop[[NUM1]]{{$}}
 define void @store_i32_i1(i1* %p, i32 %v) {
   %t = trunc i32 %v to i1
   store i1 %t, i1* %p
@@ -60,7 +60,7 @@ define void @store_i32_i1(i1* %p, i32 %v) {
 ; CHECK-LABEL: store_i64_i1:
 ; CHECK:      i64.const $push[[NUM0:[0-9]+]], 1{{$}}
 ; CHECK-NEXT: i64.and $push[[NUM1:[0-9]+]], $1, $pop[[NUM0]]{{$}}
-; CHECK-NEXT: i64.store8 $0, $pop[[NUM1]]{{$}}
+; CHECK-NEXT: i64.store8 $discard, $0, $pop[[NUM1]]{{$}}
 define void @store_i64_i1(i1* %p, i64 %v) {
   %t = trunc i64 %v to i1
   store i1 %t, i1* %p
diff --git a/test/CodeGen/WebAssembly/store-trunc.ll b/test/CodeGen/WebAssembly/store-trunc.ll
index a4fe3b0121f..c5a47a482a2 100644
--- a/test/CodeGen/WebAssembly/store-trunc.ll
+++ b/test/CodeGen/WebAssembly/store-trunc.ll
@@ -6,7 +6,7 @@ target datalayout = "e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: trunc_i8_i32:
-; CHECK: i32.store8 $0, $1{{$}}
+; CHECK: i32.store8 $discard, $0, $1{{$}}
 define void @trunc_i8_i32(i8 *%p, i32 %v) {
   %t = trunc i32 %v to i8
   store i8 %t, i8* %p
@@ -14,7 +14,7 @@ define void @trunc_i8_i32(i8 *%p, i32 %v) {
 }
 
 ; CHECK-LABEL: trunc_i16_i32:
-; CHECK: i32.store16 $0, $1{{$}}
+; CHECK: i32.store16 $discard, $0, $1{{$}}
 define void @trunc_i16_i32(i16 *%p, i32 %v) {
   %t = trunc i32 %v to i16
   store i16 %t, i16* %p
@@ -22,7 +22,7 @@ define void @trunc_i16_i32(i16 *%p, i32 %v) {
 }
 
 ; CHECK-LABEL: trunc_i8_i64:
-; CHECK: i64.store8 $0, $1{{$}}
+; CHECK: i64.store8 $discard, $0, $1{{$}}
 define void @trunc_i8_i64(i8 *%p, i64 %v) {
   %t = trunc i64 %v to i8
   store i8 %t, i8* %p
@@ -30,7 +30,7 @@ define void @trunc_i8_i64(i8 *%p, i64 %v) {
 }
 
 ; CHECK-LABEL: trunc_i16_i64:
-; CHECK: i64.store16 $0, $1{{$}}
+; CHECK: i64.store16 $discard, $0, $1{{$}}
 define void @trunc_i16_i64(i16 *%p, i64 %v) {
   %t = trunc i64 %v to i16
   store i16 %t, i16* %p
@@ -38,7 +38,7 @@ define void @trunc_i16_i64(i16 *%p, i64 %v) {
 }
 
 ; CHECK-LABEL: trunc_i32_i64:
-; CHECK: i64.store32 $0, $1{{$}}
+; CHECK: i64.store32 $discard, $0, $1{{$}}
 define void @trunc_i32_i64(i32 *%p, i64 %v) {
   %t = trunc i64 %v to i32
   store i32 %t, i32* %p
diff --git a/test/CodeGen/WebAssembly/store.ll b/test/CodeGen/WebAssembly/store.ll
index 02af54ec970..f24824f5f0b 100644
--- a/test/CodeGen/WebAssembly/store.ll
+++ b/test/CodeGen/WebAssembly/store.ll
@@ -7,7 +7,7 @@ target triple = "wasm32-unknown-unknown"
 
 ; CHECK-LABEL: sti32:
 ; CHECK-NEXT: .param i32, i32{{$}}
-; CHECK-NEXT: i32.store $0, $1{{$}}
+; CHECK-NEXT: i32.store $discard, $0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti32(i32 *%p, i32 %v) {
   store i32 %v, i32* %p
@@ -16,7 +16,7 @@ define void @sti32(i32 *%p, i32 %v) {
 
 ; CHECK-LABEL: sti64:
 ; CHECK-NEXT: .param i32, i64{{$}}
-; CHECK-NEXT: i64.store $0, $1{{$}}
+; CHECK-NEXT: i64.store $discard, $0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @sti64(i64 *%p, i64 %v) {
   store i64 %v, i64* %p
@@ -25,7 +25,7 @@ define void @sti64(i64 *%p, i64 %v) {
 
 ; CHECK-LABEL: stf32:
 ; CHECK-NEXT: .param i32, f32{{$}}
-; CHECK-NEXT: f32.store $0, $1{{$}}
+; CHECK-NEXT: f32.store $discard, $0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf32(float *%p, float %v) {
   store float %v, float* %p
@@ -34,7 +34,7 @@ define void @stf32(float *%p, float %v) {
 
 ; CHECK-LABEL: stf64:
 ; CHECK-NEXT: .param i32, f64{{$}}
-; CHECK-NEXT: f64.store $0, $1{{$}}
+; CHECK-NEXT: f64.store $discard, $0, $1{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @stf64(double *%p, double %v) {
   store double %v, double* %p