From: Dale Johannesen <dalej@apple.com>
Date: Thu, 11 Oct 2007 20:58:37 +0000 (+0000)
Subject: Add missing argument to PALIGNR
X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=83e105c600159e8d33fa3c421a163c1850483cfd

Add missing argument to PALIGNR



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42874 91177308-0d34-0410-b5e6-96231b3b80d8
---

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index f2795fff743..bbcc7530d59 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -2598,14 +2598,14 @@ defm PSIGND      : SS3I_binop_rm_int_32<0x09, "psignd",
 let isTwoAddress = 1 in {
   def PALIGNR64rr  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, VR64:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1, VR64:$src2,
                               imm:$src3))]>;
   def PALIGNR64rm  : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
                            (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR64:$dst,
                              (int_x86_ssse3_palign_r
                               VR64:$src1,
@@ -2614,14 +2614,14 @@ let isTwoAddress = 1 in {
 
   def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, VR128:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1, VR128:$src2,
                               imm:$src3))]>, OpSize;
   def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
                            (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
-                           "palignr\t{$src2, $dst|$dst, $src2}",
+                           "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                            [(set VR128:$dst,
                              (int_x86_ssse3_palign_r_128
                               VR128:$src1,