From: Daniel Sanders Date: Mon, 8 Feb 2016 14:14:18 +0000 (+0000) Subject: [mips] Add initial release notes for MIPS32. X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=7ecd92d75cda45668b6b5fdbcdd2142826514e66;hp=ff65de018b6bb5bc4da3e923bbc0f55c5ca8e039 [mips] Add initial release notes for MIPS32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@260095 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/docs/ReleaseNotes.rst b/docs/ReleaseNotes.rst index dccb7f4d1cc..2e41223f186 100644 --- a/docs/ReleaseNotes.rst +++ b/docs/ReleaseNotes.rst @@ -107,8 +107,63 @@ Changes to the ARM Backend Changes to the MIPS Target -------------------------- - During this release ... - +During this release the MIPS target has: + +* Significantly extended support for the Integrated Assembler. See below for + more information +* Added support for the ``P5600`` processor. +* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This + attribute will generate a function which can be used as a interrupt handler + on bare metal MIPS targets using the static relocation model. +* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later. +* Added support for OpenCL. See http://portablecl.org/. + + * Address spaces 1 to 255 are now reserved for software use and conversions + between them are no-op casts. + +* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE + (Application Specific Extension)` and not a processor. If you were using this, + please specify another CPU and use ``-mips16`` to enable MIPS16. +* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since + they have been removed from the MSA specification due to forward compatibility + issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave + differently on a 64-bit processor supporting MSA. The corresponding intrinsics + are still available and may expand to ``copy_s.[wd]`` where this is + appropriate for forward compatibility purposes. +* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for + compatibility with GCC. +* Made MIPS64R6 the default CPU for 64-bit Android triples. + +The MIPS target has also fixed various bugs including the following notable +fixes: + +* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE + (Application Specific Extension)`. +* The code generator no longer uses ``jal`` for calls to absolute immediate + addresses. +* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not + yet supported. +* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT +* The code generator no longer crashes when handling subregisters of an 64-bit + FPU register with undefined value. +* The code generator no longer attempts to use ``$zero`` for operands that do + not permit ``$zero``. +* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and + the Integrated Assembler. +* Added support for atomic load and atomic store. +* Corrected debug info when dynamically re-aligning the stack. + +Integrated Assembler +^^^^^^^^^^^^^^^^^^^^ +We have made a large number of improvements to the integrated assembler for +MIPS. In this release, the integrated assembler isn't quite production-ready +since there are a few known issues related to bare-metal support, checking +immediates on instructions, and the N32/N64 ABI's. However, the current support +should be sufficient for many users of the O32 ABI, particularly those targeting +MIPS32 on Linux or bare-metal MIPS32. + +If you would like to try the integrated assembler, please use +``-fintegrated-as``. Changes to the PowerPC Target -----------------------------