From: Artyom Skrobov Date: Fri, 20 Nov 2015 16:46:09 +0000 (+0000) Subject: Handle ARMv6-J as an alias, instead of fake architecture X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=7cbf72b4896c055cae285d7e488b8de18aa835f7 Handle ARMv6-J as an alias, instead of fake architecture Summary: This follows D14577 to treat ARMv6-J as an alias for ARMv6, instead of an architecture in its own right. The functional change is that the default CPU when targeting ARMv6-J changes from arm1136j-s to arm1136jf-s, which is currently used as the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs. The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't affect code generation, attributes, optimizations, or anything else, apart from selecting the default CPU. Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14755 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253675 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/include/llvm/Support/ARMTargetParser.def b/include/llvm/Support/ARMTargetParser.def index 3a72842145b..3edc34c8eda 100644 --- a/include/llvm/Support/ARMTargetParser.def +++ b/include/llvm/Support/ARMTargetParser.def @@ -95,8 +95,6 @@ ARM_ARCH("iwmmxt2", AK_IWMMXT2, "iwmmxt2", "", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, AEK_NONE) ARM_ARCH("xscale", AK_XSCALE, "xscale", "", ARMBuildAttrs::CPUArch::v5TE, FK_NONE, AEK_NONE) -ARM_ARCH("armv6j", AK_ARMV6J, "6J", "v6", ARMBuildAttrs::CPUArch::v6, - FK_NONE, AEK_DSP) ARM_ARCH("armv7s", AK_ARMV7S, "7-S", "v7s", ARMBuildAttrs::CPUArch::v7, FK_NEON_VFPV4, AEK_DSP) ARM_ARCH("armv7k", AK_ARMV7K, "7-K", "v7k", ARMBuildAttrs::CPUArch::v7, @@ -169,7 +167,9 @@ ARM_CPU_NAME("arm10e", AK_ARMV5TE, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("arm1020e", AK_ARMV5TE, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("arm1022e", AK_ARMV5TE, FK_NONE, true, AEK_NONE) ARM_CPU_NAME("arm926ej-s", AK_ARMV5TEJ, FK_NONE, true, AEK_NONE) +ARM_CPU_NAME("arm1136j-s", AK_ARMV6, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("arm1136jf-s", AK_ARMV6, FK_VFPV2, true, AEK_NONE) +ARM_CPU_NAME("arm1136jz-s", AK_ARMV6, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, true, AEK_NONE) ARM_CPU_NAME("arm1176jz-s", AK_ARMV6KZ, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("mpcore", AK_ARMV6K, FK_VFPV2, false, AEK_NONE) @@ -211,8 +211,6 @@ ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC) // Non-standard Arch names. ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, AEK_NONE) ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, AEK_NONE) -ARM_CPU_NAME("arm1136j-s", AK_ARMV6J, FK_NONE, true, AEK_NONE) -ARM_CPU_NAME("arm1136jz-s", AK_ARMV6J, FK_NONE, false, AEK_NONE) ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true, (AEK_HWDIVARM | AEK_HWDIV)) ARM_CPU_NAME("cortex-a7", AK_ARMV7K, FK_NONE, true, AEK_HWDIVARM | AEK_HWDIV) diff --git a/lib/Support/TargetParser.cpp b/lib/Support/TargetParser.cpp index 75e4b4bed56..3aa55b3c885 100644 --- a/lib/Support/TargetParser.cpp +++ b/lib/Support/TargetParser.cpp @@ -400,6 +400,7 @@ static StringRef getArchSynonym(StringRef Arch) { return StringSwitch(Arch) .Case("v5", "v5t") .Case("v5e", "v5te") + .Case("v6j", "v6") .Case("v6hl", "v6k") .Cases("v6m", "v6sm", "v6s-m", "v6-m") .Cases("v6z", "v6zk", "v6kz") @@ -579,7 +580,6 @@ unsigned llvm::ARM::parseArchVersion(StringRef Arch) { case ARM::AK_ARMV5TEJ: return 5; case ARM::AK_ARMV6: - case ARM::AK_ARMV6J: case ARM::AK_ARMV6K: case ARM::AK_ARMV6T2: case ARM::AK_ARMV6KZ: diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp index b03643337e8..8163b6fee43 100644 --- a/lib/Support/Triple.cpp +++ b/lib/Support/Triple.cpp @@ -496,7 +496,6 @@ static Triple::SubArchType parseSubArch(StringRef SubArchName) { case ARM::AK_ARMV5TEJ: return Triple::ARMSubArch_v5te; case ARM::AK_ARMV6: - case ARM::AK_ARMV6J: return Triple::ARMSubArch_v6; case ARM::AK_ARMV6K: case ARM::AK_ARMV6KZ: diff --git a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp index 7fee704c35b..42591c25d6e 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -710,7 +710,6 @@ void ARMTargetELFStreamer::emitArchDefaultAttributes() { case ARM::AK_ARMV5T: case ARM::AK_ARMV5TE: case ARM::AK_ARMV6: - case ARM::AK_ARMV6J: setAttributeItem(ARM_ISA_use, Allowed, false); setAttributeItem(THUMB_ISA_use, Allowed, false); break; diff --git a/test/MC/ARM/directive-arch-armv6j.s b/test/MC/ARM/directive-arch-armv6j.s deleted file mode 100644 index e27beef1eba..00000000000 --- a/test/MC/ARM/directive-arch-armv6j.s +++ /dev/null @@ -1,34 +0,0 @@ -@ Test the .arch directive for armv6j - -@ This test case will check the default .ARM.attributes value for the -@ armv6j architecture. - -@ RUN: llvm-mc -triple arm-eabi -filetype asm %s \ -@ RUN: | FileCheck %s -check-prefix CHECK-ASM -@ RUN: llvm-mc -triple arm-eabi -filetype obj %s \ -@ RUN: | llvm-readobj -arm-attributes | FileCheck %s -check-prefix CHECK-ATTR - - .syntax unified - .arch armv6j - -@ CHECK-ASM: .arch armv6j - -@ CHECK-ATTR: FileAttributes { -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: CPU_name -@ CHECK-ATTR: Value: 6J -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: CPU_arch -@ CHECK-ATTR: Description: ARM v6 -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: ARM_ISA_use -@ CHECK-ATTR: Description: Permitted -@ CHECK-ATTR: } -@ CHECK-ATTR: Attribute { -@ CHECK-ATTR: TagName: THUMB_ISA_use -@ CHECK-ATTR: Description: Thumb-1 -@ CHECK-ATTR: } -@ CHECK-ATTR: } - diff --git a/unittests/ADT/TripleTest.cpp b/unittests/ADT/TripleTest.cpp index ff29b64ea07..ac4fa2274e9 100644 --- a/unittests/ADT/TripleTest.cpp +++ b/unittests/ADT/TripleTest.cpp @@ -852,7 +852,7 @@ TEST(TripleTest, getARMCPUForArch) { } { llvm::Triple Triple("armv6j-unknown-eabi"); - EXPECT_EQ("arm1136j-s", Triple.getARMCPUForArch()); + EXPECT_EQ("arm1136jf-s", Triple.getARMCPUForArch()); } { llvm::Triple Triple("armv6k-unknown-eabi");