From: Daniel Sanders Date: Mon, 16 Jun 2014 13:18:59 +0000 (+0000) Subject: [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=commitdiff_plain;h=77ae274ae7fb3ca1fe26147a64efd323e59fbd8c [mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211019 91177308-0d34-0410-b5e6-96231b3b80d8 --- diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index 697d550615c..051db7525f6 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -91,6 +91,10 @@ def OPCODE6_LL : OPCODE6<0b110110>; def OPCODE6_LLD : OPCODE6<0b110111>; def OPCODE6_SC : OPCODE6<0b100110>; def OPCODE6_SCD : OPCODE6<0b100111>; +def OPCODE6_CLO : OPCODE6<0b010001>; +def OPCODE6_CLZ : OPCODE6<0b010000>; +def OPCODE6_DCLO : OPCODE6<0b010011>; +def OPCODE6_DCLZ : OPCODE6<0b010010>; class FIELD_FMT Val> { bits<5> Value = Val; @@ -293,6 +297,20 @@ class SPECIAL3_MEM_FM : MipsR6Inst { let Inst{5-0} = Operation.Value; } +class SPECIAL_2R_FM : MipsR6Inst { + bits<5> rd; + bits<5> rs; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_SPECIAL.Value; + let Inst{25-21} = rs; + let Inst{20-16} = 0b00000; + let Inst{15-11} = rd; + let Inst{10-6} = 0b00001; + let Inst{5-0} = Operation.Value; +} + class SPECIAL_3R_FM mulop, bits<6> funct> : MipsR6Inst { bits<5> rd; bits<5> rs; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index e2f703b1cc6..cc0a595f1cb 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -15,7 +15,6 @@ include "Mips32r6InstrFormats.td" // Notes about removals/changes from MIPS32r6: // Unclear: ssnop -// Reencoded: clo, clz // Reencoded: jr -> jalr // Reencoded: jr.hb -> jalr.hb // Reencoded: sdbbp @@ -160,6 +159,9 @@ class SWC2_R6_ENC : COP2LDST_FM; class LL_R6_ENC : SPECIAL3_LL_SC_FM; class SC_R6_ENC : SPECIAL3_LL_SC_FM; +class CLO_R6_ENC : SPECIAL_2R_FM; +class CLZ_R6_ENC : SPECIAL_2R_FM; + class CMP_CONDN_DESC_BASE { @@ -586,6 +588,25 @@ class SC_R6_DESC_BASE { class SC_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd>; +class CLO_CLZ_R6_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rd); + dag InOperandList = (ins GPROpnd:$rs); + string AsmString = !strconcat(instr_asm, "\t$rd, $rs"); +} + +class CLO_R6_DESC_BASE : + CLO_CLZ_R6_DESC_BASE { + list Pattern = [(set GPROpnd:$rd, (ctlz (not GPROpnd:$rs)))]; +} + +class CLZ_R6_DESC_BASE : + CLO_CLZ_R6_DESC_BASE { + list Pattern = [(set GPROpnd:$rd, (ctlz GPROpnd:$rs))]; +} + +class CLO_R6_DESC : CLO_R6_DESC_BASE<"clo", GPR32Opnd>; +class CLZ_R6_DESC : CLZ_R6_DESC_BASE<"clz", GPR32Opnd>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -628,6 +649,8 @@ def BOVC : BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; def CACHE_R6 : CACHE_ENC, CACHE_DESC, ISA_MIPS32R6; def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; +def CLO_R6 : CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; +def CLZ_R6 : CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; defm S : CMP_CC_M; defm D : CMP_CC_M; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 1e14d0ea2b3..88422ce19de 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -225,8 +225,8 @@ def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, } /// Count Leading -def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64; -def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64; +def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; +def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; /// Double Word Swap Bytes/HalfWords def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 78cca109cfe..dbfb9fbbf9b 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -25,6 +25,8 @@ class DAUI_ENC : DAUI_FM; class DAHI_ENC : REGIMM_FM; class DATI_ENC : REGIMM_FM; class DBITSWAP_ENC : SPECIAL3_2R_FM; +class DCLO_R6_ENC : SPECIAL_2R_FM; +class DCLZ_R6_ENC : SPECIAL_2R_FM; class DDIV_ENC : SPECIAL_3R_FM<0b00010, 0b011110>; class DDIVU_ENC : SPECIAL_3R_FM<0b00010, 0b011111>; class DMOD_ENC : SPECIAL_3R_FM<0b00011, 0b011110>; @@ -55,6 +57,8 @@ class DAHI_DESC : AHI_ATI_DESC_BASE<"dahi", GPR64Opnd>; class DATI_DESC : AHI_ATI_DESC_BASE<"dati", GPR64Opnd>; class DAUI_DESC : AUI_DESC_BASE<"daui", GPR64Opnd>; class DBITSWAP_DESC : BITSWAP_DESC_BASE<"dbitswap", GPR64Opnd>; +class DCLO_R6_DESC : CLO_R6_DESC_BASE<"dclo", GPR64Opnd>; +class DCLZ_R6_DESC : CLZ_R6_DESC_BASE<"dclz", GPR64Opnd>; class DDIV_DESC : DIVMOD_DESC_BASE<"ddiv", GPR64Opnd, sdiv>; class DDIVU_DESC : DIVMOD_DESC_BASE<"ddivu", GPR64Opnd, udiv>; class DMOD_DESC : DIVMOD_DESC_BASE<"dmod", GPR64Opnd, srem>; @@ -80,6 +84,8 @@ def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; +def DCLO_R6 : DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; +def DCLZ_R6 : DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; // def DLSA; // See MSA diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 4df962282e3..6e8e4980109 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -240,6 +240,9 @@ class ISA_MIPS32R2_NOT_32R6_64R6 { list InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6]; } class ISA_MIPS64 { list InsnPredicates = [HasMips64]; } +class ISA_MIPS64_NOT_64R6 { + list InsnPredicates = [HasMips64, NotMips64r6]; +} class ISA_MIPS64R2 { list InsnPredicates = [HasMips64r2]; } class ISA_MIPS32R6 { list InsnPredicates = [HasMips32r6]; } class ISA_MIPS64R6 { list InsnPredicates = [HasMips64r6]; } @@ -1277,8 +1280,10 @@ def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>, ISA_MIPS32R2; /// Count Leading -def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32; -def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32; +def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, + ISA_MIPS32_NOT_32R6_64R6; +def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, + ISA_MIPS32_NOT_32R6_64R6; /// Word Swap Bytes Within Halfwords def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2; diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index 4965fee75ad..bff656ff125 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -158,7 +158,10 @@ public: bool hasMips3() const { return MipsArchVersion >= Mips3; } bool hasMips4_32() const { return HasMips4_32; } bool hasMips4_32r2() const { return HasMips4_32r2; } - bool hasMips32() const { return MipsArchVersion >= Mips32; } + bool hasMips32() const { + return MipsArchVersion >= Mips32 && MipsArchVersion != Mips3 && + MipsArchVersion != Mips4 && MipsArchVersion != Mips5; + } bool hasMips32r2() const { return MipsArchVersion == Mips32r2 || MipsArchVersion == Mips32r6 || MipsArchVersion == Mips64r2 || MipsArchVersion == Mips64r6; diff --git a/test/CodeGen/Mips/countleading.ll b/test/CodeGen/Mips/countleading.ll new file mode 100644 index 00000000000..81fb2b44942 --- /dev/null +++ b/test/CodeGen/Mips/countleading.ll @@ -0,0 +1,90 @@ +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s + +; Prefixes: +; ALL - All +; MIPS32-GT-R1 - MIPS64r1 and above (does not include MIPS64's) +; MIPS64-GT-R1 - MIPS64r1 and above + +define i32 @ctlz_i32(i32 %X) nounwind readnone { +entry: +; ALL-LABEL: ctlz_i32: + +; MIPS4-NOT: clz + +; MIPS32-GT-R1: clz $2, $4 + +; MIPS64-GT-R1: clz $2, $4 + + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) + ret i32 %tmp1 +} + +declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone + +define i32 @ctlo_i32(i32 %X) nounwind readnone { +entry: +; ALL-LABEL: ctlo_i32: + +; MIPS4-NOT: clo + +; MIPS32-GT-R1: clo $2, $4 + +; MIPS64-GT-R1: clo $2, $4 + + %neg = xor i32 %X, -1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) + ret i32 %tmp1 +} + +define i64 @ctlz_i64(i64 %X) nounwind readnone { +entry: +; ALL-LABEL: ctlz_i64: + +; MIPS4-NOT: dclz + +; MIPS32-GT-R1-DAG: clz $[[R0:[0-9]+]], $4 +; MIPS32-GT-R1-DAG: clz $[[R1:[0-9]+]], $5 +; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 +; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $5 +; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R2]], $5 +; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R1]], $5 +; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]] +; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 + +; MIPS64-GT-R1: dclz $2, $4 + + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) + ret i64 %tmp1 +} + +declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone + +define i64 @ctlo_i64(i64 %X) nounwind readnone { +entry: +; ALL-LABEL: ctlo_i64: + +; MIPS4-NOT: dclo + +; MIPS32-GT-R1-DAG: clo $[[R0:[0-9]+]], $4 +; MIPS32-GT-R1-DAG: clo $[[R1:[0-9]+]], $5 +; MIPS32-GT-R1-DAG: addiu $[[R2:2+]], $[[R0]], 32 +; MIPS32-GT-R1-DAG: addiu $[[R3:[0-9]+]], $zero, -1 +; MIPS32-GT-R1-DAG: xor $[[R4:[0-9]+]], $5, $[[R3]] +; MIPS32-R1-R2-DAG: movn $[[R2]], $[[R1]], $[[R4]] +; MIPS32-R6-DAG: selnez $[[R5:[0-9]+]], $[[R1]], $[[R4]] +; MIPS32-R6-DAG: seleqz $[[R6:[0-9]+]], $[[R2]], $[[R4]] +; MIPS32-R6-DAG: or $2, $[[R5]], $[[R6]] +; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 + +; MIPS64-GT-R1: dclo $2, $4 + + %neg = xor i64 %X, -1 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) + ret i64 %tmp1 +} diff --git a/test/CodeGen/Mips/mips64countleading.ll b/test/CodeGen/Mips/mips64countleading.ll deleted file mode 100644 index 252f323fe1a..00000000000 --- a/test/CodeGen/Mips/mips64countleading.ll +++ /dev/null @@ -1,24 +0,0 @@ -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s - -define i64 @t1(i64 %X) nounwind readnone { -entry: -; CHECK-LABEL: t1: -; MIPS4-NOT: dclz -; MIPS64: dclz - %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) - ret i64 %tmp1 -} - -declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone - -define i64 @t3(i64 %X) nounwind readnone { -entry: -; CHECK-LABEL: t3: -; MIPS4-NOT: dclo -; MIPS64: dclo - %neg = xor i64 %X, -1 - %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) - ret i64 %tmp1 -} - diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll index cf0a0976f82..ed617be6532 100644 --- a/test/CodeGen/Mips/mips64instrs.ll +++ b/test/CodeGen/Mips/mips64instrs.ll @@ -1,5 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s -; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64 %s +; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s @gll0 = common global i64 0, align 8 @gll1 = common global i64 0, align 8 @@ -87,7 +89,10 @@ entry: define i64 @f12(i64 %a, i64 %b) nounwind readnone { entry: ; ALL-LABEL: f12: -; ALL: mult ${{[45]}}, ${{[45]}} + +; ACCMULDIV: mult ${{[45]}}, ${{[45]}} +; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} + %mul = mul nsw i64 %b, %a ret i64 %mul } @@ -95,7 +100,10 @@ entry: define i64 @f13(i64 %a, i64 %b) nounwind readnone { entry: ; ALL-LABEL: f13: -; ALL: mult ${{[45]}}, ${{[45]}} + +; ACCMULDIV: mult ${{[45]}}, ${{[45]}} +; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} + %mul = mul i64 %b, %a ret i64 %mul } @@ -107,9 +115,14 @@ entry: ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) -; ALL: ddiv $zero, $[[T0]], $[[T1]] -; ALL: teq $[[T1]], $zero, 7 -; ALL: mflo $2 + +; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]] +; ACCMULDIV: teq $[[T1]], $zero, 7 +; ACCMULDIV: mflo $2 + +; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]] +; GPRMULDIV: teq $[[T1]], $zero, 7 + %0 = load i64* @gll0, align 8 %1 = load i64* @gll1, align 8 %div = sdiv i64 %0, %1 @@ -123,9 +136,14 @@ entry: ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) -; ALL: ddivu $zero, $[[T0]], $[[T1]] -; ALL: teq $[[T1]], $zero, 7 -; ALL: mflo $2 + +; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]] +; ACCMULDIV: teq $[[T1]], $zero, 7 +; ACCMULDIV: mflo $2 + +; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]] +; GPRMULDIV: teq $[[T1]], $zero, 7 + %0 = load i64* @gll0, align 8 %1 = load i64* @gll1, align 8 %div = udiv i64 %0, %1 @@ -135,9 +153,14 @@ entry: define i64 @f16(i64 %a, i64 %b) nounwind readnone { entry: ; ALL-LABEL: f16: -; ALL: ddiv $zero, $4, $5 -; ALL: teq $5, $zero, 7 -; ALL: mfhi $2 + +; ACCMULDIV: ddiv $zero, $4, $5 +; ACCMULDIV: teq $5, $zero, 7 +; ACCMULDIV: mfhi $2 + +; GPRMULDIV: dmod $2, $4, $5 +; GPRMULDIV: teq $5, $zero, 7 + %rem = srem i64 %a, %b ret i64 %rem } @@ -145,9 +168,14 @@ entry: define i64 @f17(i64 %a, i64 %b) nounwind readnone { entry: ; ALL-LABEL: f17: -; ALL: ddivu $zero, $4, $5 -; ALL: teq $5, $zero, 7 -; ALL: mfhi $2 + +; ACCMULDIV: ddivu $zero, $4, $5 +; ACCMULDIV: teq $5, $zero, 7 +; ACCMULDIV: mfhi $2 + +; GPRMULDIV: dmodu $2, $4, $5 +; GPRMULDIV: teq $5, $zero, 7 + %rem = urem i64 %a, %b ret i64 %rem } @@ -161,7 +189,8 @@ entry: ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz ; MIPS4-NOT: dclz -; MIPS64: dclz $2, $4 +; HAS-DCLO: dclz $2, $4 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 } @@ -173,7 +202,8 @@ entry: ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo ; MIPS4-NOT: dclo -; MIPS64: dclo $2, $4 +; HAS-DCLO: dclo $2, $4 + %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) ret i64 %tmp1 diff --git a/test/MC/Disassembler/Mips/mips32r6.txt b/test/MC/Disassembler/Mips/mips32r6.txt index c6fcdcc607a..f64bcfd2a12 100644 --- a/test/MC/Disassembler/Mips/mips32r6.txt +++ b/test/MC/Disassembler/Mips/mips32r6.txt @@ -121,3 +121,5 @@ 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5 0x7e 0x42 0xb3 0xb6 # CHECK: ll $2, -153($18) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp diff --git a/test/MC/Disassembler/Mips/mips64r6.txt b/test/MC/Disassembler/Mips/mips64r6.txt index 8905a2c6aa5..a2ef0d6d8f2 100644 --- a/test/MC/Disassembler/Mips/mips64r6.txt +++ b/test/MC/Disassembler/Mips/mips64r6.txt @@ -137,3 +137,7 @@ 0x7f 0xe0 0x38 0x37 # CHECK: lld $zero, 112($ra) 0x7e 0x6f 0xec 0x26 # CHECK: sc $15, -40($19) 0x7f 0xaf 0xe6 0xa7 # CHECK: scd $15, -51($sp) +0x00 0xa0 0x58 0x51 # CHECK: clo $11, $5 +0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp +0x00 0xc0 0x90 0x53 # CHECK: dclo $18, $6 +0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25 diff --git a/test/MC/Mips/mips32/valid.s b/test/MC/Mips/mips32/valid.s index a362ae175bb..a2355ef9a65 100644 --- a/test/MC/Mips/mips32/valid.s +++ b/test/MC/Mips/mips32/valid.s @@ -29,8 +29,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.s $f22,$f28 cvt.d.w $f26,$f11 diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index b66fb16940c..c814788744d 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -29,8 +29,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.s $f22,$f28 cvt.d.w $f26,$f11 diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s index 6d459a81cd4..c20afdd7445 100644 --- a/test/MC/Mips/mips32r6/valid.s +++ b/test/MC/Mips/mips32r6/valid.s @@ -138,3 +138,5 @@ swc2 $25,304($s0) # CHECK: swc2 $25, 304($16) # encoding: [0x49,0x79,0x81,0x30] ll $v0,-153($s2) # CHECK: ll $2, -153($18) # encoding: [0x7e,0x42,0xb3,0xb6] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index df5dacc75a2..f7d882a4edc 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -31,8 +31,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.l $f4,$f16 cvt.d.s $f22,$f28 @@ -52,8 +52,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra - dclo $s2,$a2 - dclz $s0,$25 + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret ddiv $zero,$k0,$s3 ddivu $zero,$s0,$s1 diff --git a/test/MC/Mips/mips64r2/valid.s b/test/MC/Mips/mips64r2/valid.s index 4edd3d6b507..6ee24c2acec 100644 --- a/test/MC/Mips/mips64r2/valid.s +++ b/test/MC/Mips/mips64r2/valid.s @@ -31,8 +31,8 @@ ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 - clo $11,$a1 - clz $sp,$gp + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] ctc1 $a2,$26 cvt.d.l $f4,$f16 cvt.d.s $f22,$f28 @@ -52,8 +52,8 @@ daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] daddiu $k0,$s6,-4586 daddu $s3,$at,$ra - dclo $s2,$a2 - dclz $s0,$25 + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] deret di $s8 ddiv $zero,$k0,$s3 diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s index 99307f2b10d..970ced2b240 100644 --- a/test/MC/Mips/mips64r6/valid.s +++ b/test/MC/Mips/mips64r6/valid.s @@ -154,3 +154,7 @@ lld $zero,112($ra) # CHECK: lld $zero, 112($ra) # encoding: [0x7f,0xe0,0x38,0x37] sc $15,-40($s3) # CHECK: sc $15, -40($19) # encoding: [0x7e,0x6f,0xec,0x26] scd $15,-51($sp) # CHECK: scd $15, -51($sp) # encoding: [0x7f,0xaf,0xe6,0xa7] + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x00,0xa0,0x58,0x51] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x03,0x80,0xe8,0x50] + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x00,0xc0,0x90,0x53] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x03,0x20,0x80,0x52]